test: remove FHDLTestCase.assertRaisesRegex.

This method is only there because I misunderstood the documentation
of unittest.

diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py
index 4946c3eb8e0bf1886c7b003fdb7b814aa3a8743e..b724ad6fef3f1ed39ddf6a6fa8b924372eb6658d 100644 (file)
--- a/nmigen/test/test_hdl_ast.py
+++ b/nmigen/test/test_hdl_ast.py
@@ -764,13 +764,13 @@ class ArrayTestCase(FHDLTestCase):
         v1 = a[s1]
         v2 = a[s2]
         with self.assertRaisesRegex(ValueError,
-                regex=r"^Array can no longer be mutated after it was indexed with a value at "):
+                r"^Array can no longer be mutated after it was indexed with a value at "):
             a[1] = 2
         with self.assertRaisesRegex(ValueError,
-                regex=r"^Array can no longer be mutated after it was indexed with a value at "):
+                r"^Array can no longer be mutated after it was indexed with a value at "):
             del a[1]
         with self.assertRaisesRegex(ValueError,
-                regex=r"^Array can no longer be mutated after it was indexed with a value at "):
+                r"^Array can no longer be mutated after it was indexed with a value at "):
             a.insert(1, 2)
 
     def test_repr(self):

diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index a3a6913fa8190045e029ed7427565fade980112c..8f48207dd86119699d6ccd44bfd8a3b71792f3fc 100644 (file)
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -582,7 +582,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
             def process():
                 nonlocal survived
                 with self.assertRaisesRegex(TypeError,
-                        regex=r"Received unsupported command 1 from process .+?"):
+                        r"Received unsupported command 1 from process .+?"):
                     yield 1
                 yield Settle()
                 survived = True
@@ -774,7 +774,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
         sim.add_clock(1e-6)
         sim.run_until(1e-5)
         with self.assertRaisesRegex(ValueError,
-                regex=r"^Cannot start writing waveforms after advancing simulation time$"):
+                r"^Cannot start writing waveforms after advancing simulation time$"):
             with sim.write_vcd(open(os.path.devnull, "wt")):
                 pass
 
@@ -785,7 +785,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
         sim = Simulator(m)
         sim.add_clock(1e-6)
         with self.assertRaisesRegex(ValueError,
-                regex=r"^Already writing waveforms to .+$"):
+                r"^Already writing waveforms to .+$"):
             with sim.write_vcd(open(os.path.devnull, "wt")):
                 with sim.write_vcd(open(os.path.devnull, "wt")):
                     pass

diff --git a/nmigen/test/utils.py b/nmigen/test/utils.py
index c3907ce8b920a1231228961d471fb7d9f858f205..d8a168cb2f5de2b45e203f170f39f06d7b2ffa9a 100644 (file)
--- a/nmigen/test/utils.py
+++ b/nmigen/test/utils.py
@@ -36,14 +36,6 @@ class FHDLTestCase(unittest.TestCase):
             # WTF? unittest.assertRaises is completely broken.
             self.assertEqual(str(cm.exception), msg)
 
-    @contextmanager
-    def assertRaisesRegex(self, exception, regex=None):
-        with super().assertRaises(exception) as cm:
-            yield
-        if regex is not None:
-            # unittest.assertRaisesRegex also seems broken...
-            self.assertRegex(str(cm.exception), regex)
-
     @contextmanager
     def assertWarns(self, category, msg=None):
         with warnings.catch_warnings(record=True) as warns: