}
/* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
- for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+ if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
+ si_shader_ctx->key.color_two_side) {
LLVMValueRef args[3];
- LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
- unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
- args[0] = llvm_chan;
- args[1] = attr_number;
+ LLVMValueRef face, is_face_positive;
+ LLVMValueRef back_attr_number =
+ lp_build_const_int32(gallivm,
+ shader->input[input_index].param_offset + 1);
+
+ face = build_intrinsic(gallivm->builder,
+ "llvm.SI.fs.read.face",
+ input_type,
+ NULL, 0, LLVMReadNoneAttribute);
+ is_face_positive = LLVMBuildFCmp(gallivm->builder,
+ LLVMRealUGT, face,
+ lp_build_const_float(gallivm, 0.0f),
+ "");
+
args[2] = params;
- si_shader_ctx->radeon_bld.inputs[soa_index] =
- build_intrinsic(base->gallivm->builder, intr_name,
- input_type, args, 3, LLVMReadOnlyAttribute);
+ for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+ LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
+ unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
+ LLVMValueRef front, back;
+
+ args[0] = llvm_chan;
+ args[1] = attr_number;
+ front = build_intrinsic(base->gallivm->builder, intr_name,
+ input_type, args, 3, LLVMReadOnlyAttribute);
+
+ args[1] = back_attr_number;
+ back = build_intrinsic(base->gallivm->builder, intr_name,
+ input_type, args, 3, LLVMReadOnlyAttribute);
+
+ si_shader_ctx->radeon_bld.inputs[soa_index] =
+ LLVMBuildSelect(gallivm->builder,
+ is_face_positive,
+ front,
+ back,
+ "");
+ }
+
+ shader->ninterp++;
+ } else {
+ for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+ LLVMValueRef args[3];
+ LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
+ unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
+ args[0] = llvm_chan;
+ args[1] = attr_number;
+ args[2] = params;
+ si_shader_ctx->radeon_bld.inputs[soa_index] =
+ build_intrinsic(base->gallivm->builder, intr_name,
+ input_type, args, 3, LLVMReadOnlyAttribute);
+ }
}
}
break;
case TGSI_SEMANTIC_COLOR:
if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+ case TGSI_SEMANTIC_BCOLOR:
target = V_008DFC_SQ_EXP_PARAM + param_count;
shader->output[i].param_offset = param_count;
param_count++;
return NULL;
}
+ rs->two_side = state->light_twoside;
+
polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
state->fill_back != PIPE_POLYGON_MODE_FILL);
if (sel->fs_write_all)
key.nr_cbufs = rctx->framebuffer.nr_cbufs;
key.export_16bpc = rctx->export_16bpc;
- /*if (rctx->queued.named.rasterizer)
- key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
- /*key.color_two_side |== rctx->two_side;*/
+ if (rctx->queued.named.rasterizer) {
+ key.color_two_side = rctx->queued.named.rasterizer->two_side;
+ /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
+ }
}
return key;
unsigned i, j, tmp;
for (i = 0; i < ps->ninput; i++) {
+ unsigned name = ps->input[i].name;
+ unsigned param_offset = ps->input[i].param_offset;
+
+bcolor:
tmp = 0;
#if 0
/* XXX: Flat shading hangs the GPU */
- if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
+ if (name == TGSI_SEMANTIC_POSITION ||
ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
(ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
rctx->rasterizer && rctx->rasterizer->flatshade)) {
}
#endif
- if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
+ if (name == TGSI_SEMANTIC_GENERIC &&
rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
tmp |= S_028644_PT_SPRITE_TEX(1);
}
for (j = 0; j < vs->noutput; j++) {
- if (ps->input[i].name == vs->output[j].name &&
+ if (name == vs->output[j].name &&
ps->input[i].sid == vs->output[j].sid) {
tmp |= S_028644_OFFSET(vs->output[j].param_offset);
break;
}
si_pm4_set_reg(pm4,
- R_028644_SPI_PS_INPUT_CNTL_0 + ps->input[i].param_offset * 4,
+ R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
tmp);
+
+ if (name == TGSI_SEMANTIC_COLOR &&
+ rctx->ps_shader->current->key.color_two_side) {
+ name = TGSI_SEMANTIC_BCOLOR;
+ param_offset++;
+ goto bcolor;
+ }
}
si_pm4_set_state(rctx, spi, pm4);