gallium/radeon: read_registers should return bool meaning success or failure
authorMarek Olšák <marek.olsak@amd.com>
Sat, 22 Aug 2015 12:17:10 +0000 (14:17 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 26 Aug 2015 17:25:20 +0000 (19:25 +0200)
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
src/gallium/drivers/radeon/radeon_winsys.h
src/gallium/drivers/radeonsi/si_debug.c
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

index 7ab6e56e0991655a0ba71d30479a1e9cf16fe341..a4a2ae15acd64d2f3023287906803b7e9bf26966 100644 (file)
@@ -680,7 +680,7 @@ struct radeon_winsys {
     uint64_t (*query_value)(struct radeon_winsys *ws,
                             enum radeon_value_id value);
 
-    void (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
+    bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
                            unsigned num_registers, uint32_t *out);
 };
 
index 22d6f250b03cac8ed706eda8941f0e50588cd4cf..d3fd201ae262d70fbece18eeae141dcc75e0aada 100644 (file)
@@ -349,8 +349,8 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
        struct radeon_winsys *ws = sctx->b.ws;
        uint32_t value;
 
-       ws->read_registers(ws, offset, 1, &value);
-       si_dump_reg(f, offset, value, ~0);
+       if (ws->read_registers(ws, offset, 1, &value))
+               si_dump_reg(f, offset, value, ~0);
 }
 
 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
index 012c9003b69a273c34b01936e8225a86f1e21ca0..875dcd09c6b045bc0bd147766607ce3df32a4981 100644 (file)
@@ -350,14 +350,14 @@ static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
    return 0;
 }
 
-static void amdgpu_read_registers(struct radeon_winsys *rws,
+static bool amdgpu_read_registers(struct radeon_winsys *rws,
                                   unsigned reg_offset,
                                   unsigned num_registers, uint32_t *out)
 {
    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 
-   amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
-                            0xffffffff, 0, out);
+   return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
+                                   0xffffffff, 0, out) == 0;
 }
 
 static unsigned hash_dev(void *key)
index f7784fb795e4794ca43fe3e950552bcd3f7acfe8..384d7280380fe2d40bba59bfe9021a07a4a5c4f6 100644 (file)
@@ -583,7 +583,7 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
     return 0;
 }
 
-static void radeon_read_registers(struct radeon_winsys *rws,
+static bool radeon_read_registers(struct radeon_winsys *rws,
                                   unsigned reg_offset,
                                   unsigned num_registers, uint32_t *out)
 {
@@ -593,9 +593,11 @@ static void radeon_read_registers(struct radeon_winsys *rws,
     for (i = 0; i < num_registers; i++) {
         uint32_t reg = reg_offset + i*4;
 
-        radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, "read-reg", &reg);
+        if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
+            return false;
         out[i] = reg;
     }
+    return true;
 }
 
 static unsigned hash_fd(void *key)