uint64_t (*query_value)(struct radeon_winsys *ws,
enum radeon_value_id value);
- void (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
+ bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
unsigned num_registers, uint32_t *out);
};
struct radeon_winsys *ws = sctx->b.ws;
uint32_t value;
- ws->read_registers(ws, offset, 1, &value);
- si_dump_reg(f, offset, value, ~0);
+ if (ws->read_registers(ws, offset, 1, &value))
+ si_dump_reg(f, offset, value, ~0);
}
static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
return 0;
}
-static void amdgpu_read_registers(struct radeon_winsys *rws,
+static bool amdgpu_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
- amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
- 0xffffffff, 0, out);
+ return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
+ 0xffffffff, 0, out) == 0;
}
static unsigned hash_dev(void *key)
return 0;
}
-static void radeon_read_registers(struct radeon_winsys *rws,
+static bool radeon_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
for (i = 0; i < num_registers; i++) {
uint32_t reg = reg_offset + i*4;
- radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, "read-reg", ®);
+ if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, ®))
+ return false;
out[i] = reg;
}
+ return true;
}
static unsigned hash_fd(void *key)