[sim] fixed fcvt rounding bugs

diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
index bd460d57c0725c71e6391792841cbe9f825045bb..206ba4fc4c4eebf75a67f8677531c76322cba1c6 100644 (file)
--- a/riscv/insns/fcvt_l_d.h
+++ b/riscv/insns/fcvt_l_d.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_i64_r_minMag(FRS1,true);
+RD = f64_to_i64(FRS1, RM, true);
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
index 1ed4594c045e033d43b424bbf3f298e2d384b8f2..e05f4761c5e81573ea39ab332ac8ffacdae57fa0 100644 (file)
--- a/riscv/insns/fcvt_l_s.h
+++ b/riscv/insns/fcvt_l_s.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_i64_r_minMag(FRS1,true);
+RD = f32_to_i64(FRS1, RM, true);
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index bd460d57c0725c71e6391792841cbe9f825045bb..44c3dd6ba426c12cefa03728d0c0f77d6329b0e2 100644 (file)
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_i64_r_minMag(FRS1,true);
+RD = f64_to_ui64(FRS1, RM, true);
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
index 1ed4594c045e033d43b424bbf3f298e2d384b8f2..13de43689ebbef7178e00249659507fada835046 100644 (file)
--- a/riscv/insns/fcvt_lu_s.h
+++ b/riscv/insns/fcvt_lu_s.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_i64_r_minMag(FRS1,true);
+RD = f32_to_ui64(FRS1, RM, true);
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
index e92446782e1b3fb803cb6c2969f0e7365d250672..88dc3d33c53253ff9e00bc836efe2a73ea3e7407 100644 (file)
--- a/riscv/insns/fcvt_w_d.h
+++ b/riscv/insns/fcvt_w_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_i32_r_minMag(FRS1,true);
+RD = sext32(f64_to_i32(FRS1, RM, true));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
index 809797f8dc87d06237763c6c2770dcb5b6025ea2..f14cc19a37798d4e2032cf69bc2b233b02c50c8c 100644 (file)
--- a/riscv/insns/fcvt_w_s.h
+++ b/riscv/insns/fcvt_w_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_i32_r_minMag(FRS1,true);
+RD = sext32(f32_to_i32(FRS1, RM, true));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
index 93860e876b2d56e851a58406176da1efc6d9fd3c..43ad6f63d30c497d5154b70af4c0f4c2a8717356 100644 (file)
--- a/riscv/insns/fcvt_wu_d.h
+++ b/riscv/insns/fcvt_wu_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_ui32_r_minMag(FRS1,true);
+RD = sext32(f64_to_ui32(FRS1, RM, true));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
index 04b8fb2764cb932d77bb797afa990dff00447fc8..ff7a11cf73062f48969529d581b8c42048b80039 100644 (file)
--- a/riscv/insns/fcvt_wu_s.h
+++ b/riscv/insns/fcvt_wu_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_ui32_r_minMag(FRS1,true);
+RD = sext32(f32_to_ui32(FRS1, RM, true));
 set_fp_exceptions;