whoops on an OR rather than an AND

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index f1aadd73a10e1cc60dad35c771c4a715f6b2e7a5..7ac8c4b48c0c34cea8727c36a3ebed8b87e297f4 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -980,7 +980,7 @@ class PowerDecodeSubset(Elaboratable):
             comb += self.do_copy("fn_unit", Function.TRAP)
             comb += self.do_copy("insn_type", internal_op)
         # SPR pipe must *not* receive MMU or TRAP SPRs
-        with m.Elif(is_spr_mv & ((fn == Function.MMU) & ~is_mmu_spr) |
+        with m.Elif(is_spr_mv & ((fn == Function.MMU) & ~is_mmu_spr) &
                                 ((fn == Function.TRAP) & ~is_trap_spr)):
             comb += self.do_copy("fn_unit", Function.NONE)
             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)