ir3/instr-a3xx.h \
ir3/ir3.c \
ir3/ir3_compiler_nir.c \
+ ir3/ir3_compiler.c \
ir3/ir3_compiler.h \
ir3/ir3_cp.c \
ir3/ir3_depth.c \
#include "fd3_screen.h"
#include "fd3_context.h"
#include "fd3_format.h"
+#include "ir3_compiler.h"
static boolean
fd3_screen_is_format_supported(struct pipe_screen *pscreen,
void
fd3_screen_init(struct pipe_screen *pscreen)
{
- fd_screen(pscreen)->max_rts = 4;
+ struct fd_screen *screen = fd_screen(pscreen);
+ screen->max_rts = 4;
+ screen->compiler = ir3_compiler_create(screen->gpu_id);
pscreen->context_create = fd3_context_create;
pscreen->is_format_supported = fd3_screen_is_format_supported;
}
#include "fd4_screen.h"
#include "fd4_context.h"
#include "fd4_format.h"
+#include "ir3_compiler.h"
static boolean
fd4_screen_is_format_supported(struct pipe_screen *pscreen,
void
fd4_screen_init(struct pipe_screen *pscreen)
{
- fd_screen(pscreen)->max_rts = 1;
+ struct fd_screen *screen = fd_screen(pscreen);
+ screen->max_rts = 1;
+ screen->compiler = ir3_compiler_create(screen->gpu_id);
pscreen->context_create = fd4_context_create;
pscreen->is_format_supported = fd4_screen_is_format_supported;
}
uint32_t device_id;
uint32_t gpu_id; /* 220, 305, etc */
uint32_t chip_id; /* coreid:8 majorrev:8 minorrev:8 patch:8 */
- uint32_t max_rts;
+ uint32_t max_rts; /* max # of render targets */
+
+ void *compiler; /* currently unused for a2xx */
struct fd_device *dev;
struct fd_pipe *pipe;
return ptr;
}
-struct ir3 * ir3_create(void)
+struct ir3 * ir3_create(struct ir3_compiler *compiler)
{
struct ir3 *shader =
calloc(1, sizeof(struct ir3));
grow_heap(shader);
+ shader->compiler = compiler;
return shader;
}
/* low level intermediate representation of an adreno shader program */
+struct ir3_compiler;
struct ir3;
struct ir3_instruction;
struct ir3_block;
struct ir3_heap_chunk;
struct ir3 {
+ struct ir3_compiler *compiler;
/* Track bary.f (and ldlv) instructions.. this is needed in
* scheduling to ensure that all varying fetches happen before
struct list_head instr_list;
};
-struct ir3 * ir3_create(void);
+struct ir3 * ir3_create(struct ir3_compiler *compiler);
void ir3_destroy(struct ir3 *shader);
void * ir3_assemble(struct ir3 *shader,
struct ir3_info *info, uint32_t gpu_id);
const char *filename;
struct tgsi_token toks[65536];
struct tgsi_parse_context parse;
+ struct ir3_compiler *compiler;
struct ir3_shader_variant v;
struct ir3_shader_key key = {};
const char *info;
break;
}
+ /* TODO cmdline option to target different gpus: */
+ compiler = ir3_compiler_create(320);
+
info = "NIR compiler";
- ret = ir3_compile_shader_nir(&v, toks, key);
+ ret = ir3_compile_shader_nir(compiler, &v, toks, key);
if (ret) {
fprintf(stderr, "compiler failed!\n");
return ret;
--- /dev/null
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+
+/*
+ * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Rob Clark <robclark@freedesktop.org>
+ */
+
+#include "util/ralloc.h"
+
+#include "ir3_compiler.h"
+
+struct ir3_compiler * ir3_compiler_create(uint32_t gpu_id)
+{
+ struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
+ compiler->gpu_id = gpu_id;
+ return compiler;
+}
+
+void ir3_compiler_destroy(struct ir3_compiler *compiler)
+{
+ ralloc_free(compiler);
+}
#include "ir3_shader.h"
-int ir3_compile_shader_nir(struct ir3_shader_variant *so,
- const struct tgsi_token *tokens, struct ir3_shader_key key);
+struct ir3_compiler {
+ uint32_t gpu_id;
+};
+
+struct ir3_compiler * ir3_compiler_create(uint32_t gpu_id);
+void ir3_compiler_destroy(struct ir3_compiler *compiler);
+
+int ir3_compile_shader_nir(struct ir3_compiler *compiler,
+ struct ir3_shader_variant *so,
+ const struct tgsi_token *tokens,
+ struct ir3_shader_key key);
#endif /* IR3_COMPILER_H_ */
break;
}
- if (!so->shader) {
- /* hack for standalone compiler which does not have
- * screen/context:
- */
- } else if (ir3_shader_gpuid(so->shader) >= 400) {
+ if (so->ir->compiler->gpu_id >= 400) {
/* a4xx seems to have *no* sam.p */
lconfig.lower_TXP = ~0; /* lower all txp */
} else {
struct ir3_compile *ctx = rzalloc(NULL, struct ir3_compile);
const struct tgsi_token *lowered_tokens;
- if (!so->shader) {
- /* hack for standalone compiler which does not have
- * screen/context:
- */
- } else if (ir3_shader_gpuid(so->shader) >= 400) {
+ if (so->ir->compiler->gpu_id >= 400) {
/* need special handling for "flat" */
ctx->flat_bypass = true;
ctx->levels_add_one = false;
}
int
-ir3_compile_shader_nir(struct ir3_shader_variant *so,
- const struct tgsi_token *tokens, struct ir3_shader_key key)
+ir3_compile_shader_nir(struct ir3_compiler *compiler,
+ struct ir3_shader_variant *so,
+ const struct tgsi_token *tokens,
+ struct ir3_shader_key key)
{
struct ir3_compile *ctx;
struct ir3_block *block;
assert(!so->ir);
- so->ir = ir3_create();
+ so->ir = ir3_create(compiler);
assert(so->ir);
assemble_variant(struct ir3_shader_variant *v)
{
struct fd_context *ctx = fd_context(v->shader->pctx);
- uint32_t gpu_id = ir3_shader_gpuid(v->shader);
+ uint32_t gpu_id = v->shader->compiler->gpu_id;
uint32_t sz, *bin;
bin = ir3_shader_assemble(v, gpu_id);
tgsi_dump(tokens, 0);
}
- ret = ir3_compile_shader_nir(v, tokens, key);
+ ret = ir3_compile_shader_nir(shader->compiler, v, tokens, key);
if (ret) {
debug_error("compile failed!");
goto fail;
return NULL;
}
-uint32_t
-ir3_shader_gpuid(struct ir3_shader *shader)
-{
- struct fd_context *ctx = fd_context(shader->pctx);
- return ctx->screen->gpu_id;
-}
-
struct ir3_shader_variant *
ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
{
enum shader_t type)
{
struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
+ shader->compiler = fd_context(pctx)->screen->compiler;
shader->pctx = pctx;
shader->type = type;
shader->tokens = tgsi_dup_tokens(tokens);
struct ir3_shader {
enum shader_t type;
+ struct ir3_compiler *compiler;
+
struct pipe_context *pctx;
const struct tgsi_token *tokens;
struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
const struct tgsi_token *tokens, enum shader_t type);
void ir3_shader_destroy(struct ir3_shader *shader);
-uint32_t ir3_shader_gpuid(struct ir3_shader *shader);
struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
struct ir3_shader_key key);
* Helper/util:
*/
+#include "pipe/p_shader_tokens.h"
+
static inline int
ir3_find_output(const struct ir3_shader_variant *so, ir3_semantic semantic)
{
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