(no commit message)

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index f6c2265b15e80bc4ae0b6f3c553374cf6f77d581..2948c2adbc8f63dc0972422033a213e627d32261 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -514,6 +514,10 @@ uint64_t gorc64(uint64_t RA, uint64_t RB)
 
 see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
 
+
+https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf
+
+
 ## SPRs to set modulo and degree
 
 to save registers and make operations orthogonal with standard