Updated FastCPU model with all the recent changes.

arch/alpha/ev5.cc:
    Updated to support new forms of setIntReg and setFloatRegDouble.  Will need to be cleaned up in the future.
arch/isa_parser.py:
    Added in FastCPU model.

--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index e88f6d0a3a3dca0fe5f61af836e11160f52a1b85..ecf66f4f51ef890be76dd7280cb97c0ff93e0165 100644 (file)
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -153,8 +153,10 @@ void
 AlphaISA::zeroRegisters(XC *xc)
 {
     // Insure ISA semantics
-    xc->setIntReg(ZeroReg, 0);
-    xc->setFloatRegDouble(ZeroReg, 0.0);
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    xc->xc->setIntReg(ZeroReg, 0);
+    xc->xc->setFloatRegDouble(ZeroReg, 0.0);
 }
 
 void

diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 7f77241beda974f4515fa52c479516f993ddc634..c808c256547902ef564f7700582a81bd2be75d4b 100755 (executable)
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -630,6 +630,9 @@ class CpuModel:
 CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
          '#include "cpu/simple_cpu/simple_cpu.hh"',
          { 'CPU_exec_context': 'SimpleCPU' })
+CpuModel('FastCPU', 'fast_cpu_exec.cc',
+         '#include "cpu/fast_cpu/fast_cpu.hh"',
+         { 'CPU_exec_context': 'FastCPU' })
 CpuModel('FullCPU', 'full_cpu_exec.cc',
          '#include "cpu/full_cpu/dyn_inst.hh"',
          { 'CPU_exec_context': 'DynInst' })