CR0 (if Rc=1)
-# Generalized Bit-Reverse
-
-X-Form
-
-* grev RT,RA,RB (Rc=0)
-* grev. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- result <- [0] * XLEN
- b <- EXTZ64(RB)
- do i = 0 to XLEN - 1
- idx <- b[64-log2(XLEN):63] ^ i
- result[i] <- (RA)[idx]
- RT <- result
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Generalized Bit-Reverse Immediate
-
-XB-Form
-
-* grevi RT,RA,XBI (Rc=0)
-* grevi. RT,RA,XBI (Rc=1)
-
-Pseudo-code:
-
- result <- [0] * XLEN
- do i = 0 to XLEN - 1
- idx <- XBI[6-log2(XLEN):5] ^ i
- result[i] <- (RA)[idx]
- RT <- result
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Generalized Bit-Reverse Word
-
-X-Form
-
-* grevw RT,RA,RB (Rc=0)
-* grevw. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- result <- [0] * (XLEN / 2)
- a <- (RA)[XLEN/2:XLEN-1]
- b <- EXTZ64(RB)
- do i = 0 to XLEN / 2 - 1
- idx <- b[64-log2(XLEN/2):63] ^ i
- result[i] <- a[idx]
- RT <- ([0] * (XLEN / 2)) || result
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Generalized Bit-Reverse Word Immediate
-
-X-Form
-
-* grevwi RT,RA,SH (Rc=0)
-* grevwi. RT,RA,SH (Rc=1)
-
-Pseudo-code:
-
- result <- [0] * (XLEN / 2)
- a <- (RA)[XLEN/2:XLEN-1]
- do i = 0 to XLEN / 2 - 1
- idx <- SH[5-log2(XLEN/2):4] ^ i
- result[i] <- a[idx]
- RT <- ([0] * (XLEN / 2)) || result
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
# Add With Shift By Immediate
Z23-Form
divwuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
divdo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
divwo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-grev,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-grevw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
fdivs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
fsubs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
fadds,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
sradi,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
extswsli,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
extswsli,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-grevi,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-grevwi,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
|0 |6 |11 |16 |21 |30|31 |
| PO | RS | RA | sh | XO |sh|Rc |
-# 1.6.15 XB-FORM
- |0 |6 |11 |16 |22 |31 |
- | PO | RT | RA | XBI | XO |Rc |
-
# 1.6.16 XO-FORM
|0 |6 |11 |13 |16 |21 |22 |31 |
| PO | RT | RA | RB | OE | XO | Rc |
RA (11:15)
Field used to specify a GPR to be used as a
source or as a target.
- Formats: A, BM2, D, DQ, DQE, DS, M, MD, MDS, MM, TX, VA, VA2, VX, X, XO, XS, SVL, XB, TLI, Z23
+ Formats: A, BM2, D, DQ, DQE, DS, M, MD, MDS, MM, TX, VA, VA2, VX, X, XO, XS, SVL, TLI, Z23
RB (16:20)
Field used to specify a GPR to be used as a
source.
1 Set Condition Register Field 0 or Field 1 as
described in Section 2.3.1, 'Condition Regis-
ter' on page 30.
- Formats: A, M, MD, MDS, MM, VA2, X, XFL, XO, XS, Z22, Z23, SVL, XB, TLI, DCT
+ Formats: A, M, MD, MDS, MM, VA2, X, XFL, XO, XS, Z22, Z23, SVL, TLI, DCT
RIC (12:13)
Field used to specify what types of entries to inval-
idate for tlbie[l].
Formats: DS, X
RT (6:10)
Field used to specify a GPR to be used as a target.
- Formats: A, BM2, D, DQE, DS, DX, MM, VA, VA2, VX, X, XFX, XO, XX2, SVL, XB, TLI, Z23
+ Formats: A, BM2, D, DQE, DS, DX, MM, VA, VA2, VX, X, XFX, XO, XX2, SVL, TLI, Z23
RTp (6:10)
Field used to specify an even/odd pair of GPRs to
be concatenated and used as a target.
XBI (21:24)
Field used to specify a bit in the XER.
Formats: MDS, MDS, TX
- XBI (16:21)
- Field used to specify a 6-bit unsigned immediate for bit manipulation
- instructions, such as grevi.
- Formats: XB
XO (21:23,26:31)
Extended opcode field.
Formats: SVM2
Formats: VX
XO (22:30)
Extended opcode field.
- Formats: XO, XX3, Z22, XB
+ Formats: XO, XX3, Z22
XO (22:31)
Extended opcode field.
Formats: VC
opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
--------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0010010110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,grev,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
--011010110-,SHIFT_ROT,OP_GREV,RA,CONST_XBI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,grevi,XB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0010110110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,grevw,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0011110110-,SHIFT_ROT,OP_GREV,RA,CONST_SH32,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,grevwi,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
comb += Assert(pdecode2.e.imm_data.data == dec.sh)
with m.Case(In2Sel.CONST_SH32):
comb += Assert(pdecode2.e.imm_data.data == dec.SH32)
- with m.Case(In2Sel.CONST_XBI):
- comb += Assert(pdecode2.e.imm_data.data == dec.FormXB.XBI)
with m.Default():
comb += Assert(0)
"brh", "brw", "brd",
'setvl', 'svindex', 'svremap', 'svstep',
'svshape', 'svshape2',
- 'grev', 'ternlogi', 'bmask', 'cprop',
+ 'ternlogi', 'bmask', 'cprop',
'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
"dsld", "dsrd", "maddedus",
with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
comb += self.imm_out.data.eq(self.dec.SH32)
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_XBI): # unsigned - for grevi
- comb += self.imm_out.data.eq(self.dec.FormXB.XBI)
- comb += self.imm_out.ok.eq(1)
return m
SVM2 = 33 # Simple-V SHAPE2 mode - fits into SVM
SVRM = 34 # Simple-V REMAP mode
TLI = 35 # ternlogi
- XB = 36
+ # 36 available
BM2 = 37 # bmask
SVI = 38 # Simple-V Index Mode
VA2 = 39
"mffpr", "mffprs",
"ctfpr", "ctfprs",
"mtfpr", "mtfprs",
- 'grev', 'grev.', 'grevi', 'grevi.',
- 'grevw', 'grevw.', 'grevwi', 'grevwi.',
"hrfid", "icbi", "icbt", "isel", "isync",
"lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte
"ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
OP_CBCDTD = 85
OP_TERNLOG = 86
OP_FETCH_FAILED = 87
- OP_GREV = 88
+ # 88 available
OP_MINMAX = 89
OP_AVGADD = 90
OP_ABSDIFF = 91
FRBp = FRB
CONST_SVD = 15 # for SVD-Form
CONST_SVDS = 16 # for SVDS-Form
- CONST_XBI = 17
+ # 17 available
CONST_DXHI4 = 18 # for addpcis
CONST_DQ = 19 # for ld/st-quad
rb = hash_256(f"ternlogi rb {i}") % 2 ** 64
self.do_case_ternlogi(rc, rt, ra, rb, imm)
- @skip_case("invalid, replaced by grevlut")
+ @skip_case("grev removed -- leaving code for later use in grevlut")
def case_grev_random(self):
for i in range(100):
w = hash_256(f"grev w {i}") & 1
rb = hash_256(f"grev rb {i}") % 2 ** 64
self.do_case_grev(w, is_imm, ra, rb)
- @skip_case("invalid, replaced by grevlut")
+ @skip_case("grev removed -- leaving code for later use in grevlut")
def case_grevi_1(self):
self.do_case_grev(False, True, 14361919363078703450,
8396479064514513069)
- @skip_case("invalid, replaced by grevlut")
+ @skip_case("grev removed -- leaving code for later use in grevlut")
def case_grevi_2(self):
self.do_case_grev(True, True, 397097147229333315, 8326716970539357702)
- @skip_case("invalid, replaced by grevlut")
+ @skip_case("grev removed -- leaving code for later use in grevlut")
def case_grevi_3(self):
self.do_case_grev(True, True, 0xFFFF_FFFF_0000_0000, 6)
projects / openpower-isa.git / commitdiff