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intel/genxml: turn SLM Enable bit into boolean
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Fri, 7 Sep 2018 10:55:45 +0000 (11:55 +0100)
committerLionel Landwerlin <lionel.g.landwerlin@intel.com>
Fri, 7 Sep 2018 13:46:20 +0000 (14:46 +0100)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
src/intel/genxml/gen10.xml patch | blob | history
src/intel/genxml/gen8.xml patch | blob | history
src/intel/genxml/gen9.xml patch | blob | history

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 541e4405716268005fbd43cdb624ca75fcc12e65..abd5da297d66c29aa07b287fc2da6d947583c7cf 100644 (file)
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3546,7 +3546,7 @@
   </register>
 
   <register name="L3CNTLREG" length="1" num="0x7034">
-    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="SLM Enable" start="0" end="0" type="bool"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
     <field name="RO Allocation" start="11" end="17" type="uint"/>
     <field name="DC Allocation" start="18" end="24" type="uint"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 330366b7ed083ac18f5fb316d387f31707877fdf..d42c63aabd83451644836b0d2a66e56aae27cb7a 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3199,7 +3199,7 @@
   </register>
 
   <register name="L3CNTLREG" length="1" num="0x7034">
-    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="SLM Enable" start="0" end="0" type="bool"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
     <field name="RO Allocation" start="11" end="17" type="uint"/>
     <field name="DC Allocation" start="18" end="24" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 318ae89d5e70e59adb9450c5e17e77fe5c6840bb..ca268254503683649fb743853e29dad25a4cdf1a 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3484,7 +3484,7 @@
   </register>
 
   <register name="L3CNTLREG" length="1" num="0x7034">
-    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="SLM Enable" start="0" end="0" type="bool"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
     <field name="RO Allocation" start="11" end="17" type="uint"/>
     <field name="DC Allocation" start="18" end="24" type="uint"/>