(no commit message)

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 0469b3f072b088c03e8a0cf164f40d4d7734d4d0..b260c5909dfe2a66c084e0f1f852685b79b8ed3b 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -485,10 +485,10 @@ destination, *all* the sequential ordered standard patterns of Vector
 ISAs are provided: VSPLAT, VSELECT, VINSERT, VCOMPRESS, VEXPAND.
 
 The only one missing from the list here, because it is non-sequential,
-is VGATHER: moving registers by specifying a vector of register indices
+is VGATHER (and VSCATTER): moving registers by specifying a vector of register indices
 (`regs[rd] = regs[regs[rs]]` in a loop).  This one is tricky because it
 typically does not exist in standard scalar ISAs.  If it did it would
-be called [[sv/mv.x]]. Once Vectorised, it's a VGATHER.
+be called [[sv/mv.x]]. Once Vectorised, it's a VGATHER/VSCATTER.
 
 # CR predicate result analysis