SigBit y_port;
pool<Cell*> reduce_or;
for (auto cell : module->cells()) {
- if (cell->type == "$eq") {
- nonconst_sig = sigmap(cell->getPort("\\A"));
- const_sig = sigmap(cell->getPort("\\B"));
+ if (cell->type == ID($eq)) {
+ nonconst_sig = sigmap(cell->getPort(ID(A)));
+ const_sig = sigmap(cell->getPort(ID(B)));
if (!const_sig.is_fully_const()) {
if (!nonconst_sig.is_fully_const())
continue;
std::swap(nonconst_sig, const_sig);
}
- y_port = sigmap(cell->getPort("\\Y"));
+ y_port = sigmap(cell->getPort(ID(Y)));
}
- else if (cell->type == "$logic_not") {
- nonconst_sig = sigmap(cell->getPort("\\A"));
+ else if (cell->type == ID($logic_not)) {
+ nonconst_sig = sigmap(cell->getPort(ID(A)));
const_sig = Const(State::S0, GetSize(nonconst_sig));
- y_port = sigmap(cell->getPort("\\Y"));
+ y_port = sigmap(cell->getPort(ID(Y)));
}
- else if (cell->type == "$reduce_or") {
+ else if (cell->type == ID($reduce_or)) {
reduce_or.insert(cell);
continue;
}
for (auto cell : reduce_or) {
nonconst_sig = SigSpec();
std::vector<Const> values;
- SigSpec a_port = sigmap(cell->getPort("\\A"));
+ SigSpec a_port = sigmap(cell->getPort(ID(A)));
for (auto bit : a_port) {
auto it = sig_cmp_prev.find(bit);
if (it == sig_cmp_prev.end()) {
}
if (nonconst_sig.empty())
continue;
- y_port = sigmap(cell->getPort("\\Y"));
+ y_port = sigmap(cell->getPort(ID(Y)));
sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::move(values));
}
}
{
for (auto wire : module->wires())
{
- if (wire->port_output || wire->get_bool_attribute("\\keep")) {
+ if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
for (auto bit : sigmap(wire))
sigbit_with_non_chain_users.insert(bit);
}
for (auto cell : module->cells())
{
- if (cell->type.in("$mux", "$pmux") && !cell->get_bool_attribute("\\keep"))
+ if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID(keep)))
{
- SigSpec a_sig = sigmap(cell->getPort("\\A"));
+ SigSpec a_sig = sigmap(cell->getPort(ID(A)));
SigSpec b_sig;
- if (cell->type == "$mux")
- b_sig = sigmap(cell->getPort("\\B"));
- SigSpec y_sig = sigmap(cell->getPort("\\Y"));
+ if (cell->type == ID($mux))
+ b_sig = sigmap(cell->getPort(ID(B)));
+ SigSpec y_sig = sigmap(cell->getPort(ID(Y)));
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig.bits())
{
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
- SigSpec a_sig = sigmap(cell->getPort("\\A"));
- if (cell->type == "$mux") {
- SigSpec b_sig = sigmap(cell->getPort("\\B"));
+ SigSpec a_sig = sigmap(cell->getPort(ID(A)));
+ if (cell->type == ID($mux)) {
+ SigSpec b_sig = sigmap(cell->getPort(ID(B)));
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
goto start_cell;
if (!sig_chain_prev.count(a_sig))
a_sig = b_sig;
}
- else if (cell->type == "$pmux") {
+ else if (cell->type == ID($pmux)) {
if (!sig_chain_prev.count(a_sig))
goto start_cell;
}
{
Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell);
- SigSpec s_sig = sigmap(cell->getPort("\\S"));
- s_sig.append(sigmap(prev_cell->getPort("\\S")));
+ SigSpec s_sig = sigmap(cell->getPort(ID(S)));
+ s_sig.append(sigmap(prev_cell->getPort(ID(S))));
if (!excl_db.query(s_sig))
goto start_cell;
}
{
chain.push_back(c);
- SigSpec y_sig = sigmap(c->getPort("\\Y"));
+ SigSpec y_sig = sigmap(c->getPort(ID(Y)));
if (sig_chain_next.count(y_sig) == 0)
break;
mux_count += cases;
pmux_count += 1;
- first_cell->type = "$pmux";
- SigSpec b_sig = first_cell->getPort("\\B");
- SigSpec s_sig = first_cell->getPort("\\S");
+ first_cell->type = ID($pmux);
+ SigSpec b_sig = first_cell->getPort(ID(B));
+ SigSpec s_sig = first_cell->getPort(ID(S));
for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i];
- if (sigmap(prev_cell->getPort("\\Y")) == sigmap(cursor_cell->getPort("\\A"))) {
- b_sig.append(cursor_cell->getPort("\\B"));
- s_sig.append(cursor_cell->getPort("\\S"));
+ if (sigmap(prev_cell->getPort(ID(Y))) == sigmap(cursor_cell->getPort(ID(A)))) {
+ b_sig.append(cursor_cell->getPort(ID(B)));
+ s_sig.append(cursor_cell->getPort(ID(S)));
}
else {
- log_assert(cursor_cell->type == "$mux");
- b_sig.append(cursor_cell->getPort("\\A"));
- s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort("\\S")));
+ log_assert(cursor_cell->type == ID($mux));
+ b_sig.append(cursor_cell->getPort(ID(A)));
+ s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID(S))));
}
remove_cells.insert(cursor_cell);
}
- first_cell->setPort("\\B", b_sig);
- first_cell->setPort("\\S", s_sig);
- first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
- first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
+ first_cell->setPort(ID(B), b_sig);
+ first_cell->setPort(ID(S), s_sig);
+ first_cell->setParam(ID(S_WIDTH), GetSize(s_sig));
+ first_cell->setPort(ID(Y), last_cell->getPort(ID(Y)));
cursor += cases;
}
return cache.at(module);
cache[module] = true;
- if (!module->get_bool_attribute("\\keep")) {
+ if (!module->get_bool_attribute(ID(keep))) {
bool found_keep = false;
for (auto cell : module->cells())
if (query(cell)) found_keep = true;
bool query(Cell *cell)
{
- if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover", "$specify2", "$specify3", "$specrule"))
+ if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($specify2), ID($specify3), ID($specrule)))
return true;
if (cell->has_keep_attr())
for (auto &it : module->wires_) {
Wire *wire = it.second;
- if (wire->port_output || wire->get_bool_attribute("\\keep")) {
+ if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
for (auto bit : sigmap(wire))
for (auto c : wire2driver[bit])
queue.insert(c), unused.erase(c);
int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
- count -= w->attributes.count("\\src");
- count -= w->attributes.count("\\unused_bits");
+ count -= w->attributes.count(ID(src));
+ count -= w->attributes.count(ID(unused_bits));
return count;
}
if (!wire->port_input)
used_signals_nodrivers.add(sig);
}
- if (wire->get_bool_attribute("\\keep")) {
+ if (wire->get_bool_attribute(ID(keep))) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
assign_map.apply(sig);
used_signals.add(sig);
log_assert(GetSize(s1) == GetSize(s2));
Const initval;
- if (wire->attributes.count("\\init"))
- initval = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID(init)))
+ initval = wire->attributes.at(ID(init));
if (GetSize(initval) != GetSize(wire))
initval.bits.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID(init));
if (GetSize(wire) == 0) {
// delete zero-width wires, unless they are module ports
if (wire->port_id == 0)
goto delete_this_wire;
} else
- if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
+ if (wire->port_id != 0 || wire->get_bool_attribute(ID(keep)) || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires
} else
if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) {
}
if (new_conn.first.size() > 0) {
if (initval.is_fully_undef())
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID(init));
else
- wire->attributes.at("\\init") = initval;
+ wire->attributes.at(ID(init)) = initval;
used_signals.add(new_conn.first);
used_signals.add(new_conn.second);
module->connect(new_conn);
}
}
if (unused_bits.empty() || wire->port_id != 0)
- wire->attributes.erase("\\unused_bits");
+ wire->attributes.erase(ID(unused_bits));
else
- wire->attributes["\\unused_bits"] = RTLIL::Const(unused_bits);
+ wire->attributes[ID(unused_bits)] = RTLIL::Const(unused_bits);
} else {
- wire->attributes.erase("\\unused_bits");
+ wire->attributes.erase(ID(unused_bits));
}
}
}
dict<SigBit, State> qbits;
for (auto cell : module->cells())
- if (fftypes.cell_known(cell->type) && cell->hasPort("\\Q"))
+ if (fftypes.cell_known(cell->type) && cell->hasPort(ID(Q)))
{
- SigSpec sig = cell->getPort("\\Q");
+ SigSpec sig = cell->getPort(ID(Q));
for (int i = 0; i < GetSize(sig); i++)
{
SigBit bit = sig[i];
- if (bit.wire == nullptr || bit.wire->attributes.count("\\init") == 0)
+ if (bit.wire == nullptr || bit.wire->attributes.count(ID(init)) == 0)
continue;
- Const init = bit.wire->attributes.at("\\init");
+ Const init = bit.wire->attributes.at(ID(init));
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
continue;
if (!purge_mode && wire->name[0] == '\\')
continue;
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID(init)) == 0)
continue;
- Const init = wire->attributes.at("\\init");
+ Const init = wire->attributes.at(ID(init));
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
{
if (verbose)
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID(init));
did_something = true;
next_wire:;
}
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())
- if (cell->type.in("$pos", "$_BUF_") && !cell->has_keep_attr()) {
- bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool();
- RTLIL::SigSpec a = cell->getPort("\\A");
- RTLIL::SigSpec y = cell->getPort("\\Y");
+ if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
+ bool is_signed = cell->type == ID($pos) && cell->getParam(ID(A_SIGNED)).as_bool();
+ RTLIL::SigSpec a = cell->getPort(ID(A));
+ RTLIL::SigSpec y = cell->getPort(ID(Y));
a.extend_u0(GetSize(y), is_signed);
module->connect(y, a);
delcells.push_back(cell);
for (auto cell : delcells) {
if (verbose)
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(),
- log_signal(cell->getPort("\\Y")), log_signal(cell->getPort("\\A")));
+ log_signal(cell->getPort(ID(Y))), log_signal(cell->getPort(ID(A))));
module->remove(cell);
}
if (!delcells.empty())
//TODO: Add support for reduce_xor
//DeMorgan of XOR is either XOR (if even number of inputs) or XNOR (if odd number)
- if( (cell->type != "$reduce_and") && (cell->type != "$reduce_or") )
+ if( (cell->type != ID($reduce_and)) && (cell->type != ID($reduce_or)) )
return;
- auto insig = sigmap(cell->getPort("\\A"));
+ auto insig = sigmap(cell->getPort(ID(A)));
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)
bool inverted = false;
for(auto x : ports)
{
- if(x.port == "\\Y" && x.cell->type == "$_NOT_")
+ if(x.port == ID(Y) && x.cell->type == ID($_NOT_))
{
inverted = true;
break;
RTLIL::Cell* srcinv = NULL;
for(auto x : ports)
{
- if(x.port == "\\Y" && x.cell->type == "$_NOT_")
+ if(x.port == ID(Y) && x.cell->type == ID($_NOT_))
{
srcinv = x.cell;
break;
//We ARE inverted - bypass it
//Don't automatically delete the inverter since other stuff might still use it
else
- insig[i] = srcinv->getPort("\\A");
+ insig[i] = srcinv->getPort(ID(A));
}
//Cosmetic fixup: If our input is just a scrambled version of one bus, rearrange it
}
//Push the new input signal back to the reduction (after bypassing/adding inverters)
- cell->setPort("\\A", insig);
+ cell->setPort(ID(A), insig);
//Change the cell type
- if(cell->type == "$reduce_and")
- cell->type = "$reduce_or";
- else if(cell->type == "$reduce_or")
- cell->type = "$reduce_and";
+ if(cell->type == ID($reduce_and))
+ cell->type = ID($reduce_or);
+ else if(cell->type == ID($reduce_or))
+ cell->type = ID($reduce_and);
//don't change XOR
//Add an inverter to the output
- auto inverted_output = cell->getPort("\\Y");
+ auto inverted_output = cell->getPort(ID(Y));
auto uninverted_output = m->addWire(NEW_ID);
m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
- cell->setPort("\\Y", uninverted_output);
+ cell->setPort(ID(Y), uninverted_output);
}
struct OptDemorganPass : public Pass {
}
for (auto wire : module->wires()) {
- if (wire->attributes.count("\\init")) {
+ if (wire->attributes.count(ID(init))) {
SigSpec sig = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID(init));
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (initval[i] == State::S0 || initval[i] == State::S1)
initbits[sig[i]] = make_pair(wire, initval[i]);
}
if (wire->port_input)
driven_signals.add(sigmap(wire));
- if (wire->port_output || wire->get_bool_attribute("\\keep"))
+ if (wire->port_output || wire->get_bool_attribute(ID(keep)))
used_signals.add(sigmap(wire));
all_signals.add(sigmap(wire));
}
for (auto wire : revisit_initwires) {
SigSpec sig = sm2(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID(init));
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i])
initval[i] = State::Sx;
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID(init));
did_something = true;
- } else if (initval != wire->attributes.at("\\init")) {
+ } else if (initval != wire->attributes.at(ID(init))) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
- wire->attributes["\\init"] = initval;
+ wire->attributes[ID(init)] = initval;
did_something = true;
}
}
}
}
-void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
+void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, IdString out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->getPort(out_port);
out_val.extend_u0(Y.size(), false);
bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
{
- std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
+ IdString b_name = cell->hasPort(ID(B)) ? ID(B) : ID(A);
- bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
- bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
+ bool a_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
+ bool b_signed = cell->parameters.at(b_name.str() + "_SIGNED").as_bool();
- RTLIL::SigSpec sig_a = sigmap(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = sigmap(cell->getPort(ID(A)));
RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name));
- RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID(Y)));
sig_a.extend_u0(sig_y.size(), a_signed);
sig_b.extend_u0(sig_y.size(), b_signed);
int group_idx = GRP_DYN;
RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i];
- if (cell->type == "$or" && (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1))
+ if (cell->type == ID($or) && (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1))
bit_a = bit_b = RTLIL::State::S1;
- if (cell->type == "$and" && (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0))
+ if (cell->type == ID($and) && (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0))
bit_a = bit_b = RTLIL::State::S0;
if (bit_a.wire == NULL && bit_b.wire == NULL)
new_b.append_bit(it.first.second);
}
- if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
+ if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) {
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
module->connect(new_y, new_b);
module->connect(new_conn);
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
- c->setPort("\\A", new_a);
- c->parameters["\\A_WIDTH"] = new_a.size();
- c->parameters["\\A_SIGNED"] = false;
+ c->setPort(ID(A), new_a);
+ c->parameters[ID(A_WIDTH)] = new_a.size();
+ c->parameters[ID(A_SIGNED)] = false;
- if (b_name == "\\B") {
- c->setPort("\\B", new_b);
- c->parameters["\\B_WIDTH"] = new_b.size();
- c->parameters["\\B_SIGNED"] = false;
+ if (b_name == ID(B)) {
+ c->setPort(ID(B), new_b);
+ c->parameters[ID(B_WIDTH)] = new_b.size();
+ c->parameters[ID(B_SIGNED)] = false;
}
- c->setPort("\\Y", new_y);
- c->parameters["\\Y_WIDTH"] = new_y->width;
+ c->setPort(ID(Y), new_y);
+ c->parameters[ID(Y_WIDTH)] = new_y->width;
c->check();
module->connect(new_conn);
log_debug(" New cell `%s': A=%s", log_id(c), log_signal(new_a));
- if (b_name == "\\B")
+ if (b_name == ID(B))
log_debug(", B=%s", log_signal(new_b));
log_debug("\n");
}
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
- if (cell->type.in("$_NOT_", "$not", "$logic_not") &&
- cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1)
- invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A"));
- if (cell->type.in("$mux", "$_MUX_") &&
- cell->getPort("\\A") == SigSpec(State::S1) && cell->getPort("\\B") == SigSpec(State::S0))
- invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\S"));
+ if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
+ cell->getPort(ID(A)).size() == 1 && cell->getPort(ID(Y)).size() == 1)
+ invert_map[assign_map(cell->getPort(ID(Y)))] = assign_map(cell->getPort(ID(A)));
+ if (cell->type.in(ID($mux), ID($_MUX_)) &&
+ cell->getPort(ID(A)) == SigSpec(State::S1) && cell->getPort(ID(B)) == SigSpec(State::S0))
+ invert_map[assign_map(cell->getPort(ID(Y)))] = assign_map(cell->getPort(ID(S)));
if (ct_combinational.cell_known(cell->type))
for (auto &conn : cell->connections()) {
RTLIL::SigSpec sig = assign_map(conn.second);
for (auto cell : cells.sorted)
{
#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
-#define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_))
+#define ACTION_DO_Y(_v_) ACTION_DO(ID(Y), RTLIL::SigSpec(RTLIL::State::S ## _v_))
if (clkinv)
{
- if (cell->type.in("$dff", "$dffe", "$dffsr", "$adff", "$fsm", "$memrd", "$memwr"))
- handle_polarity_inv(cell, "\\CLK", "\\CLK_POLARITY", assign_map, invert_map);
+ if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
+ handle_polarity_inv(cell, ID(CLK), ID(CLK_POLARITY), assign_map, invert_map);
- if (cell->type.in("$sr", "$dffsr", "$dlatchsr")) {
- handle_polarity_inv(cell, "\\SET", "\\SET_POLARITY", assign_map, invert_map);
- handle_polarity_inv(cell, "\\CLR", "\\CLR_POLARITY", assign_map, invert_map);
+ if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
+ handle_polarity_inv(cell, ID(SET), ID(SET_POLARITY), assign_map, invert_map);
+ handle_polarity_inv(cell, ID(CLR), ID(CLR_POLARITY), assign_map, invert_map);
}
- if (cell->type.in("$dffe", "$dlatch", "$dlatchsr"))
- handle_polarity_inv(cell, "\\EN", "\\EN_POLARITY", assign_map, invert_map);
+ if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
+ handle_polarity_inv(cell, ID(EN), ID(EN_POLARITY), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", "\\S", assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", "\\R", assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID(S), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID(R), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", "\\C", assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID(C), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", "\\C", assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", "\\E", assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID(C), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID(E), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", "\\C", assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", "\\R", assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID(C), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID(R), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", "\\C", assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", "\\S", assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", "\\R", assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID(C), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID(S), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID(R), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", "\\E", assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID(E), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", "\\E", assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", "\\S", assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", "\\R", assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID(E), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID(S), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID(R), assign_map, invert_map);
}
bool detect_const_and = false;
bool detect_const_or = false;
- if (cell->type.in("$reduce_and", "$_AND_"))
+ if (cell->type.in(ID($reduce_and), ID($_AND_)))
detect_const_and = true;
- if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool())
+ if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID(A))) == 1 && GetSize(cell->getPort(ID(B))) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())
detect_const_and = true;
- if (cell->type.in("$reduce_or", "$reduce_bool", "$_OR_"))
+ if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_)))
detect_const_or = true;
- if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool())
+ if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID(A))) == 1 && GetSize(cell->getPort(ID(B))) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())
detect_const_or = true;
if (detect_const_and || detect_const_or)
{
- pool<SigBit> input_bits = assign_map(cell->getPort("\\A")).to_sigbit_pool();
+ pool<SigBit> input_bits = assign_map(cell->getPort(ID(A))).to_sigbit_pool();
bool found_zero = false, found_one = false, found_undef = false, found_inv = false, many_conconst = false;
SigBit non_const_input = State::Sm;
- if (cell->hasPort("\\B")) {
- vector<SigBit> more_bits = assign_map(cell->getPort("\\B")).to_sigbit_vector();
+ if (cell->hasPort(ID(B))) {
+ vector<SigBit> more_bits = assign_map(cell->getPort(ID(B))).to_sigbit_vector();
input_bits.insert(more_bits.begin(), more_bits.end());
}
}
}
- if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor", "$neg") &&
- GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\Y")) == 1)
+ if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&
+ GetSize(cell->getPort(ID(A))) == 1 && GetSize(cell->getPort(ID(Y))) == 1)
{
- if (cell->type == "$reduce_xnor") {
+ if (cell->type == ID($reduce_xnor)) {
cover("opt.opt_expr.reduce_xnor_not");
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
- cell->type = "$not";
+ cell->type = ID($not);
did_something = true;
} else {
cover("opt.opt_expr.unary_buffer");
if (do_fine)
{
- if (cell->type.in("$not", "$pos", "$and", "$or", "$xor", "$xnor"))
+ if (cell->type.in(ID($not), ID($pos), ID($and), ID($or), ID($xor), ID($xnor)))
if (group_cell_inputs(module, cell, true, assign_map))
goto next_cell;
- if (cell->type.in("$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool"))
+ if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_or), ID($reduce_and), ID($reduce_bool)))
{
- SigBit neutral_bit = cell->type == "$reduce_and" ? State::S1 : State::S0;
+ SigBit neutral_bit = cell->type == ID($reduce_and) ? State::S1 : State::S0;
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
RTLIL::SigSpec new_sig_a;
for (auto bit : sig_a)
cover_list("opt.opt_expr.fine.neutral_A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool", cell->type.str());
log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
- cell->setPort("\\A", new_sig_a);
- cell->parameters.at("\\A_WIDTH") = GetSize(new_sig_a);
+ cell->setPort(ID(A), new_sig_a);
+ cell->parameters.at(ID(A_WIDTH)) = GetSize(new_sig_a);
did_something = true;
}
}
- if (cell->type.in("$logic_and", "$logic_or"))
+ if (cell->type.in(ID($logic_and), ID($logic_or)))
{
SigBit neutral_bit = State::S0;
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B)));
RTLIL::SigSpec new_sig_b;
for (auto bit : sig_b)
cover_list("opt.opt_expr.fine.neutral_B", "$logic_and", "$logic_or", cell->type.str());
log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
- cell->setPort("\\B", new_sig_b);
- cell->parameters.at("\\B_WIDTH") = GetSize(new_sig_b);
+ cell->setPort(ID(B), new_sig_b);
+ cell->parameters.at(ID(B_WIDTH)) = GetSize(new_sig_b);
did_something = true;
}
}
- if (cell->type == "$reduce_and")
+ if (cell->type == ID($reduce_and))
{
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
RTLIL::State new_a = RTLIL::State::S1;
for (auto &bit : sig_a.to_sigbit_vector())
cover("opt.opt_expr.fine.$reduce_and");
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
- cell->setPort("\\A", sig_a = new_a);
- cell->parameters.at("\\A_WIDTH") = 1;
+ cell->setPort(ID(A), sig_a = new_a);
+ cell->parameters.at(ID(A_WIDTH)) = 1;
did_something = true;
}
}
- if (cell->type.in("$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool"))
+ if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_or), ID($reduce_bool)))
{
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
RTLIL::State new_a = RTLIL::State::S0;
for (auto &bit : sig_a.to_sigbit_vector())
cover_list("opt.opt_expr.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str());
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
- cell->setPort("\\A", sig_a = new_a);
- cell->parameters.at("\\A_WIDTH") = 1;
+ cell->setPort(ID(A), sig_a = new_a);
+ cell->parameters.at(ID(A_WIDTH)) = 1;
did_something = true;
}
}
- if (cell->type.in("$logic_and", "$logic_or"))
+ if (cell->type.in(ID($logic_and), ID($logic_or)))
{
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B)));
RTLIL::State new_b = RTLIL::State::S0;
for (auto &bit : sig_b.to_sigbit_vector())
cover_list("opt.opt_expr.fine.B", "$logic_and", "$logic_or", cell->type.str());
log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
- cell->setPort("\\B", sig_b = new_b);
- cell->parameters.at("\\B_WIDTH") = 1;
+ cell->setPort(ID(B), sig_b = new_b);
+ cell->parameters.at(ID(B_WIDTH)) = 1;
did_something = true;
}
}
- if (cell->type.in("$add", "$sub")) {
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_y = cell->getPort("\\Y");
- bool sub = cell->type == "$sub";
+ if (cell->type.in(ID($add), ID($sub))) {
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B)));
+ RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ bool sub = cell->type == ID($sub);
int i;
for (i = 0; i < GetSize(sig_y); i++) {
}
if (i > 0) {
cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
- cell->setPort("\\A", sig_a.extract_end(i));
- cell->setPort("\\B", sig_b.extract_end(i));
- cell->setPort("\\Y", sig_y.extract_end(i));
+ cell->setPort(ID(A), sig_a.extract_end(i));
+ cell->setPort(ID(B), sig_b.extract_end(i));
+ cell->setPort(ID(Y), sig_y.extract_end(i));
cell->fixup_parameters();
did_something = true;
}
}
}
- if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr",
- "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow"))
+ if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($shift), ID($shiftx), ID($shl), ID($shr), ID($sshl), ID($sshr),
+ ID($lt), ID($le), ID($ge), ID($gt), ID($neg), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow)))
{
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec sig_b = cell->hasPort(ID(B)) ? assign_map(cell->getPort(ID(B))) : RTLIL::SigSpec();
- if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
+ if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
sig_a = RTLIL::SigSpec();
for (auto &bit : sig_a.to_sigbit_vector())
found_the_x_bit:
cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str());
- if (cell->type.in("$reduce_xor", "$reduce_xnor", "$lt", "$le", "$ge", "$gt"))
+ if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
else
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort("\\Y").size()));
}
}
- if (cell->type.in("$_NOT_", "$not", "$logic_not") && cell->getPort("\\Y").size() == 1 &&
- invert_map.count(assign_map(cell->getPort("\\A"))) != 0) {
+ if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID(Y)).size() == 1 &&
+ invert_map.count(assign_map(cell->getPort(ID(A)))) != 0) {
cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A"))));
goto next_cell;
}
- if (cell->type.in("$_MUX_", "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
+ if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID(S)))) != 0) {
cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
- RTLIL::SigSpec tmp = cell->getPort("\\A");
- cell->setPort("\\A", cell->getPort("\\B"));
- cell->setPort("\\B", tmp);
- cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S"))));
+ RTLIL::SigSpec tmp = cell->getPort(ID(A));
+ cell->setPort(ID(A), cell->getPort(ID(B)));
+ cell->setPort(ID(B), tmp);
+ cell->setPort(ID(S), invert_map.at(assign_map(cell->getPort(ID(S)))));
did_something = true;
goto next_cell;
}
- if (cell->type == "$_NOT_") {
- RTLIL::SigSpec input = cell->getPort("\\A");
+ if (cell->type == ID($_NOT_)) {
+ RTLIL::SigSpec input = cell->getPort(ID(A));
assign_map.apply(input);
if (input.match("1")) ACTION_DO_Y(0);
if (input.match("0")) ACTION_DO_Y(1);
if (input.match("*")) ACTION_DO_Y(x);
}
- if (cell->type == "$_AND_") {
+ if (cell->type == ID($_AND_)) {
RTLIL::SigSpec input;
- input.append(cell->getPort("\\B"));
- input.append(cell->getPort("\\A"));
+ input.append(cell->getPort(ID(B)));
+ input.append(cell->getPort(ID(A)));
assign_map.apply(input);
if (input.match(" 0")) ACTION_DO_Y(0);
if (input.match("0 ")) ACTION_DO_Y(0);
if (input.match(" *")) ACTION_DO_Y(0);
if (input.match("* ")) ACTION_DO_Y(0);
}
- if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1));
- if (input.match("1 ")) ACTION_DO("\\Y", input.extract(0, 1));
+ if (input.match(" 1")) ACTION_DO(ID(Y), input.extract(1, 1));
+ if (input.match("1 ")) ACTION_DO(ID(Y), input.extract(0, 1));
}
- if (cell->type == "$_OR_") {
+ if (cell->type == ID($_OR_)) {
RTLIL::SigSpec input;
- input.append(cell->getPort("\\B"));
- input.append(cell->getPort("\\A"));
+ input.append(cell->getPort(ID(B)));
+ input.append(cell->getPort(ID(A)));
assign_map.apply(input);
if (input.match(" 1")) ACTION_DO_Y(1);
if (input.match("1 ")) ACTION_DO_Y(1);
if (input.match(" *")) ACTION_DO_Y(1);
if (input.match("* ")) ACTION_DO_Y(1);
}
- if (input.match(" 0")) ACTION_DO("\\Y", input.extract(1, 1));
- if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1));
+ if (input.match(" 0")) ACTION_DO(ID(Y), input.extract(1, 1));
+ if (input.match("0 ")) ACTION_DO(ID(Y), input.extract(0, 1));
}
- if (cell->type == "$_XOR_") {
+ if (cell->type == ID($_XOR_)) {
RTLIL::SigSpec input;
- input.append(cell->getPort("\\B"));
- input.append(cell->getPort("\\A"));
+ input.append(cell->getPort(ID(B)));
+ input.append(cell->getPort(ID(A)));
assign_map.apply(input);
if (input.match("00")) ACTION_DO_Y(0);
if (input.match("01")) ACTION_DO_Y(1);
if (input.match("11")) ACTION_DO_Y(0);
if (input.match(" *")) ACTION_DO_Y(x);
if (input.match("* ")) ACTION_DO_Y(x);
- if (input.match(" 0")) ACTION_DO("\\Y", input.extract(1, 1));
- if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1));
+ if (input.match(" 0")) ACTION_DO(ID(Y), input.extract(1, 1));
+ if (input.match("0 ")) ACTION_DO(ID(Y), input.extract(0, 1));
}
- if (cell->type == "$_MUX_") {
+ if (cell->type == ID($_MUX_)) {
RTLIL::SigSpec input;
- input.append(cell->getPort("\\S"));
- input.append(cell->getPort("\\B"));
- input.append(cell->getPort("\\A"));
+ input.append(cell->getPort(ID(S)));
+ input.append(cell->getPort(ID(B)));
+ input.append(cell->getPort(ID(A)));
assign_map.apply(input);
if (input.extract(2, 1) == input.extract(1, 1))
- ACTION_DO("\\Y", input.extract(2, 1));
- if (input.match(" 0")) ACTION_DO("\\Y", input.extract(2, 1));
- if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1));
- if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1));
+ ACTION_DO(ID(Y), input.extract(2, 1));
+ if (input.match(" 0")) ACTION_DO(ID(Y), input.extract(2, 1));
+ if (input.match(" 1")) ACTION_DO(ID(Y), input.extract(1, 1));
+ if (input.match("01 ")) ACTION_DO(ID(Y), input.extract(0, 1));
if (input.match("10 ")) {
cover("opt.opt_expr.mux_to_inv");
- cell->type = "$_NOT_";
- cell->setPort("\\A", input.extract(0, 1));
- cell->unsetPort("\\B");
- cell->unsetPort("\\S");
+ cell->type = ID($_NOT_);
+ cell->setPort(ID(A), input.extract(0, 1));
+ cell->unsetPort(ID(B));
+ cell->unsetPort(ID(S));
goto next_cell;
}
if (input.match("11 ")) ACTION_DO_Y(1);
if (input.match("01*")) ACTION_DO_Y(x);
if (input.match("10*")) ACTION_DO_Y(x);
if (mux_undef) {
- if (input.match("* ")) ACTION_DO("\\Y", input.extract(1, 1));
- if (input.match(" * ")) ACTION_DO("\\Y", input.extract(2, 1));
- if (input.match(" *")) ACTION_DO("\\Y", input.extract(2, 1));
+ if (input.match("* ")) ACTION_DO(ID(Y), input.extract(1, 1));
+ if (input.match(" * ")) ACTION_DO(ID(Y), input.extract(2, 1));
+ if (input.match(" *")) ACTION_DO(ID(Y), input.extract(2, 1));
}
}
- if (cell->type.in("$_TBUF_", "$tribuf")) {
- RTLIL::SigSpec input = cell->getPort(cell->type == "$_TBUF_" ? "\\E" : "\\EN");
- RTLIL::SigSpec a = cell->getPort("\\A");
+ if (cell->type.in(ID($_TBUF_), ID($tribuf))) {
+ RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID(E) : ID(EN));
+ RTLIL::SigSpec a = cell->getPort(ID(A));
assign_map.apply(input);
assign_map.apply(a);
if (input == State::S1)
- ACTION_DO("\\Y", cell->getPort("\\A"));
+ ACTION_DO(ID(Y), cell->getPort(ID(A)));
if (input == State::S0 && !a.is_fully_undef()) {
cover("opt.opt_expr.action_" S__LINE__);
log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str());
- cell->setPort("\\A", SigSpec(State::Sx, GetSize(a)));
+ cell->setPort(ID(A), SigSpec(State::Sx, GetSize(a)));
did_something = true;
goto next_cell;
}
}
- if (cell->type.in("$eq", "$ne", "$eqx", "$nex"))
+ if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
{
- RTLIL::SigSpec a = cell->getPort("\\A");
- RTLIL::SigSpec b = cell->getPort("\\B");
+ RTLIL::SigSpec a = cell->getPort(ID(A));
+ RTLIL::SigSpec b = cell->getPort(ID(B));
- if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
- int width = max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
- a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
- b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+ if (cell->parameters[ID(A_WIDTH)].as_int() != cell->parameters[ID(B_WIDTH)].as_int()) {
+ int width = max(cell->parameters[ID(A_WIDTH)].as_int(), cell->parameters[ID(B_WIDTH)].as_int());
+ a.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool());
+ b.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool());
}
RTLIL::SigSpec new_a, new_b;
for (int i = 0; i < GetSize(a); i++) {
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
- RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in("$eq", "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1);
- new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
+ RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
+ new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false);
replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y);
goto next_cell;
}
if (new_a.size() == 0) {
cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
- RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in("$eq", "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0);
- new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
- replace_cell(assign_map, module, cell, "empty", "\\Y", new_y);
+ RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0);
+ new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false);
+ replace_cell(assign_map, module, cell, "empty", ID(Y), new_y);
goto next_cell;
}
if (new_a.size() < a.size() || new_b.size() < b.size()) {
cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
- cell->setPort("\\A", new_a);
- cell->setPort("\\B", new_b);
- cell->parameters["\\A_WIDTH"] = new_a.size();
- cell->parameters["\\B_WIDTH"] = new_b.size();
+ cell->setPort(ID(A), new_a);
+ cell->setPort(ID(B), new_b);
+ cell->parameters[ID(A_WIDTH)] = new_a.size();
+ cell->parameters[ID(B_WIDTH)] = new_b.size();
}
}
- if (cell->type.in("$eq", "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
- cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
+ if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID(Y_WIDTH)].as_int() == 1 &&
+ cell->parameters[ID(A_WIDTH)].as_int() == 1 && cell->parameters[ID(B_WIDTH)].as_int() == 1)
{
- RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec b = assign_map(cell->getPort(ID(B)));
if (a.is_fully_const() && !b.is_fully_const()) {
cover_list("opt.opt_expr.eqneq.swapconst", "$eq", "$ne", cell->type.str());
- cell->setPort("\\A", b);
- cell->setPort("\\B", a);
+ cell->setPort(ID(A), b);
+ cell->setPort(ID(B), a);
std::swap(a, b);
}
if (b.is_fully_const()) {
- if (b.as_bool() == (cell->type == "$eq")) {
+ if (b.as_bool() == (cell->type == ID($eq))) {
RTLIL::SigSpec input = b;
- ACTION_DO("\\Y", cell->getPort("\\A"));
+ ACTION_DO(ID(Y), cell->getPort(ID(A)));
} else {
cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->type = "$not";
- cell->parameters.erase("\\B_WIDTH");
- cell->parameters.erase("\\B_SIGNED");
- cell->unsetPort("\\B");
+ cell->type = ID($not);
+ cell->parameters.erase(ID(B_WIDTH));
+ cell->parameters.erase(ID(B_SIGNED));
+ cell->unsetPort(ID(B));
did_something = true;
}
goto next_cell;
}
}
- if (cell->type.in("$eq", "$ne") &&
- (assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero()))
+ if (cell->type.in(ID($eq), ID($ne)) &&
+ (assign_map(cell->getPort(ID(A))).is_fully_zero() || assign_map(cell->getPort(ID(B))).is_fully_zero()))
{
cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
log_id(module), "$eq" ? "$logic_not" : "$reduce_bool");
- cell->type = cell->type == "$eq" ? "$logic_not" : "$reduce_bool";
- if (assign_map(cell->getPort("\\A")).is_fully_zero()) {
- cell->setPort("\\A", cell->getPort("\\B"));
- cell->setParam("\\A_SIGNED", cell->getParam("\\B_SIGNED"));
- cell->setParam("\\A_WIDTH", cell->getParam("\\B_WIDTH"));
+ cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
+ if (assign_map(cell->getPort(ID(A))).is_fully_zero()) {
+ cell->setPort(ID(A), cell->getPort(ID(B)));
+ cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED)));
+ cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH)));
}
- cell->unsetPort("\\B");
- cell->unsetParam("\\B_SIGNED");
- cell->unsetParam("\\B_WIDTH");
+ cell->unsetPort(ID(B));
+ cell->unsetParam(ID(B_SIGNED));
+ cell->unsetParam(ID(B_WIDTH));
did_something = true;
goto next_cell;
}
- if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx") && assign_map(cell->getPort("\\B")).is_fully_const())
+ if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && assign_map(cell->getPort(ID(B))).is_fully_const())
{
- bool sign_ext = cell->type == "$sshr" && cell->getParam("\\A_SIGNED").as_bool();
- int shift_bits = assign_map(cell->getPort("\\B")).as_int(cell->type.in("$shift", "$shiftx") && cell->getParam("\\B_SIGNED").as_bool());
+ bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID(A_SIGNED)).as_bool();
+ int shift_bits = assign_map(cell->getPort(ID(B))).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID(B_SIGNED)).as_bool());
- if (cell->type.in("$shl", "$sshl"))
+ if (cell->type.in(ID($shl), ID($sshl)))
shift_bits *= -1;
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_y(cell->type == "$shiftx" ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam("\\Y_WIDTH").as_int());
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID(Y_WIDTH)).as_int());
if (GetSize(sig_a) < GetSize(sig_y))
- sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID(A_SIGNED)).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
int idx = i + shift_bits;
cover_list("opt.opt_expr.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str());
log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
- log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort("\\B"))), shift_bits, log_id(module), log_signal(sig_y));
+ log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort(ID(B)))), shift_bits, log_id(module), log_signal(sig_y));
- module->connect(cell->getPort("\\Y"), sig_y);
+ module->connect(cell->getPort(ID(Y)), sig_y);
module->remove(cell);
did_something = true;
bool identity_wrt_b = false;
bool arith_inverse = false;
- if (cell->type.in("$add", "$sub", "$or", "$xor"))
+ if (cell->type.in(ID($add), ID($sub), ID($or), ID($xor)))
{
- RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec b = assign_map(cell->getPort(ID(B)));
- if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false)
+ if (cell->type != ID($sub) && a.is_fully_const() && a.as_bool() == false)
identity_wrt_b = true;
if (b.is_fully_const() && b.as_bool() == false)
identity_wrt_a = true;
}
- if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
+ if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{
- RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec b = assign_map(cell->getPort(ID(B)));
if (b.is_fully_const() && b.as_bool() == false)
identity_wrt_a = true;
}
- if (cell->type == "$mul")
+ if (cell->type == ID($mul))
{
- RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec b = assign_map(cell->getPort(ID(B)));
- if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam("\\A_SIGNED").as_bool(), arith_inverse))
+ if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID(A_SIGNED)).as_bool(), arith_inverse))
identity_wrt_b = true;
else
- if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam("\\B_SIGNED").as_bool(), arith_inverse))
+ if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID(B_SIGNED)).as_bool(), arith_inverse))
identity_wrt_a = true;
}
- if (cell->type == "$div")
+ if (cell->type == ID($div))
{
- RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec b = assign_map(cell->getPort(ID(B)));
if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
identity_wrt_a = true;
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
if (!identity_wrt_a) {
- cell->setPort("\\A", cell->getPort("\\B"));
- cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
- cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
+ cell->setPort(ID(A), cell->getPort(ID(B)));
+ cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH));
+ cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED));
}
- cell->type = arith_inverse ? "$neg" : "$pos";
- cell->unsetPort("\\B");
- cell->parameters.erase("\\B_WIDTH");
- cell->parameters.erase("\\B_SIGNED");
+ cell->type = arith_inverse ? ID($neg) : ID($pos);
+ cell->unsetPort(ID(B));
+ cell->parameters.erase(ID(B_WIDTH));
+ cell->parameters.erase(ID(B_SIGNED));
cell->check();
did_something = true;
}
}
- if (mux_bool && cell->type.in("$mux", "$_MUX_") &&
- cell->getPort("\\A") == State::S0 && cell->getPort("\\B") == State::S1) {
+ if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
+ cell->getPort(ID(A)) == State::S0 && cell->getPort(ID(B)) == State::S1) {
cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str());
- replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S"));
+ replace_cell(assign_map, module, cell, "mux_bool", ID(Y), cell->getPort(ID(S)));
goto next_cell;
}
- if (mux_bool && cell->type.in("$mux", "$_MUX_") &&
- cell->getPort("\\A") == State::S1 && cell->getPort("\\B") == State::S0) {
+ if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
+ cell->getPort(ID(A)) == State::S1 && cell->getPort(ID(B)) == State::S0) {
cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort("\\A", cell->getPort("\\S"));
- cell->unsetPort("\\B");
- cell->unsetPort("\\S");
- if (cell->type == "$mux") {
- Const width = cell->parameters["\\WIDTH"];
- cell->parameters["\\A_WIDTH"] = width;
- cell->parameters["\\Y_WIDTH"] = width;
- cell->parameters["\\A_SIGNED"] = 0;
- cell->parameters.erase("\\WIDTH");
- cell->type = "$not";
+ cell->setPort(ID(A), cell->getPort(ID(S)));
+ cell->unsetPort(ID(B));
+ cell->unsetPort(ID(S));
+ if (cell->type == ID($mux)) {
+ Const width = cell->parameters[ID(WIDTH)];
+ cell->parameters[ID(A_WIDTH)] = width;
+ cell->parameters[ID(Y_WIDTH)] = width;
+ cell->parameters[ID(A_SIGNED)] = 0;
+ cell->parameters.erase(ID(WIDTH));
+ cell->type = ID($not);
} else
- cell->type = "$_NOT_";
+ cell->type = ID($_NOT_);
did_something = true;
goto next_cell;
}
- if (consume_x && mux_bool && cell->type.in("$mux", "$_MUX_") && cell->getPort("\\A") == State::S0) {
+ if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID(A)) == State::S0) {
cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort("\\A", cell->getPort("\\S"));
- cell->unsetPort("\\S");
- if (cell->type == "$mux") {
- Const width = cell->parameters["\\WIDTH"];
- cell->parameters["\\A_WIDTH"] = width;
- cell->parameters["\\B_WIDTH"] = width;
- cell->parameters["\\Y_WIDTH"] = width;
- cell->parameters["\\A_SIGNED"] = 0;
- cell->parameters["\\B_SIGNED"] = 0;
- cell->parameters.erase("\\WIDTH");
- cell->type = "$and";
+ cell->setPort(ID(A), cell->getPort(ID(S)));
+ cell->unsetPort(ID(S));
+ if (cell->type == ID($mux)) {
+ Const width = cell->parameters[ID(WIDTH)];
+ cell->parameters[ID(A_WIDTH)] = width;
+ cell->parameters[ID(B_WIDTH)] = width;
+ cell->parameters[ID(Y_WIDTH)] = width;
+ cell->parameters[ID(A_SIGNED)] = 0;
+ cell->parameters[ID(B_SIGNED)] = 0;
+ cell->parameters.erase(ID(WIDTH));
+ cell->type = ID($and);
} else
- cell->type = "$_AND_";
+ cell->type = ID($_AND_);
did_something = true;
goto next_cell;
}
- if (consume_x && mux_bool && cell->type.in("$mux", "$_MUX_") && cell->getPort("\\B") == State::S1) {
+ if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID(B)) == State::S1) {
cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort("\\B", cell->getPort("\\S"));
- cell->unsetPort("\\S");
- if (cell->type == "$mux") {
- Const width = cell->parameters["\\WIDTH"];
- cell->parameters["\\A_WIDTH"] = width;
- cell->parameters["\\B_WIDTH"] = width;
- cell->parameters["\\Y_WIDTH"] = width;
- cell->parameters["\\A_SIGNED"] = 0;
- cell->parameters["\\B_SIGNED"] = 0;
- cell->parameters.erase("\\WIDTH");
- cell->type = "$or";
+ cell->setPort(ID(B), cell->getPort(ID(S)));
+ cell->unsetPort(ID(S));
+ if (cell->type == ID($mux)) {
+ Const width = cell->parameters[ID(WIDTH)];
+ cell->parameters[ID(A_WIDTH)] = width;
+ cell->parameters[ID(B_WIDTH)] = width;
+ cell->parameters[ID(Y_WIDTH)] = width;
+ cell->parameters[ID(A_SIGNED)] = 0;
+ cell->parameters[ID(B_SIGNED)] = 0;
+ cell->parameters.erase(ID(WIDTH));
+ cell->type = ID($or);
} else
- cell->type = "$_OR_";
+ cell->type = ID($_OR_);
did_something = true;
goto next_cell;
}
- if (mux_undef && cell->type.in("$mux", "$pmux")) {
+ if (mux_undef && cell->type.in(ID($mux), ID($pmux))) {
RTLIL::SigSpec new_a, new_b, new_s;
- int width = cell->getPort("\\A").size();
- if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) ||
- cell->getPort("\\S").is_fully_undef()) {
+ int width = cell->getPort(ID(A)).size();
+ if ((cell->getPort(ID(A)).is_fully_undef() && cell->getPort(ID(B)).is_fully_undef()) ||
+ cell->getPort(ID(S)).is_fully_undef()) {
cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str());
- replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A"));
+ replace_cell(assign_map, module, cell, "mux_undef", ID(Y), cell->getPort(ID(A)));
goto next_cell;
}
- for (int i = 0; i < cell->getPort("\\S").size(); i++) {
- RTLIL::SigSpec old_b = cell->getPort("\\B").extract(i*width, width);
- RTLIL::SigSpec old_s = cell->getPort("\\S").extract(i, 1);
+ for (int i = 0; i < cell->getPort(ID(S)).size(); i++) {
+ RTLIL::SigSpec old_b = cell->getPort(ID(B)).extract(i*width, width);
+ RTLIL::SigSpec old_s = cell->getPort(ID(S)).extract(i, 1);
if (old_b.is_fully_undef() || old_s.is_fully_undef())
continue;
new_b.append(old_b);
new_s.append(old_s);
}
- new_a = cell->getPort("\\A");
+ new_a = cell->getPort(ID(A));
if (new_a.is_fully_undef() && new_s.size() > 0) {
new_a = new_b.extract((new_s.size()-1)*width, width);
new_b = new_b.extract(0, (new_s.size()-1)*width);
}
if (new_s.size() == 0) {
cover_list("opt.opt_expr.mux_empty", "$mux", "$pmux", cell->type.str());
- replace_cell(assign_map, module, cell, "mux_empty", "\\Y", new_a);
+ replace_cell(assign_map, module, cell, "mux_empty", ID(Y), new_a);
goto next_cell;
}
if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) {
cover_list("opt.opt_expr.mux_sel01", "$mux", "$pmux", cell->type.str());
- replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s);
+ replace_cell(assign_map, module, cell, "mux_sel01", ID(Y), new_s);
goto next_cell;
}
- if (cell->getPort("\\S").size() != new_s.size()) {
+ if (cell->getPort(ID(S)).size() != new_s.size()) {
cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str());
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
- GetSize(cell->getPort("\\S")) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort("\\A", new_a);
- cell->setPort("\\B", new_b);
- cell->setPort("\\S", new_s);
+ GetSize(cell->getPort(ID(S))) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
+ cell->setPort(ID(A), new_a);
+ cell->setPort(ID(B), new_b);
+ cell->setPort(ID(S), new_s);
if (new_s.size() > 1) {
- cell->type = "$pmux";
- cell->parameters["\\S_WIDTH"] = new_s.size();
+ cell->type = ID($pmux);
+ cell->parameters[ID(S_WIDTH)] = new_s.size();
} else {
- cell->type = "$mux";
- cell->parameters.erase("\\S_WIDTH");
+ cell->type = ID($mux);
+ cell->parameters.erase(ID(S_WIDTH));
}
did_something = true;
}
#define FOLD_1ARG_CELL(_t) \
if (cell->type == "$" #_t) { \
- RTLIL::SigSpec a = cell->getPort("\\A"); \
+ RTLIL::SigSpec a = cell->getPort(ID(A)); \
assign_map.apply(a); \
if (a.is_fully_const()) { \
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
- cell->parameters["\\A_SIGNED"].as_bool(), false, \
- cell->parameters["\\Y_WIDTH"].as_int())); \
+ cell->parameters[ID(A_SIGNED)].as_bool(), false, \
+ cell->parameters[ID(Y_WIDTH)].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
- replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
+ replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID(Y), y); \
goto next_cell; \
} \
}
#define FOLD_2ARG_CELL(_t) \
if (cell->type == "$" #_t) { \
- RTLIL::SigSpec a = cell->getPort("\\A"); \
- RTLIL::SigSpec b = cell->getPort("\\B"); \
+ RTLIL::SigSpec a = cell->getPort(ID(A)); \
+ RTLIL::SigSpec b = cell->getPort(ID(B)); \
assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
- cell->parameters["\\A_SIGNED"].as_bool(), \
- cell->parameters["\\B_SIGNED"].as_bool(), \
- cell->parameters["\\Y_WIDTH"].as_int())); \
+ cell->parameters[ID(A_SIGNED)].as_bool(), \
+ cell->parameters[ID(B_SIGNED)].as_bool(), \
+ cell->parameters[ID(Y_WIDTH)].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
- replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), "\\Y", y); \
+ replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID(Y), y); \
goto next_cell; \
} \
}
FOLD_1ARG_CELL(neg)
// be very conservative with optimizing $mux cells as we do not want to break mux trees
- if (cell->type == "$mux") {
- RTLIL::SigSpec input = assign_map(cell->getPort("\\S"));
- RTLIL::SigSpec inA = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec inB = assign_map(cell->getPort("\\B"));
+ if (cell->type == ID($mux)) {
+ RTLIL::SigSpec input = assign_map(cell->getPort(ID(S)));
+ RTLIL::SigSpec inA = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec inB = assign_map(cell->getPort(ID(B)));
if (input.is_fully_const())
- ACTION_DO("\\Y", input.as_bool() ? cell->getPort("\\B") : cell->getPort("\\A"));
+ ACTION_DO(ID(Y), input.as_bool() ? cell->getPort(ID(B)) : cell->getPort(ID(A)));
else if (inA == inB)
- ACTION_DO("\\Y", cell->getPort("\\A"));
+ ACTION_DO(ID(Y), cell->getPort(ID(A)));
}
- if (!keepdc && cell->type == "$mul")
+ if (!keepdc && cell->type == ID($mul))
{
- bool a_signed = cell->parameters["\\A_SIGNED"].as_bool();
- bool b_signed = cell->parameters["\\B_SIGNED"].as_bool();
+ bool a_signed = cell->parameters[ID(A_SIGNED)].as_bool();
+ bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool();
bool swapped_ab = false;
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B)));
+ RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID(Y)));
if (sig_b.is_fully_const() && sig_b.size() <= 32)
std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
a_val, cell->name.c_str(), module->name.c_str(), i);
if (!swapped_ab) {
- cell->setPort("\\A", cell->getPort("\\B"));
- cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
- cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
+ cell->setPort(ID(A), cell->getPort(ID(B)));
+ cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH));
+ cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED));
}
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
while (GetSize(new_b) > 1 && new_b.back() == RTLIL::State::S0)
new_b.pop_back();
- cell->type = "$shl";
- cell->parameters["\\B_WIDTH"] = GetSize(new_b);
- cell->parameters["\\B_SIGNED"] = false;
- cell->setPort("\\B", new_b);
+ cell->type = ID($shl);
+ cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
+ cell->parameters[ID(B_SIGNED)] = false;
+ cell->setPort(ID(B), new_b);
cell->check();
did_something = true;
}
}
- if (!keepdc && cell->type.in("$div", "$mod"))
+ if (!keepdc && cell->type.in(ID($div), ID($mod)))
{
- bool b_signed = cell->parameters["\\B_SIGNED"].as_bool();
- SigSpec sig_b = assign_map(cell->getPort("\\B"));
- SigSpec sig_y = assign_map(cell->getPort("\\Y"));
+ bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool();
+ SigSpec sig_b = assign_map(cell->getPort(ID(B)));
+ SigSpec sig_y = assign_map(cell->getPort(ID(Y)));
if (sig_b.is_fully_def() && sig_b.size() <= 32)
{
for (int i = 1; i < (b_signed ? sig_b.size()-1 : sig_b.size()); i++)
if (b_val == (1 << i))
{
- if (cell->type == "$div")
+ if (cell->type == ID($div))
{
cover("opt.opt_expr.div_shift");
while (GetSize(new_b) > 1 && new_b.back() == RTLIL::State::S0)
new_b.pop_back();
- cell->type = "$shr";
- cell->parameters["\\B_WIDTH"] = GetSize(new_b);
- cell->parameters["\\B_SIGNED"] = false;
- cell->setPort("\\B", new_b);
+ cell->type = ID($shr);
+ cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
+ cell->parameters[ID(B_SIGNED)] = false;
+ cell->setPort(ID(B), new_b);
cell->check();
}
else
if (b_signed)
new_b.push_back(State::S0);
- cell->type = "$and";
- cell->parameters["\\B_WIDTH"] = GetSize(new_b);
- cell->setPort("\\B", new_b);
+ cell->type = ID($and);
+ cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
+ cell->setPort(ID(B), new_b);
cell->check();
}
// remove redundant pairs of bits in ==, ===, !=, and !==
// replace cell with const driver if inputs can't be equal
- if (do_fine && cell->type.in("$eq", "$ne", "$eqx", "$nex"))
+ if (do_fine && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex)))
{
pool<pair<SigBit, SigBit>> redundant_cache;
mfp<SigBit> contradiction_cache;
contradiction_cache.promote(State::S0);
contradiction_cache.promote(State::S1);
- int a_width = cell->getParam("\\A_WIDTH").as_int();
- int b_width = cell->getParam("\\B_WIDTH").as_int();
+ int a_width = cell->getParam(ID(A_WIDTH)).as_int();
+ int b_width = cell->getParam(ID(B_WIDTH)).as_int();
- bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+ bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
int width = is_signed ? std::min(a_width, b_width) : std::max(a_width, b_width);
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_b = cell->getPort("\\B");
+ SigSpec sig_a = cell->getPort(ID(A));
+ SigSpec sig_b = cell->getPort(ID(B));
int redundant_bits = 0;
if (contradiction_cache.find(State::S0) == contradiction_cache.find(State::S1))
{
- SigSpec y_sig = cell->getPort("\\Y");
- Const y_value(cell->type.in("$eq", "$eqx") ? 0 : 1, GetSize(y_sig));
+ SigSpec y_sig = cell->getPort(ID(Y));
+ Const y_value(cell->type.in(ID($eq), ID($eqx)) ? 0 : 1, GetSize(y_sig));
log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
log_id(cell), log_id(module), log_signal(y_value));
log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
redundant_bits, log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort("\\A", sig_a);
- cell->setPort("\\B", sig_b);
- cell->setParam("\\A_WIDTH", GetSize(sig_a));
- cell->setParam("\\B_WIDTH", GetSize(sig_b));
+ cell->setPort(ID(A), sig_a);
+ cell->setPort(ID(B), sig_b);
+ cell->setParam(ID(A_WIDTH), GetSize(sig_a));
+ cell->setParam(ID(B_WIDTH), GetSize(sig_b));
did_something = true;
goto next_cell;
}
// simplify comparisons
- if (do_fine && cell->type.in("$lt", "$ge", "$gt", "$le"))
+ if (do_fine && cell->type.in(ID($lt), ID($ge), ID($gt), ID($le)))
{
IdString cmp_type = cell->type;
- SigSpec var_sig = cell->getPort("\\A");
- SigSpec const_sig = cell->getPort("\\B");
- int var_width = cell->parameters["\\A_WIDTH"].as_int();
- int const_width = cell->parameters["\\B_WIDTH"].as_int();
- bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+ SigSpec var_sig = cell->getPort(ID(A));
+ SigSpec const_sig = cell->getPort(ID(B));
+ int var_width = cell->parameters[ID(A_WIDTH)].as_int();
+ int const_width = cell->parameters[ID(B_WIDTH)].as_int();
+ bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
if (!const_sig.is_fully_const())
{
std::swap(var_sig, const_sig);
std::swap(var_width, const_width);
- if (cmp_type == "$gt")
- cmp_type = "$lt";
- else if (cmp_type == "$lt")
- cmp_type = "$gt";
- else if (cmp_type == "$ge")
- cmp_type = "$le";
- else if (cmp_type == "$le")
- cmp_type = "$ge";
+ if (cmp_type == ID($gt))
+ cmp_type = ID($lt);
+ else if (cmp_type == ID($lt))
+ cmp_type = ID($gt);
+ else if (cmp_type == ID($ge))
+ cmp_type = ID($le);
+ else if (cmp_type == ID($le))
+ cmp_type = ID($ge);
}
if (const_sig.is_fully_def() && const_sig.is_fully_const())
{
std::string condition, replacement;
- SigSpec replace_sig(State::S0, GetSize(cell->getPort("\\Y")));
+ SigSpec replace_sig(State::S0, GetSize(cell->getPort(ID(Y))));
bool replace = false;
bool remove = false;
if (!is_signed)
{ /* unsigned */
- if (const_sig.is_fully_zero() && cmp_type == "$lt") {
+ if (const_sig.is_fully_zero() && cmp_type == ID($lt)) {
condition = "unsigned X<0";
replacement = "constant 0";
replace_sig[0] = State::S0;
replace = true;
}
- if (const_sig.is_fully_zero() && cmp_type == "$ge") {
+ if (const_sig.is_fully_zero() && cmp_type == ID($ge)) {
condition = "unsigned X>=0";
replacement = "constant 1";
replace_sig[0] = State::S1;
replace = true;
}
- if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$gt") {
+ if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == ID($gt)) {
condition = "unsigned X>~0";
replacement = "constant 0";
replace_sig[0] = State::S0;
replace = true;
}
- if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$le") {
+ if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == ID($le)) {
condition = "unsigned X<=~0";
replacement = "constant 1";
replace_sig[0] = State::S1;
var_high_sig[i - const_bit_hot] = var_sig[i];
}
- if (cmp_type == "$lt")
+ if (cmp_type == ID($lt))
{
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
- module->addLogicNot(NEW_ID, var_high_sig, cell->getPort("\\Y"));
+ module->addLogicNot(NEW_ID, var_high_sig, cell->getPort(ID(Y)));
remove = true;
}
- if (cmp_type == "$ge")
+ if (cmp_type == ID($ge))
{
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
- module->addReduceOr(NEW_ID, var_high_sig, cell->getPort("\\Y"));
+ module->addReduceOr(NEW_ID, var_high_sig, cell->getPort(ID(Y)));
remove = true;
}
}
if(const_bit_set >= var_width)
{
string cmp_name;
- if (cmp_type == "$lt" || cmp_type == "$le")
+ if (cmp_type == ID($lt) || cmp_type == ID($le))
{
- if (cmp_type == "$lt") cmp_name = "<";
- if (cmp_type == "$le") cmp_name = "<=";
+ if (cmp_type == ID($lt)) cmp_name = "<";
+ if (cmp_type == ID($le)) cmp_name = "<=";
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
replacement = "constant 1";
replace_sig[0] = State::S1;
replace = true;
}
- if (cmp_type == "$gt" || cmp_type == "$ge")
+ if (cmp_type == ID($gt) || cmp_type == ID($ge))
{
- if (cmp_type == "$gt") cmp_name = ">";
- if (cmp_type == "$ge") cmp_name = ">=";
+ if (cmp_type == ID($gt)) cmp_name = ">";
+ if (cmp_type == ID($ge)) cmp_name = ">=";
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
replacement = "constant 0";
replace_sig[0] = State::S0;
}
else
{ /* signed */
- if (const_sig.is_fully_zero() && cmp_type == "$lt")
+ if (const_sig.is_fully_zero() && cmp_type == ID($lt))
{
condition = "signed X<0";
replacement = stringf("X[%d]", var_width - 1);
replace_sig[0] = var_sig[var_width - 1];
replace = true;
}
- if (const_sig.is_fully_zero() && cmp_type == "$ge")
+ if (const_sig.is_fully_zero() && cmp_type == ID($ge))
{
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
- module->addNot(NEW_ID, var_sig[var_width - 1], cell->getPort("\\Y"));
+ module->addNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID(Y)));
remove = true;
}
}
log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
if (replace)
- module->connect(cell->getPort("\\Y"), replace_sig);
+ module->connect(cell->getPort(ID(Y)), replace_sig);
module->remove(cell);
did_something = true;
goto next_cell;
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{
- SigSpec lut_input = sigmap(lut->getPort("\\A"));
- int lut_width = lut->getParam("\\WIDTH").as_int();
- Const lut_table = lut->getParam("\\LUT");
+ SigSpec lut_input = sigmap(lut->getPort(ID(A)));
+ int lut_width = lut->getParam(ID(WIDTH)).as_int();
+ Const lut_table = lut->getParam(ID(LUT));
int lut_index = 0;
for (int i = 0; i < lut_width; i++)
log("Discovering LUTs.\n");
for (auto cell : module->selected_cells())
{
- if (cell->type == "$lut")
+ if (cell->type == ID($lut))
{
if (cell->has_keep_attr())
continue;
- SigBit lut_output = cell->getPort("\\Y");
- if (lut_output.wire->get_bool_attribute("\\keep"))
+ SigBit lut_output = cell->getPort(ID(Y));
+ if (lut_output.wire->get_bool_attribute(ID(keep)))
continue;
- int lut_width = cell->getParam("\\WIDTH").as_int();
- SigSpec lut_input = cell->getPort("\\A");
+ int lut_width = cell->getParam(ID(WIDTH)).as_int();
+ SigSpec lut_input = cell->getPort(ID(A));
int lut_arity = 0;
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
}
auto lut = worklist.pop();
- SigSpec lut_input = sigmap(lut->getPort("\\A"));
+ SigSpec lut_input = sigmap(lut->getPort(ID(A)));
pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
vector<SigBit> lut_inputs;
log_debug(" Not eliminating cell (connected to dedicated logic).\n");
else
{
- SigSpec lut_output = lut->getPort("\\Y");
+ SigSpec lut_output = lut->getPort(ID(Y));
for (auto &port : index.query_ports(lut_output))
{
if (port.cell != lut && luts.count(port.cell))
}
auto lutA = worklist.pop();
- SigSpec lutA_input = sigmap(lutA->getPort("\\A"));
- SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
- int lutA_width = lutA->getParam("\\WIDTH").as_int();
+ SigSpec lutA_input = sigmap(lutA->getPort(ID(A)));
+ SigSpec lutA_output = sigmap(lutA->getPort(ID(Y))[0]);
+ int lutA_width = lutA->getParam(ID(WIDTH)).as_int();
int lutA_arity = luts_arity[lutA];
pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
- auto lutA_output_ports = index.query_ports(lutA->getPort("\\Y"));
+ auto lutA_output_ports = index.query_ports(lutA->getPort(ID(Y)));
if (lutA_output_ports.size() != 2)
continue;
if (luts.count(port.cell))
{
auto lutB = port.cell;
- SigSpec lutB_input = sigmap(lutB->getPort("\\A"));
- SigSpec lutB_output = sigmap(lutB->getPort("\\Y")[0]);
- int lutB_width = lutB->getParam("\\WIDTH").as_int();
+ SigSpec lutB_input = sigmap(lutB->getPort(ID(A)));
+ SigSpec lutB_output = sigmap(lutB->getPort(ID(Y))[0]);
+ int lutB_width = lutB->getParam(ID(WIDTH)).as_int();
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
- if (index.query_is_output(lutA->getPort("\\Y")))
+ if (index.query_is_output(lutA->getPort(ID(Y))))
{
log_debug(" Not combining LUTs (cascade connection feeds module output).\n");
continue;
log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n");
else if (lutB_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
- else if (lutB->get_bool_attribute("\\lut_keep"))
+ else if (lutB->get_bool_attribute(ID(lut_keep)))
log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
else
combine_mask |= COMBINE_A;
log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n");
else if (lutA_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
- else if (lutA->get_bool_attribute("\\lut_keep"))
+ else if (lutA->get_bool_attribute(ID(lut_keep)))
log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
else
combine_mask |= COMBINE_B;
lutR_unique.insert(bit);
}
- int lutM_width = lutM->getParam("\\WIDTH").as_int();
- SigSpec lutM_input = sigmap(lutM->getPort("\\A"));
+ int lutM_width = lutM->getParam(ID(WIDTH)).as_int();
+ SigSpec lutM_input = sigmap(lutM->getPort(ID(A)));
std::vector<SigBit> lutM_new_inputs;
for (int i = 0; i < lutM_width; i++)
{
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
}
- log_debug(" Cell A truth table: %s.\n", lutA->getParam("\\LUT").as_string().c_str());
- log_debug(" Cell B truth table: %s.\n", lutB->getParam("\\LUT").as_string().c_str());
+ log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID(LUT)).as_string().c_str());
+ log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID(LUT)).as_string().c_str());
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
- lutM->setParam("\\LUT", lutM_new_table);
- lutM->setPort("\\A", lutM_new_inputs);
- lutM->setPort("\\Y", lutB_output);
+ lutM->setParam(ID(LUT), lutM_new_table);
+ lutM->setPort(ID(A), lutM_new_inputs);
+ lutM->setPort(ID(Y), lutB_output);
luts_arity[lutM] = lutM_arity;
luts.erase(lutR);
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{
- SigSpec sig_s = conn.at("\\S");
- SigSpec sig_b = conn.at("\\B");
+ SigSpec sig_s = conn.at(ID(S));
+ SigSpec sig_b = conn.at(ID(B));
int s_width = GetSize(sig_s);
int width = GetSize(sig_b) / s_width;
std::sort(sb_pairs.begin(), sb_pairs.end());
- conn["\\S"] = SigSpec();
- conn["\\B"] = SigSpec();
+ conn[ID(S)] = SigSpec();
+ conn[ID(B)] = SigSpec();
for (auto &it : sb_pairs) {
- conn["\\S"].append(it.first);
- conn["\\B"].append(it.second);
+ conn[ID(S)].append(it.first);
+ conn[ID(B)].append(it.second);
}
}
const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
- if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul",
- "$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) {
+ if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
+ ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
alt_conn = *conn;
- if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
- alt_conn["\\A"] = conn->at("\\B");
- alt_conn["\\B"] = conn->at("\\A");
+ if (assign_map(alt_conn.at(ID(A))) < assign_map(alt_conn.at(ID(B)))) {
+ alt_conn[ID(A)] = conn->at(ID(B));
+ alt_conn[ID(B)] = conn->at(ID(A));
}
conn = &alt_conn;
} else
- if (cell->type.in("$reduce_xor", "$reduce_xnor")) {
+ if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
alt_conn = *conn;
- assign_map.apply(alt_conn.at("\\A"));
- alt_conn.at("\\A").sort();
+ assign_map.apply(alt_conn.at(ID(A)));
+ alt_conn.at(ID(A)).sort();
conn = &alt_conn;
} else
- if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) {
+ if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
alt_conn = *conn;
- assign_map.apply(alt_conn.at("\\A"));
- alt_conn.at("\\A").sort_and_unify();
+ assign_map.apply(alt_conn.at(ID(A)));
+ alt_conn.at(ID(A)).sort_and_unify();
conn = &alt_conn;
} else
- if (cell->type == "$pmux") {
+ if (cell->type == ID($pmux)) {
alt_conn = *conn;
- assign_map.apply(alt_conn.at("\\A"));
- assign_map.apply(alt_conn.at("\\B"));
- assign_map.apply(alt_conn.at("\\S"));
+ assign_map.apply(alt_conn.at(ID(A)));
+ assign_map.apply(alt_conn.at(ID(B)));
+ assign_map.apply(alt_conn.at(ID(S)));
sort_pmux_conn(alt_conn);
conn = &alt_conn;
}
assign_map.apply(it.second);
}
- if (cell1->type == "$and" || cell1->type == "$or" || cell1->type == "$xor" || cell1->type == "$xnor" || cell1->type == "$add" || cell1->type == "$mul" ||
- cell1->type == "$logic_and" || cell1->type == "$logic_or" || cell1->type == "$_AND_" || cell1->type == "$_OR_" || cell1->type == "$_XOR_") {
- if (conn1.at("\\A") < conn1.at("\\B")) {
- RTLIL::SigSpec tmp = conn1["\\A"];
- conn1["\\A"] = conn1["\\B"];
- conn1["\\B"] = tmp;
+ if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
+ cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) {
+ if (conn1.at(ID(A)) < conn1.at(ID(B))) {
+ RTLIL::SigSpec tmp = conn1[ID(A)];
+ conn1[ID(A)] = conn1[ID(B)];
+ conn1[ID(B)] = tmp;
}
- if (conn2.at("\\A") < conn2.at("\\B")) {
- RTLIL::SigSpec tmp = conn2["\\A"];
- conn2["\\A"] = conn2["\\B"];
- conn2["\\B"] = tmp;
+ if (conn2.at(ID(A)) < conn2.at(ID(B))) {
+ RTLIL::SigSpec tmp = conn2[ID(A)];
+ conn2[ID(A)] = conn2[ID(B)];
+ conn2[ID(B)] = tmp;
}
} else
- if (cell1->type == "$reduce_xor" || cell1->type == "$reduce_xnor") {
- conn1["\\A"].sort();
- conn2["\\A"].sort();
+ if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) {
+ conn1[ID(A)].sort();
+ conn2[ID(A)].sort();
} else
- if (cell1->type == "$reduce_and" || cell1->type == "$reduce_or" || cell1->type == "$reduce_bool") {
- conn1["\\A"].sort_and_unify();
- conn2["\\A"].sort_and_unify();
+ if (cell1->type == ID($reduce_and) || cell1->type == ID($reduce_or) || cell1->type == ID($reduce_bool)) {
+ conn1[ID(A)].sort_and_unify();
+ conn2[ID(A)].sort_and_unify();
} else
- if (cell1->type == "$pmux") {
+ if (cell1->type == ID($pmux)) {
sort_pmux_conn(conn1);
sort_pmux_conn(conn2);
}
return true;
}
- if (cell1->type.begins_with("$") && conn1.count("\\Q") != 0) {
- std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
+ if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) {
+ std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
for (size_t i = 0; i < q1.size(); i++)
if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
lt = q1.at(i) < q2.at(i);
ct.setup_stdcells_mem();
if (mode_nomux) {
- ct.cell_types.erase("$mux");
- ct.cell_types.erase("$pmux");
+ ct.cell_types.erase(ID($mux));
+ ct.cell_types.erase(ID($pmux));
}
- ct.cell_types.erase("$tribuf");
- ct.cell_types.erase("$_TBUF_");
- ct.cell_types.erase("$anyseq");
- ct.cell_types.erase("$anyconst");
- ct.cell_types.erase("$allseq");
- ct.cell_types.erase("$allconst");
+ ct.cell_types.erase(ID($tribuf));
+ ct.cell_types.erase(ID($_TBUF_));
+ ct.cell_types.erase(ID($anyseq));
+ ct.cell_types.erase(ID($anyconst));
+ ct.cell_types.erase(ID($allseq));
+ ct.cell_types.erase(ID($allconst));
log("Finding identical cells in module `%s'.\n", module->name.c_str());
assign_map.set(module);
dff_init_map.set(module);
for (auto &it : module->wires_)
- if (it.second->attributes.count("\\init") != 0) {
- Const initval = it.second->attributes.at("\\init");
+ if (it.second->attributes.count(ID(init)) != 0) {
+ Const initval = it.second->attributes.at(ID(init));
for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(it.second, i), initval[i]);
// .const_deactivated
for (auto cell : module->cells())
{
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
- RTLIL::SigSpec sig_a = cell->getPort("\\A");
- RTLIL::SigSpec sig_b = cell->getPort("\\B");
- RTLIL::SigSpec sig_s = cell->getPort("\\S");
- RTLIL::SigSpec sig_y = cell->getPort("\\Y");
+ RTLIL::SigSpec sig_a = cell->getPort(ID(A));
+ RTLIL::SigSpec sig_b = cell->getPort(ID(B));
+ RTLIL::SigSpec sig_s = cell->getPort(ID(S));
+ RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
muxinfo_t muxinfo;
muxinfo.cell = cell;
}
}
for (auto wire : module->wires()) {
- if (wire->port_output || wire->get_bool_attribute("\\keep"))
+ if (wire->port_output || wire->get_bool_attribute(ID(keep)))
for (int idx : sig2bits(RTLIL::SigSpec(wire)))
bit2info[idx].seen_non_mux = true;
}
continue;
}
- RTLIL::SigSpec sig_a = mi.cell->getPort("\\A");
- RTLIL::SigSpec sig_b = mi.cell->getPort("\\B");
- RTLIL::SigSpec sig_s = mi.cell->getPort("\\S");
- RTLIL::SigSpec sig_y = mi.cell->getPort("\\Y");
+ RTLIL::SigSpec sig_a = mi.cell->getPort(ID(A));
+ RTLIL::SigSpec sig_b = mi.cell->getPort(ID(B));
+ RTLIL::SigSpec sig_s = mi.cell->getPort(ID(S));
+ RTLIL::SigSpec sig_y = mi.cell->getPort(ID(Y));
RTLIL::SigSpec sig_ports = sig_b;
sig_ports.append(sig_a);
}
}
- mi.cell->setPort("\\A", new_sig_a);
- mi.cell->setPort("\\B", new_sig_b);
- mi.cell->setPort("\\S", new_sig_s);
+ mi.cell->setPort(ID(A), new_sig_a);
+ mi.cell->setPort(ID(B), new_sig_b);
+ mi.cell->setPort(ID(S), new_sig_s);
if (GetSize(new_sig_s) == 1) {
- mi.cell->type = "$mux";
- mi.cell->parameters.erase("\\S_WIDTH");
+ mi.cell->type = ID($mux);
+ mi.cell->parameters.erase(ID(S_WIDTH));
} else {
- mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(GetSize(new_sig_s));
+ mi.cell->parameters[ID(S_WIDTH)] = RTLIL::Const(GetSize(new_sig_s));
}
}
}
int width = 0;
idict<int> ctrl_bits;
- if (portname == "\\B")
- width = GetSize(muxinfo.cell->getPort("\\A"));
- for (int bit : sig2bits(muxinfo.cell->getPort("\\S"), false))
+ if (portname == ID(B))
+ width = GetSize(muxinfo.cell->getPort(ID(A)));
+ for (int bit : sig2bits(muxinfo.cell->getPort(ID(S)), false))
ctrl_bits(bit);
int port_idx = 0, port_off = 0;
// set input ports to constants if we find known active or inactive signals
if (do_replace_known) {
- replace_known(knowledge, muxinfo, "\\A");
- replace_known(knowledge, muxinfo, "\\B");
+ replace_known(knowledge, muxinfo, ID(A));
+ replace_known(knowledge, muxinfo, ID(B));
}
// if there is a constant activated port we just use it
return;
cells.erase(cell);
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
pool<RTLIL::SigBit> new_sig_a_bits;
for (auto &bit : sig_a.to_sigbit_set())
{
if (bit == RTLIL::State::S0) {
- if (cell->type == "$reduce_and") {
+ if (cell->type == ID($reduce_and)) {
new_sig_a_bits.clear();
new_sig_a_bits.insert(RTLIL::State::S0);
break;
continue;
}
if (bit == RTLIL::State::S1) {
- if (cell->type == "$reduce_or") {
+ if (cell->type == ID($reduce_or)) {
new_sig_a_bits.clear();
new_sig_a_bits.insert(RTLIL::State::S1);
break;
for (auto child_cell : drivers.find(bit)) {
if (child_cell->type == cell->type) {
opt_reduce(cells, drivers, child_cell);
- if (child_cell->getPort("\\Y")[0] == bit) {
- pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort("\\A")).to_sigbit_pool();
+ if (child_cell->getPort(ID(Y))[0] == bit) {
+ pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(ID(A))).to_sigbit_pool();
new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
} else
new_sig_a_bits.insert(RTLIL::State::S0);
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
- if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
+ if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID(A)).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
total_count++;
}
- cell->setPort("\\A", new_sig_a);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
+ cell->setPort(ID(A), new_sig_a);
+ cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size());
return;
}
void opt_mux(RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B)));
+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S)));
RTLIL::SigSpec new_sig_b, new_sig_s;
pool<RTLIL::SigSpec> handled_sig;
if (this_s.size() > 1)
{
- RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
- reduce_or_cell->setPort("\\A", this_s);
- reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
- reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
+ reduce_or_cell->setPort(ID(A), this_s);
+ reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0);
+ reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size());
+ reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
- reduce_or_cell->setPort("\\Y", this_s);
+ reduce_or_cell->setPort(ID(Y), this_s);
}
new_sig_b.append(this_b);
if (new_sig_s.size() == 0)
{
- module->connect(RTLIL::SigSig(cell->getPort("\\Y"), cell->getPort("\\A")));
- assign_map.add(cell->getPort("\\Y"), cell->getPort("\\A"));
+ module->connect(RTLIL::SigSig(cell->getPort(ID(Y)), cell->getPort(ID(A))));
+ assign_map.add(cell->getPort(ID(Y)), cell->getPort(ID(A)));
module->remove(cell);
}
else
{
- cell->setPort("\\B", new_sig_b);
- cell->setPort("\\S", new_sig_s);
+ cell->setPort(ID(B), new_sig_b);
+ cell->setPort(ID(S), new_sig_s);
if (new_sig_s.size() > 1) {
- cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
+ cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size());
} else {
- cell->type = "$mux";
- cell->parameters.erase("\\S_WIDTH");
+ cell->type = ID($mux);
+ cell->parameters.erase(ID(S_WIDTH));
}
}
}
void opt_mux_bits(RTLIL::Cell *cell)
{
- std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort("\\A")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort("\\B")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort("\\Y")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort(ID(A))).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort(ID(B))).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort(ID(Y))).to_sigbit_vector();
std::vector<RTLIL::SigBit> new_sig_y;
RTLIL::SigSig old_sig_conn;
if (new_sig_y.size() != sig_y.size())
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
- log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
- log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
+ log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID(A))),
+ log_signal(cell->getPort(ID(B))), log_signal(cell->getPort(ID(Y))));
- cell->setPort("\\A", RTLIL::SigSpec());
+ cell->setPort(ID(A), RTLIL::SigSpec());
for (auto &in_tuple : consolidated_in_tuples) {
- RTLIL::SigSpec new_a = cell->getPort("\\A");
+ RTLIL::SigSpec new_a = cell->getPort(ID(A));
new_a.append(in_tuple.at(0));
- cell->setPort("\\A", new_a);
+ cell->setPort(ID(A), new_a);
}
- cell->setPort("\\B", RTLIL::SigSpec());
- for (int i = 1; i <= cell->getPort("\\S").size(); i++)
+ cell->setPort(ID(B), RTLIL::SigSpec());
+ for (int i = 1; i <= cell->getPort(ID(S)).size(); i++)
for (auto &in_tuple : consolidated_in_tuples) {
- RTLIL::SigSpec new_b = cell->getPort("\\B");
+ RTLIL::SigSpec new_b = cell->getPort(ID(B));
new_b.append(in_tuple.at(i));
- cell->setPort("\\B", new_b);
+ cell->setPort(ID(B), new_b);
}
- cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
- cell->setPort("\\Y", new_sig_y);
+ cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size());
+ cell->setPort(ID(Y), new_sig_y);
- log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
- log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
+ log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID(A))),
+ log_signal(cell->getPort(ID(B))), log_signal(cell->getPort(ID(Y))));
log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
module->connect(old_sig_conn);
SigPool mem_wren_sigs;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$mem")
- mem_wren_sigs.add(assign_map(cell->getPort("\\WR_EN")));
- if (cell->type == "$memwr")
- mem_wren_sigs.add(assign_map(cell->getPort("\\EN")));
+ if (cell->type == ID($mem))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN))));
+ if (cell->type == ID($memwr))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(EN))));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Q"))))
- mem_wren_sigs.add(assign_map(cell->getPort("\\D")));
+ if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q)))))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(D))));
}
bool keep_expanding_mem_wren_sigs = true;
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) {
- if (!mem_wren_sigs.check_all(assign_map(cell->getPort("\\A"))) ||
- !mem_wren_sigs.check_all(assign_map(cell->getPort("\\B"))))
+ if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Y))))) {
+ if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID(A)))) ||
+ !mem_wren_sigs.check_all(assign_map(cell->getPort(ID(B)))))
keep_expanding_mem_wren_sigs = true;
- mem_wren_sigs.add(assign_map(cell->getPort("\\A")));
- mem_wren_sigs.add(assign_map(cell->getPort("\\B")));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(A))));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(B))));
}
}
}
// merge trees of reduce_* cells to one single cell and unify input vectors
// (only handle reduce_and and reduce_or for various reasons)
- const char *type_list[] = { "$reduce_or", "$reduce_and" };
+ const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
for (auto type : type_list)
{
SigSet<RTLIL::Cell*> drivers;
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
- drivers.insert(assign_map(cell->getPort("\\Y")), cell);
+ drivers.insert(assign_map(cell->getPort(ID(Y))), cell);
cells.insert(cell);
}
std::vector<RTLIL::Cell*> cells;
for (auto &it : module->cells_)
- if ((it.second->type == "$mux" || it.second->type == "$pmux") && design->selected(module, it.second))
+ if ((it.second->type == ID($mux) || it.second->type == ID($pmux)) && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : cells)
{
// this optimization is to aggressive for most coarse-grain applications.
// but we always want it for multiplexers driving write enable ports.
- if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y"))))
+ if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Y)))))
opt_mux_bits(cell);
opt_mux(cell);
for (auto bit : assign_map(sig))
if (init_attributes.count(bit))
for (auto wbit : init_attributes.at(bit))
- wbit.wire->attributes.at("\\init")[wbit.offset] = State::Sx;
+ wbit.wire->attributes.at(ID(init))[wbit.offset] = State::Sx;
}
bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
SigSpec sig_set, sig_clr;
State pol_set, pol_clr;
- if (cell->hasPort("\\S"))
- sig_set = cell->getPort("\\S");
+ if (cell->hasPort(ID(S)))
+ sig_set = cell->getPort(ID(S));
- if (cell->hasPort("\\R"))
- sig_clr = cell->getPort("\\R");
+ if (cell->hasPort(ID(R)))
+ sig_clr = cell->getPort(ID(R));
- if (cell->hasPort("\\SET"))
- sig_set = cell->getPort("\\SET");
+ if (cell->hasPort(ID(SET)))
+ sig_set = cell->getPort(ID(SET));
- if (cell->hasPort("\\CLR"))
- sig_clr = cell->getPort("\\CLR");
+ if (cell->hasPort(ID(CLR)))
+ sig_clr = cell->getPort(ID(CLR));
log_assert(GetSize(sig_set) == GetSize(sig_clr));
pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
} else
- if (cell->type.in("$dffsr", "$dlatchsr")) {
- pol_set = cell->parameters["\\SET_POLARITY"].as_bool() ? State::S1 : State::S0;
- pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool() ? State::S1 : State::S0;
+ if (cell->type.in(ID($dffsr), ID($dlatchsr))) {
+ pol_set = cell->parameters[ID(SET_POLARITY)].as_bool() ? State::S1 : State::S0;
+ pol_clr = cell->parameters[ID(CLR_POLARITY)].as_bool() ? State::S1 : State::S0;
} else
log_abort();
State npol_set = pol_set == State::S0 ? State::S1 : State::S0;
State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0;
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_d = cell->getPort(ID(D));
+ SigSpec sig_q = cell->getPort(ID(Q));
bool did_something = false;
bool proper_sr = false;
return true;
}
- if (cell->type.in("$dffsr", "$dlatchsr"))
+ if (cell->type.in(ID($dffsr), ID($dlatchsr)))
{
- cell->setParam("\\WIDTH", GetSize(sig_d));
- cell->setPort("\\SET", sig_set);
- cell->setPort("\\CLR", sig_clr);
- cell->setPort("\\D", sig_d);
- cell->setPort("\\Q", sig_q);
+ cell->setParam(ID(WIDTH), GetSize(sig_d));
+ cell->setPort(ID(SET), sig_set);
+ cell->setPort(ID(CLR), sig_clr);
+ cell->setPort(ID(D), sig_d);
+ cell->setPort(ID(Q), sig_q);
}
else
{
- cell->setPort("\\S", sig_set);
- cell->setPort("\\R", sig_clr);
- cell->setPort("\\D", sig_d);
- cell->setPort("\\Q", sig_q);
+ cell->setPort(ID(S), sig_set);
+ cell->setPort(ID(R), sig_clr);
+ cell->setPort(ID(D), sig_d);
+ cell->setPort(ID(Q), sig_q);
}
if (proper_sr)
if (used_pol_set && used_pol_clr && pol_set != pol_clr)
return did_something;
- if (cell->type == "$dlatchsr")
+ if (cell->type == ID($dlatchsr))
return did_something;
State unified_pol = used_pol_set ? pol_set : pol_clr;
- if (cell->type == "$dffsr")
+ if (cell->type == ID($dffsr))
{
if (hasreset)
{
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod));
- cell->type = "$adff";
- cell->setParam("\\ARST_POLARITY", unified_pol);
- cell->setParam("\\ARST_VALUE", reset_val);
- cell->setPort("\\ARST", sig_reset);
+ cell->type = ID($adff);
+ cell->setParam(ID(ARST_POLARITY), unified_pol);
+ cell->setParam(ID(ARST_VALUE), reset_val);
+ cell->setPort(ID(ARST), sig_reset);
- cell->unsetParam("\\SET_POLARITY");
- cell->unsetParam("\\CLR_POLARITY");
- cell->unsetPort("\\SET");
- cell->unsetPort("\\CLR");
+ cell->unsetParam(ID(SET_POLARITY));
+ cell->unsetParam(ID(CLR_POLARITY));
+ cell->unsetPort(ID(SET));
+ cell->unsetPort(ID(CLR));
}
else
{
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod));
- cell->type = "$dff";
- cell->unsetParam("\\SET_POLARITY");
- cell->unsetParam("\\CLR_POLARITY");
- cell->unsetPort("\\SET");
- cell->unsetPort("\\CLR");
+ cell->type = ID($dff);
+ cell->unsetParam(ID(SET_POLARITY));
+ cell->unsetParam(ID(CLR_POLARITY));
+ cell->unsetPort(ID(SET));
+ cell->unsetPort(ID(CLR));
}
return true;
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod));
cell->type = new_type;
- cell->unsetPort("\\S");
- cell->unsetPort("\\R");
+ cell->unsetPort(ID(S));
+ cell->unsetPort(ID(R));
return true;
}
SigSpec sig_e;
State on_state, off_state;
- if (dlatch->type == "$dlatch") {
- sig_e = assign_map(dlatch->getPort("\\EN"));
- on_state = dlatch->getParam("\\EN_POLARITY").as_bool() ? State::S1 : State::S0;
- off_state = dlatch->getParam("\\EN_POLARITY").as_bool() ? State::S0 : State::S1;
+ if (dlatch->type == ID($dlatch)) {
+ sig_e = assign_map(dlatch->getPort(ID(EN)));
+ on_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S1 : State::S0;
+ off_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S0 : State::S1;
} else
- if (dlatch->type == "$_DLATCH_P_") {
- sig_e = assign_map(dlatch->getPort("\\E"));
+ if (dlatch->type == ID($_DLATCH_P_)) {
+ sig_e = assign_map(dlatch->getPort(ID(E)));
on_state = State::S1;
off_state = State::S0;
} else
- if (dlatch->type == "$_DLATCH_N_") {
- sig_e = assign_map(dlatch->getPort("\\E"));
+ if (dlatch->type == ID($_DLATCH_N_)) {
+ sig_e = assign_map(dlatch->getPort(ID(E)));
on_state = State::S0;
off_state = State::S1;
} else
if (sig_e == off_state)
{
RTLIL::Const val_init;
- for (auto bit : dff_init_map(dlatch->getPort("\\Q")))
+ for (auto bit : dff_init_map(dlatch->getPort(ID(Q))))
val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx);
- mod->connect(dlatch->getPort("\\Q"), val_init);
+ mod->connect(dlatch->getPort(ID(Q)), val_init);
goto delete_dlatch;
}
if (sig_e == on_state)
{
- mod->connect(dlatch->getPort("\\Q"), dlatch->getPort("\\D"));
+ mod->connect(dlatch->getPort(ID(Q)), dlatch->getPort(ID(D)));
goto delete_dlatch;
}
delete_dlatch:
log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod));
- remove_init_attr(dlatch->getPort("\\Q"));
+ remove_init_attr(dlatch->getPort(ID(Q)));
mod->remove(dlatch);
return true;
}
RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r, sig_e;
RTLIL::Const val_cp, val_rp, val_rv, val_ep;
- if (dff->type == "$_FF_") {
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
+ if (dff->type == ID($_FF_)) {
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
}
- else if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
- sig_c = dff->getPort("\\C");
- val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
+ else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) {
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
+ sig_c = dff->getPort(ID(C));
+ val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1);
}
else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[6] == 'N' || dff->type[6] == 'P') &&
(dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == '0' || dff->type[8] == '1')) {
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
- sig_c = dff->getPort("\\C");
- sig_r = dff->getPort("\\R");
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
+ sig_c = dff->getPort(ID(C));
+ sig_r = dff->getPort(ID(R));
val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
val_rv = RTLIL::Const(dff->type[8] == '1', 1);
else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == 'N' || dff->type[8] == 'P')) {
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
- sig_c = dff->getPort("\\C");
- sig_e = dff->getPort("\\E");
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
+ sig_c = dff->getPort(ID(C));
+ sig_e = dff->getPort(ID(E));
val_cp = RTLIL::Const(dff->type[7] == 'P', 1);
val_ep = RTLIL::Const(dff->type[8] == 'P', 1);
}
- else if (dff->type == "$ff") {
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
+ else if (dff->type == ID($ff)) {
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
}
- else if (dff->type == "$dff") {
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
- sig_c = dff->getPort("\\CLK");
- val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
+ else if (dff->type == ID($dff)) {
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
+ sig_c = dff->getPort(ID(CLK));
+ val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
}
- else if (dff->type == "$dffe") {
- sig_e = dff->getPort("\\EN");
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
- sig_c = dff->getPort("\\CLK");
- val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
- val_ep = RTLIL::Const(dff->parameters["\\EN_POLARITY"].as_bool(), 1);
+ else if (dff->type == ID($dffe)) {
+ sig_e = dff->getPort(ID(EN));
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
+ sig_c = dff->getPort(ID(CLK));
+ val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
+ val_ep = RTLIL::Const(dff->parameters[ID(EN_POLARITY)].as_bool(), 1);
}
- else if (dff->type == "$adff") {
- sig_d = dff->getPort("\\D");
- sig_q = dff->getPort("\\Q");
- sig_c = dff->getPort("\\CLK");
- sig_r = dff->getPort("\\ARST");
- val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
- val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1);
- val_rv = dff->parameters["\\ARST_VALUE"];
+ else if (dff->type == ID($adff)) {
+ sig_d = dff->getPort(ID(D));
+ sig_q = dff->getPort(ID(Q));
+ sig_c = dff->getPort(ID(CLK));
+ sig_r = dff->getPort(ID(ARST));
+ val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
+ val_rp = RTLIL::Const(dff->parameters[ID(ARST_POLARITY)].as_bool(), 1);
+ val_rv = dff->parameters[ID(ARST_VALUE)];
}
else
log_abort();
val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
}
- if (dff->type.in("$ff", "$dff") && mux_drivers.has(sig_d)) {
+ if (dff->type.in(ID($ff), ID($dff)) && mux_drivers.has(sig_d)) {
std::set<RTLIL::Cell*> muxes;
mux_drivers.find(sig_d, muxes);
for (auto mux : muxes) {
- RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B"));
+ RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID(A)));
+ RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID(B)));
if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) {
mod->connect(sig_q, sig_b);
goto delete_dff;
log("Removing unused reset from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
- if (dff->type == "$adff") {
- dff->type = "$dff";
- dff->unsetPort("\\ARST");
- dff->unsetParam("\\ARST_POLARITY");
- dff->unsetParam("\\ARST_VALUE");
+ if (dff->type == ID($adff)) {
+ dff->type = ID($dff);
+ dff->unsetPort(ID(ARST));
+ dff->unsetParam(ID(ARST_POLARITY));
+ dff->unsetParam(ID(ARST_VALUE));
return true;
}
log_assert(dff->type.begins_with("$_DFF_"));
dff->type = stringf("$_DFF_%c_", + dff->type[6]);
- dff->unsetPort("\\R");
+ dff->unsetPort(ID(R));
}
// If enable signal is present, and is fully constant
log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
- if (dff->type == "$dffe") {
- dff->type = "$dff";
- dff->unsetPort("\\EN");
- dff->unsetParam("\\EN_POLARITY");
+ if (dff->type == ID($dffe)) {
+ dff->type = ID($dff);
+ dff->unsetPort(ID(EN));
+ dff->unsetParam(ID(EN_POLARITY));
return true;
}
log_assert(dff->type.begins_with("$_DFFE_"));
dff->type = stringf("$_DFF_%c_", + dff->type[7]);
- dff->unsetPort("\\E");
+ dff->unsetPort(ID(E));
}
if (sat && has_init && (!sig_r.size() || val_init == val_rv))
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0,
position, log_id(dff), log_id(dff->type), log_id(mod));
- SigSpec tmp = dff->getPort("\\D");
+ SigSpec tmp = dff->getPort(ID(D));
tmp[position] = sigbit_init_val;
- dff->setPort("\\D", tmp);
+ dff->setPort(ID(D), tmp);
removed_sigbits = true;
}
delete_dff:
log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
- remove_init_attr(dff->getPort("\\Q"));
+ remove_init_attr(dff->getPort(ID(Q)));
mod->remove(dff);
for (auto &entry : bit2driver)
for (auto wire : module->wires())
{
- if (wire->attributes.count("\\init") != 0) {
- Const initval = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID(init)) != 0) {
+ Const initval = wire->attributes.at(ID(init));
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(wire, i), initval[i]);
}
}
- if (cell->type.in("$mux", "$pmux")) {
- if (cell->getPort("\\A").size() == cell->getPort("\\B").size())
- mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell);
+ if (cell->type.in(ID($mux), ID($pmux))) {
+ if (cell->getPort(ID(A)).size() == cell->getPort(ID(B)).size())
+ mux_drivers.insert(assign_map(cell->getPort(ID(Y))), cell);
continue;
}
if (!design->selected(module, cell))
continue;
- if (cell->type.in("$_DFFSR_NNN_", "$_DFFSR_NNP_", "$_DFFSR_NPN_", "$_DFFSR_NPP_",
- "$_DFFSR_PNN_", "$_DFFSR_PNP_", "$_DFFSR_PPN_", "$_DFFSR_PPP_", "$dffsr",
- "$_DLATCHSR_NNN_", "$_DLATCHSR_NNP_", "$_DLATCHSR_NPN_", "$_DLATCHSR_NPP_",
- "$_DLATCHSR_PNN_", "$_DLATCHSR_PNP_", "$_DLATCHSR_PPN_", "$_DLATCHSR_PPP_", "$dlatchsr"))
+ if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_), ID($dffsr),
+ ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
+ ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_), ID($dlatchsr)))
dffsr_list.push_back(cell->name);
- if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_",
- "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
- "$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_",
- "$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_",
- "$ff", "$dff", "$dffe", "$adff"))
+ if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_),
+ ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
+ ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
+ ID($ff), ID($dff), ID($dffe), ID($adff)))
dff_list.push_back(cell->name);
- if (cell->type.in("$dlatch", "$_DLATCH_P_", "$_DLATCH_N_"))
+ if (cell->type.in(ID($dlatch), ID($_DLATCH_P_), ID($_DLATCH_N_)))
dlatch_list.push_back(cell->name);
}
for (auto wire : module->wires())
{
- auto it = wire->attributes.find("\\init");
+ auto it = wire->attributes.find(ID(init));
if (it == wire->attributes.end())
continue;
vector<SigSpec> inputs;
SigSpec output;
- if (cell->type.in("$adff", "$dff", "$dffe", "$dlatch", "$ff"))
+ if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
{
- output = cell->getPort("\\Q");
- if (cell->type == "$adff")
- inputs.push_back(cell->getParam("\\ARST_VALUE"));
- inputs.push_back(cell->getPort("\\D"));
+ output = cell->getPort(ID(Q));
+ if (cell->type == ID($adff))
+ inputs.push_back(cell->getParam(ID(ARST_VALUE)));
+ inputs.push_back(cell->getPort(ID(D)));
}
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
- output = cell->getPort("\\Y");
- inputs.push_back(cell->getPort("\\A"));
- SigSpec B = cell->getPort("\\B");
+ output = cell->getPort(ID(Y));
+ inputs.push_back(cell->getPort(ID(A)));
+ SigSpec B = cell->getPort(ID(B));
for (int i = 0; i < GetSize(B); i += GetSize(output))
inputs.push_back(B.extract(i, GetSize(output)));
}
for (auto cell : module->cells())
{
- if (cell->type == "$eq")
+ if (cell->type == ID($eq))
{
dict<SigBit, State> bits;
- SigSpec A = sigmap(cell->getPort("\\A"));
- SigSpec B = sigmap(cell->getPort("\\B"));
+ SigSpec A = sigmap(cell->getPort(ID(A)));
+ SigSpec B = sigmap(cell->getPort(ID(B)));
- int a_width = cell->getParam("\\A_WIDTH").as_int();
- int b_width = cell->getParam("\\B_WIDTH").as_int();
+ int a_width = cell->getParam(ID(A_WIDTH)).as_int();
+ int b_width = cell->getParam(ID(B_WIDTH)).as_int();
if (a_width < b_width) {
- bool a_signed = cell->getParam("\\A_SIGNED").as_int();
+ bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
A.extend_u0(b_width, a_signed);
}
if (b_width < a_width) {
- bool b_signed = cell->getParam("\\B_SIGNED").as_int();
+ bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
B.extend_u0(a_width, b_signed);
}
entry.second.bits.push_back(it.second);
}
- eqdb[sigmap(cell->getPort("\\Y")[0])] = entry;
+ eqdb[sigmap(cell->getPort(ID(Y))[0])] = entry;
goto next_cell;
}
- if (cell->type == "$logic_not")
+ if (cell->type == ID($logic_not))
{
dict<SigBit, State> bits;
- SigSpec A = sigmap(cell->getPort("\\A"));
+ SigSpec A = sigmap(cell->getPort(ID(A)));
for (int i = 0; i < GetSize(A); i++)
bits[A[i]] = State::S0;
entry.second.bits.push_back(it.second);
}
- eqdb[sigmap(cell->getPort("\\Y")[0])] = entry;
+ eqdb[sigmap(cell->getPort(ID(Y))[0])] = entry;
goto next_cell;
}
next_cell:;
for (auto cell : module->selected_cells())
{
- if (cell->type != "$pmux")
+ if (cell->type != ID($pmux))
continue;
string src = cell->get_src_attribute();
- int width = cell->getParam("\\WIDTH").as_int();
+ int width = cell->getParam(ID(WIDTH)).as_int();
int width_bits = ceil_log2(width);
int extwidth = width;
dict<SigSpec, pool<int>> seldb;
- SigSpec A = cell->getPort("\\A");
- SigSpec B = cell->getPort("\\B");
- SigSpec S = sigmap(cell->getPort("\\S"));
+ SigSpec A = cell->getPort(ID(A));
+ SigSpec B = cell->getPort(ID(B));
+ SigSpec S = sigmap(cell->getPort(ID(S)));
for (int i = 0; i < GetSize(S); i++)
{
if (!eqdb.count(S[i]))
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
- SigSpec updated_S = cell->getPort("\\S");
- SigSpec updated_B = cell->getPort("\\B");
+ SigSpec updated_S = cell->getPort(ID(S));
+ SigSpec updated_B = cell->getPort(ID(B));
while (!seldb.empty())
{
}
// update $pmux cell
- cell->setPort("\\S", updated_S);
- cell->setPort("\\B", updated_B);
- cell->setParam("\\S_WIDTH", GetSize(updated_S));
+ cell->setPort(ID(S), updated_S);
+ cell->setPort(ID(B), updated_B);
+ cell->setParam(ID(S_WIDTH), GetSize(updated_S));
}
}
}
for (auto cell : module->selected_cells())
{
- if (cell->type != "$eq")
+ if (cell->type != ID($eq))
continue;
- SigSpec A = sigmap(cell->getPort("\\A"));
- SigSpec B = sigmap(cell->getPort("\\B"));
+ SigSpec A = sigmap(cell->getPort(ID(A)));
+ SigSpec B = sigmap(cell->getPort(ID(B)));
- int a_width = cell->getParam("\\A_WIDTH").as_int();
- int b_width = cell->getParam("\\B_WIDTH").as_int();
+ int a_width = cell->getParam(ID(A_WIDTH)).as_int();
+ int b_width = cell->getParam(ID(B_WIDTH)).as_int();
if (a_width < b_width) {
- bool a_signed = cell->getParam("\\A_SIGNED").as_int();
+ bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
A.extend_u0(b_width, a_signed);
}
if (b_width < a_width) {
- bool b_signed = cell->getParam("\\B_SIGNED").as_int();
+ bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
B.extend_u0(a_width, b_signed);
}
continue;
}
- SigSpec Y = cell->getPort("\\Y");
+ SigSpec Y = cell->getPort(ID(Y));
if (not_onehot)
{
queue_bits.clear();
for (auto &pbit : portbits) {
- if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") {
- pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_pool();
+ if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) {
+ pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID(S))).to_sigbit_pool();
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell);
static int bits_macc(RTLIL::Cell *c)
{
Macc m(c);
- int width = GetSize(c->getPort("\\Y"));
+ int width = GetSize(c->getPort(ID(Y)));
return bits_macc(m, width);
}
{
Macc m1(c1), m2(c2), supermacc;
- int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y"));
+ int w1 = GetSize(c1->getPort(ID(Y))), w2 = GetSize(c2->getPort(ID(Y)));
int width = max(w1, w2);
m1.optimize(w1);
{
RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width);
- supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort("\\Y")));
- supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort("\\Y")));
+ supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID(Y))));
+ supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID(Y))));
- supercell->setParam("\\Y_WIDTH", width);
- supercell->setPort("\\Y", sig_y);
+ supercell->setParam(ID(Y_WIDTH), width);
+ supercell->setPort(ID(Y), sig_y);
supermacc.optimize(width);
supermacc.to_cell(supercell);
continue;
}
- if (cell->type == "$memrd") {
- if (cell->parameters.at("\\CLK_ENABLE").as_bool())
+ if (cell->type == ID($memrd)) {
+ if (cell->parameters.at(ID(CLK_ENABLE)).as_bool())
continue;
- if (config.opt_aggressive || !modwalker.sigmap(cell->getPort("\\ADDR")).is_fully_const())
+ if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID(ADDR))).is_fully_const())
shareable_cells.insert(cell);
continue;
}
- if (cell->type.in("$mul", "$div", "$mod")) {
- if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4)
+ if (cell->type.in(ID($mul), ID($div), ID($mod))) {
+ if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 4)
shareable_cells.insert(cell);
continue;
}
- if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) {
- if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8)
+ if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
+ if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 8)
shareable_cells.insert(cell);
continue;
}
if (c1->type != c2->type)
return false;
- if (c1->type == "$memrd")
+ if (c1->type == ID($memrd))
{
- if (c1->parameters.at("\\MEMID").decode_string() != c2->parameters.at("\\MEMID").decode_string())
+ if (c1->parameters.at(ID(MEMID)).decode_string() != c2->parameters.at(ID(MEMID)).decode_string())
return false;
return true;
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
- int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
+ int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
+ int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
- int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
- int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
+ int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
+ int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
return true;
}
- if (config.generic_bin_ops.count(c1->type) || c1->type == "$alu")
+ if (config.generic_bin_ops.count(c1->type) || c1->type == ID($alu))
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
- int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
- int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
+ int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
+ int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
+ int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
- int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
- int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
- int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
+ int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
+ int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
+ int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false;
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
- int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
- int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
+ int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
+ int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
+ int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
- int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
- int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
- int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
+ int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
+ int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
+ int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
int min1_width = min(a1_width, b1_width);
int max1_width = max(a1_width, b1_width);
return true;
}
- if (c1->type == "$macc")
+ if (c1->type == ID($macc))
{
if (!config.opt_aggressive)
if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false;
if (config.generic_uni_ops.count(c1->type))
{
- if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
+ if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
- if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
- RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
+ if (unsigned_cell->getPort(ID(A)).to_sigbit_vector().back() != RTLIL::State::S0) {
+ unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
+ RTLIL::SigSpec new_a = unsigned_cell->getPort(ID(A));
new_a.append_bit(RTLIL::State::S0);
- unsigned_cell->setPort("\\A", new_a);
+ unsigned_cell->setPort(ID(A), new_a);
}
- unsigned_cell->parameters.at("\\A_SIGNED") = true;
+ unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
unsigned_cell->check();
}
- bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
- log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
+ bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
+ log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
- RTLIL::SigSpec a1 = c1->getPort("\\A");
- RTLIL::SigSpec y1 = c1->getPort("\\Y");
+ RTLIL::SigSpec a1 = c1->getPort(ID(A));
+ RTLIL::SigSpec y1 = c1->getPort(ID(Y));
- RTLIL::SigSpec a2 = c2->getPort("\\A");
- RTLIL::SigSpec y2 = c2->getPort("\\Y");
+ RTLIL::SigSpec a2 = c2->getPort(ID(A));
+ RTLIL::SigSpec y2 = c2->getPort(ID(Y));
int a_width = max(a1.size(), a2.size());
int y_width = max(y1.size(), y2.size());
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
- supercell->parameters["\\A_SIGNED"] = a_signed;
- supercell->parameters["\\A_WIDTH"] = a_width;
- supercell->parameters["\\Y_WIDTH"] = y_width;
- supercell->setPort("\\A", a);
- supercell->setPort("\\Y", y);
+ supercell->parameters[ID(A_SIGNED)] = a_signed;
+ supercell->parameters[ID(A_WIDTH)] = a_width;
+ supercell->parameters[ID(Y_WIDTH)] = y_width;
+ supercell->setPort(ID(A), a);
+ supercell->setPort(ID(Y), y);
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
return supercell;
}
- if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == "$alu")
+ if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == ID($alu))
{
bool modified_src_cells = false;
if (config.generic_cbin_ops.count(c1->type))
{
- int score_unflipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) +
- max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int());
+ int score_unflipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()) +
+ max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int());
- int score_flipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) +
- max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int());
+ int score_flipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()) +
+ max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int());
if (score_flipped < score_unflipped)
{
- RTLIL::SigSpec tmp = c2->getPort("\\A");
- c2->setPort("\\A", c2->getPort("\\B"));
- c2->setPort("\\B", tmp);
+ RTLIL::SigSpec tmp = c2->getPort(ID(A));
+ c2->setPort(ID(A), c2->getPort(ID(B)));
+ c2->setPort(ID(B), tmp);
- std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
- std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
+ std::swap(c2->parameters.at(ID(A_WIDTH)), c2->parameters.at(ID(B_WIDTH)));
+ std::swap(c2->parameters.at(ID(A_SIGNED)), c2->parameters.at(ID(B_SIGNED)));
modified_src_cells = true;
}
}
- if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
+ if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
- if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
- RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
+ if (unsigned_cell->getPort(ID(A)).to_sigbit_vector().back() != RTLIL::State::S0) {
+ unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
+ RTLIL::SigSpec new_a = unsigned_cell->getPort(ID(A));
new_a.append_bit(RTLIL::State::S0);
- unsigned_cell->setPort("\\A", new_a);
+ unsigned_cell->setPort(ID(A), new_a);
}
- unsigned_cell->parameters.at("\\A_SIGNED") = true;
+ unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
modified_src_cells = true;
}
- if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
+ if (c1->parameters.at(ID(B_SIGNED)).as_bool() != c2->parameters.at(ID(B_SIGNED)).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
- if (unsigned_cell->getPort("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
- RTLIL::SigSpec new_b = unsigned_cell->getPort("\\B");
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(B_SIGNED)).as_bool() ? c2 : c1;
+ if (unsigned_cell->getPort(ID(B)).to_sigbit_vector().back() != RTLIL::State::S0) {
+ unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1;
+ RTLIL::SigSpec new_b = unsigned_cell->getPort(ID(B));
new_b.append_bit(RTLIL::State::S0);
- unsigned_cell->setPort("\\B", new_b);
+ unsigned_cell->setPort(ID(B), new_b);
}
- unsigned_cell->parameters.at("\\B_SIGNED") = true;
+ unsigned_cell->parameters.at(ID(B_SIGNED)) = true;
modified_src_cells = true;
}
c2->check();
}
- bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
- bool b_signed = c1->parameters.at("\\B_SIGNED").as_bool();
+ bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
+ bool b_signed = c1->parameters.at(ID(B_SIGNED)).as_bool();
- log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
- log_assert(b_signed == c2->parameters.at("\\B_SIGNED").as_bool());
+ log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
+ log_assert(b_signed == c2->parameters.at(ID(B_SIGNED)).as_bool());
- if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
+ if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
b_signed = false;
- RTLIL::SigSpec a1 = c1->getPort("\\A");
- RTLIL::SigSpec b1 = c1->getPort("\\B");
- RTLIL::SigSpec y1 = c1->getPort("\\Y");
+ RTLIL::SigSpec a1 = c1->getPort(ID(A));
+ RTLIL::SigSpec b1 = c1->getPort(ID(B));
+ RTLIL::SigSpec y1 = c1->getPort(ID(Y));
- RTLIL::SigSpec a2 = c2->getPort("\\A");
- RTLIL::SigSpec b2 = c2->getPort("\\B");
- RTLIL::SigSpec y2 = c2->getPort("\\Y");
+ RTLIL::SigSpec a2 = c2->getPort(ID(A));
+ RTLIL::SigSpec b2 = c2->getPort(ID(B));
+ RTLIL::SigSpec y2 = c2->getPort(ID(Y));
int a_width = max(a1.size(), a2.size());
int b_width = max(b1.size(), b2.size());
int y_width = max(y1.size(), y2.size());
- if (c1->type == "$shr" && a_signed)
+ if (c1->type == ID($shr) && a_signed)
{
a_width = max(y_width, a_width);
supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
- RTLIL::Wire *x = c1->type == "$alu" ? module->addWire(NEW_ID, y_width) : nullptr;
- RTLIL::Wire *co = c1->type == "$alu" ? module->addWire(NEW_ID, y_width) : nullptr;
+ RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
+ RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
- supercell->parameters["\\A_SIGNED"] = a_signed;
- supercell->parameters["\\B_SIGNED"] = b_signed;
- supercell->parameters["\\A_WIDTH"] = a_width;
- supercell->parameters["\\B_WIDTH"] = b_width;
- supercell->parameters["\\Y_WIDTH"] = y_width;
- supercell->setPort("\\A", a);
- supercell->setPort("\\B", b);
- supercell->setPort("\\Y", y);
- if (c1->type == "$alu") {
+ supercell->parameters[ID(A_SIGNED)] = a_signed;
+ supercell->parameters[ID(B_SIGNED)] = b_signed;
+ supercell->parameters[ID(A_WIDTH)] = a_width;
+ supercell->parameters[ID(B_WIDTH)] = b_width;
+ supercell->parameters[ID(Y_WIDTH)] = y_width;
+ supercell->setPort(ID(A), a);
+ supercell->setPort(ID(B), b);
+ supercell->setPort(ID(Y), y);
+ if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
- supercell_aux.insert(module->addMux(NEW_ID, c2->getPort("\\CI"), c1->getPort("\\CI"), act, ci));
- supercell_aux.insert(module->addMux(NEW_ID, c2->getPort("\\BI"), c1->getPort("\\BI"), act, bi));
- supercell->setPort("\\CI", ci);
- supercell->setPort("\\BI", bi);
- supercell->setPort("\\CO", co);
- supercell->setPort("\\X", x);
+ supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(CI)), c1->getPort(ID(CI)), act, ci));
+ supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(BI)), c1->getPort(ID(BI)), act, bi));
+ supercell->setPort(ID(CI), ci);
+ supercell->setPort(ID(BI), bi);
+ supercell->setPort(ID(CO), co);
+ supercell->setPort(ID(X), x);
}
supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
- if (c1->type == "$alu") {
- supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort("\\CO")));
- supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort("\\CO")));
- supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort("\\X")));
- supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort("\\X")));
+ if (c1->type == ID($alu)) {
+ supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID(CO))));
+ supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID(CO))));
+ supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID(X))));
+ supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID(X))));
}
supercell_aux.insert(supercell);
return supercell;
}
- if (c1->type == "$macc")
+ if (c1->type == ID($macc))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
supercell_aux.insert(supercell);
return supercell;
}
- if (c1->type == "$memrd")
+ if (c1->type == ID($memrd))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
- RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
- RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
+ RTLIL::SigSpec addr1 = c1->getPort(ID(ADDR));
+ RTLIL::SigSpec addr2 = c2->getPort(ID(ADDR));
if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2));
else
addr2.extend_u0(GetSize(addr1));
- supercell->setPort("\\ADDR", addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
- supercell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr1));
- supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
+ supercell->setPort(ID(ADDR), addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
+ supercell->parameters[ID(ABITS)] = RTLIL::Const(GetSize(addr1));
+ supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID(DATA)), c2->getPort(ID(DATA))));
supercell_aux.insert(supercell);
return supercell;
}
modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
for (auto &bit : pbits) {
- if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S")
- forbidden_controls_cache[cell].insert(bit.cell->getPort("\\S").extract(bit.offset, 1));
+ if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID(S))
+ forbidden_controls_cache[cell].insert(bit.cell->getPort(ID(S)).extract(bit.offset, 1));
consumer_cells.insert(bit.cell);
}
}
for (auto &pbit : modwalker.signal_consumers[bit]) {
log_assert(fwd_ct.cell_known(pbit.cell->type));
- if ((pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") && (pbit.port == "\\A" || pbit.port == "\\B"))
+ if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == ID(A) || pbit.port == ID(B)))
driven_data_muxes.insert(pbit.cell);
else
driven_cells.insert(pbit.cell);
bool used_in_a = false;
std::set<int> used_in_b_parts;
- int width = c->parameters.at("\\WIDTH").as_int();
- std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort("\\A"));
- std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort("\\B"));
- std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort("\\S"));
+ int width = c->parameters.at(ID(WIDTH)).as_int();
+ std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID(A)));
+ std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID(B)));
+ std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID(S)));
for (auto &bit : sig_a)
if (cell_out_bits.count(bit))
fwd_ct.setup_internals();
cone_ct.setup_internals();
- cone_ct.cell_types.erase("$mul");
- cone_ct.cell_types.erase("$mod");
- cone_ct.cell_types.erase("$div");
- cone_ct.cell_types.erase("$pow");
- cone_ct.cell_types.erase("$shl");
- cone_ct.cell_types.erase("$shr");
- cone_ct.cell_types.erase("$sshl");
- cone_ct.cell_types.erase("$sshr");
+ cone_ct.cell_types.erase(ID($mul));
+ cone_ct.cell_types.erase(ID($mod));
+ cone_ct.cell_types.erase(ID($div));
+ cone_ct.cell_types.erase(ID($pow));
+ cone_ct.cell_types.erase(ID($shl));
+ cone_ct.cell_types.erase(ID($shr));
+ cone_ct.cell_types.erase(ID($sshl));
+ cone_ct.cell_types.erase(ID($sshr));
modwalker.setup(design, module);
GetSize(shareable_cells), log_id(module));
for (auto cell : module->cells())
- if (cell->type == "$pmux")
- for (auto bit : cell->getPort("\\S"))
- for (auto other_bit : cell->getPort("\\S"))
+ if (cell->type == ID($pmux))
+ for (auto bit : cell->getPort(ID(S)))
+ for (auto other_bit : cell->getPort(ID(S)))
if (bit < other_bit)
exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit));
config.opt_aggressive = false;
config.opt_fast = false;
- config.generic_uni_ops.insert("$not");
- // config.generic_uni_ops.insert("$pos");
- config.generic_uni_ops.insert("$neg");
-
- config.generic_cbin_ops.insert("$and");
- config.generic_cbin_ops.insert("$or");
- config.generic_cbin_ops.insert("$xor");
- config.generic_cbin_ops.insert("$xnor");
-
- config.generic_bin_ops.insert("$shl");
- config.generic_bin_ops.insert("$shr");
- config.generic_bin_ops.insert("$sshl");
- config.generic_bin_ops.insert("$sshr");
-
- config.generic_bin_ops.insert("$lt");
- config.generic_bin_ops.insert("$le");
- config.generic_bin_ops.insert("$eq");
- config.generic_bin_ops.insert("$ne");
- config.generic_bin_ops.insert("$eqx");
- config.generic_bin_ops.insert("$nex");
- config.generic_bin_ops.insert("$ge");
- config.generic_bin_ops.insert("$gt");
-
- config.generic_cbin_ops.insert("$add");
- config.generic_cbin_ops.insert("$mul");
-
- config.generic_bin_ops.insert("$sub");
- config.generic_bin_ops.insert("$div");
- config.generic_bin_ops.insert("$mod");
- // config.generic_bin_ops.insert("$pow");
-
- config.generic_uni_ops.insert("$logic_not");
- config.generic_cbin_ops.insert("$logic_and");
- config.generic_cbin_ops.insert("$logic_or");
-
- config.generic_other_ops.insert("$alu");
- config.generic_other_ops.insert("$macc");
+ config.generic_uni_ops.insert(ID($not));
+ // config.generic_uni_ops.insert(ID($pos));
+ config.generic_uni_ops.insert(ID($neg));
+
+ config.generic_cbin_ops.insert(ID($and));
+ config.generic_cbin_ops.insert(ID($or));
+ config.generic_cbin_ops.insert(ID($xor));
+ config.generic_cbin_ops.insert(ID($xnor));
+
+ config.generic_bin_ops.insert(ID($shl));
+ config.generic_bin_ops.insert(ID($shr));
+ config.generic_bin_ops.insert(ID($sshl));
+ config.generic_bin_ops.insert(ID($sshr));
+
+ config.generic_bin_ops.insert(ID($lt));
+ config.generic_bin_ops.insert(ID($le));
+ config.generic_bin_ops.insert(ID($eq));
+ config.generic_bin_ops.insert(ID($ne));
+ config.generic_bin_ops.insert(ID($eqx));
+ config.generic_bin_ops.insert(ID($nex));
+ config.generic_bin_ops.insert(ID($ge));
+ config.generic_bin_ops.insert(ID($gt));
+
+ config.generic_cbin_ops.insert(ID($add));
+ config.generic_cbin_ops.insert(ID($mul));
+
+ config.generic_bin_ops.insert(ID($sub));
+ config.generic_bin_ops.insert(ID($div));
+ config.generic_bin_ops.insert(ID($mod));
+ // config.generic_bin_ops.insert(ID($pow));
+
+ config.generic_uni_ops.insert(ID($logic_not));
+ config.generic_cbin_ops.insert(ID($logic_and));
+ config.generic_cbin_ops.insert(ID($logic_or));
+
+ config.generic_other_ops.insert(ID($alu));
+ config.generic_other_ops.insert(ID($macc));
log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
WreduceConfig()
{
supported_cell_types = pool<IdString>({
- "$not", "$pos", "$neg",
- "$and", "$or", "$xor", "$xnor",
- "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
- "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
- "$add", "$sub", "$mul", // "$div", "$mod", "$pow",
- "$mux", "$pmux",
- "$dff", "$adff"
+ ID($not), ID($pos), ID($neg),
+ ID($and), ID($or), ID($xor), ID($xnor),
+ ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
+ ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
+ ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($pow),
+ ID($mux), ID($pmux),
+ ID($dff), ID($adff)
});
}
};
{
// Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused
- SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
- SigSpec sig_b = mi.sigmap(cell->getPort("\\B"));
- SigSpec sig_s = mi.sigmap(cell->getPort("\\S"));
- SigSpec sig_y = mi.sigmap(cell->getPort("\\Y"));
+ SigSpec sig_a = mi.sigmap(cell->getPort(ID(A)));
+ SigSpec sig_b = mi.sigmap(cell->getPort(ID(B)));
+ SigSpec sig_s = mi.sigmap(cell->getPort(ID(S)));
+ SigSpec sig_y = mi.sigmap(cell->getPort(ID(Y)));
std::vector<SigBit> bits_removed;
if (sig_y.has_const())
for (auto bit : new_work_queue_bits)
work_queue_bits.insert(bit);
- cell->setPort("\\A", new_sig_a);
- cell->setPort("\\B", new_sig_b);
- cell->setPort("\\Y", new_sig_y);
+ cell->setPort(ID(A), new_sig_a);
+ cell->setPort(ID(B), new_sig_b);
+ cell->setPort(ID(Y), new_sig_y);
cell->fixup_parameters();
module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
{
// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
- SigSpec sig_d = mi.sigmap(cell->getPort("\\D"));
- SigSpec sig_q = mi.sigmap(cell->getPort("\\Q"));
+ SigSpec sig_d = mi.sigmap(cell->getPort(ID(D)));
+ SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q)));
Const initval;
int width_before = GetSize(sig_q);
work_queue_bits.insert(bit);
// Narrow ARST_VALUE parameter to new size.
- if (cell->parameters.count("\\ARST_VALUE")) {
- Const arst_value = cell->getParam("\\ARST_VALUE");
+ if (cell->parameters.count(ID(ARST_VALUE))) {
+ Const arst_value = cell->getParam(ID(ARST_VALUE));
arst_value.bits.resize(GetSize(sig_q));
- cell->setParam("\\ARST_VALUE", arst_value);
+ cell->setParam(ID(ARST_VALUE), arst_value);
}
- cell->setPort("\\D", sig_d);
- cell->setPort("\\Q", sig_q);
+ cell->setPort(ID(D), sig_d);
+ cell->setPort(ID(Q), sig_q);
cell->fixup_parameters();
}
port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port)));
- if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr"))
+ if (port == 'B' && cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr)))
port_signed = false;
int bits_removed = 0;
if (!cell->type.in(config->supported_cell_types))
return;
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
return run_cell_mux(cell);
- if (cell->type.in("$dff", "$adff"))
+ if (cell->type.in(ID($dff), ID($adff)))
return run_cell_dff(cell);
- SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
+ SigSpec sig = mi.sigmap(cell->getPort(ID(Y)));
if (sig.has_const())
return;
// Reduce size of ports A and B based on constant input bits and size of output port
- int max_port_a_size = cell->hasPort("\\A") ? GetSize(cell->getPort("\\A")) : -1;
- int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1;
+ int max_port_a_size = cell->hasPort(ID(A)) ? GetSize(cell->getPort(ID(A))) : -1;
+ int max_port_b_size = cell->hasPort(ID(B)) ? GetSize(cell->getPort(ID(B))) : -1;
- if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
+ if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) {
max_port_a_size = min(max_port_a_size, GetSize(sig));
max_port_b_size = min(max_port_b_size, GetSize(sig));
}
bool port_a_signed = false;
bool port_b_signed = false;
- if (max_port_a_size >= 0 && cell->type != "$shiftx")
+ if (max_port_a_size >= 0 && cell->type != ID($shiftx))
run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something);
if (max_port_b_size >= 0)
run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something);
- if (cell->hasPort("\\A") && cell->hasPort("\\B") && port_a_signed && port_b_signed) {
- SigSpec sig_a = mi.sigmap(cell->getPort("\\A")), sig_b = mi.sigmap(cell->getPort("\\B"));
+ if (cell->hasPort(ID(A)) && cell->hasPort(ID(B)) && port_a_signed && port_b_signed) {
+ SigSpec sig_a = mi.sigmap(cell->getPort(ID(A))), sig_b = mi.sigmap(cell->getPort(ID(B)));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
- cell->setParam("\\A_SIGNED", 0);
- cell->setParam("\\B_SIGNED", 0);
+ cell->setParam(ID(A_SIGNED), 0);
+ cell->setParam(ID(B_SIGNED), 0);
port_a_signed = false;
port_b_signed = false;
did_something = true;
}
}
- if (cell->hasPort("\\A") && !cell->hasPort("\\B") && port_a_signed) {
- SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
+ if (cell->hasPort(ID(A)) && !cell->hasPort(ID(B)) && port_a_signed) {
+ SigSpec sig_a = mi.sigmap(cell->getPort(ID(A)));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
- cell->setParam("\\A_SIGNED", 0);
+ cell->setParam(ID(A_SIGNED), 0);
port_a_signed = false;
did_something = true;
}
// Reduce size of port Y based on sizes for A and B and unused bits in Y
int bits_removed = 0;
- if (port_a_signed && cell->type == "$shr") {
+ if (port_a_signed && cell->type == ID($shr)) {
// do not reduce size of output on $shr cells with signed A inputs
} else {
while (GetSize(sig) > 0)
}
}
- if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor", "$sub"))
+ if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
{
- bool is_signed = cell->getParam("\\A_SIGNED").as_bool() || cell->type == "$sub";
+ bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool() || cell->type == ID($sub);
int a_size = 0, b_size = 0;
- if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A"));
- if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B"));
+ if (cell->hasPort(ID(A))) a_size = GetSize(cell->getPort(ID(A)));
+ if (cell->hasPort(ID(B))) b_size = GetSize(cell->getPort(ID(B)));
int max_y_size = max(a_size, b_size);
- if (cell->type.in("$add", "$sub"))
+ if (cell->type.in(ID($add), ID($sub)))
max_y_size++;
- if (cell->type == "$mul")
+ if (cell->type == ID($mul))
max_y_size = a_size + b_size;
while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) {
if (bits_removed) {
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
- cell->setPort("\\Y", sig);
+ cell->setPort(ID(Y), sig);
did_something = true;
}
static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
- count -= w->attributes.count("\\src");
- count -= w->attributes.count("\\unused_bits");
+ count -= w->attributes.count(ID(src));
+ count -= w->attributes.count(ID(unused_bits));
return count;
}
SigMap init_attr_sigmap = mi.sigmap;
for (auto w : module->wires()) {
- if (w->get_bool_attribute("\\keep"))
+ if (w->get_bool_attribute(ID(keep)))
for (auto bit : mi.sigmap(w))
keep_bits.insert(bit);
- if (w->attributes.count("\\init")) {
- Const initval = w->attributes.at("\\init");
+ if (w->attributes.count(ID(init))) {
+ Const initval = w->attributes.at(ID(init));
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++)
if (!remove_init_bits.empty()) {
for (auto w : module->wires()) {
- if (w->attributes.count("\\init")) {
- Const initval = w->attributes.at("\\init");
+ if (w->attributes.count(ID(init))) {
+ Const initval = w->attributes.at(ID(init));
Const new_initval(State::Sx, GetSize(w));
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
if (!remove_init_bits.count(initsig[i]))
new_initval[i] = initval[i];
}
- w->attributes.at("\\init") = new_initval;
+ w->attributes.at(ID(init)) = new_initval;
}
}
}
for (auto c : module->selected_cells())
{
- if (c->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
- "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
- "$logic_not", "$logic_and", "$logic_or") && GetSize(c->getPort("\\Y")) > 1) {
- SigSpec sig = c->getPort("\\Y");
+ if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
+ ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
+ ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(ID(Y))) > 1) {
+ SigSpec sig = c->getPort(ID(Y));
if (!sig.has_const()) {
- c->setPort("\\Y", sig[0]);
- c->setParam("\\Y_WIDTH", 1);
+ c->setPort(ID(Y), sig[0]);
+ c->setParam(ID(Y_WIDTH), 1);
sig.remove(0);
module->connect(sig, Const(0, GetSize(sig)));
}
}
- if (c->type.in("$div", "$mod", "$pow"))
+ if (c->type.in(ID($div), ID($mod), ID($pow)))
{
- SigSpec A = c->getPort("\\A");
+ SigSpec A = c->getPort(ID(A));
int original_a_width = GetSize(A);
- if (c->getParam("\\A_SIGNED").as_bool()) {
+ if (c->getParam(ID(A_SIGNED)).as_bool()) {
while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
A.remove(GetSize(A)-1, 1);
} else {
if (original_a_width != GetSize(A)) {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
- c->setPort("\\A", A);
- c->setParam("\\A_WIDTH", GetSize(A));
+ c->setPort(ID(A), A);
+ c->setParam(ID(A_WIDTH), GetSize(A));
}
- SigSpec B = c->getPort("\\B");
+ SigSpec B = c->getPort(ID(B));
int original_b_width = GetSize(B);
- if (c->getParam("\\B_SIGNED").as_bool()) {
+ if (c->getParam(ID(B_SIGNED)).as_bool()) {
while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
B.remove(GetSize(B)-1, 1);
} else {
if (original_b_width != GetSize(B)) {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
- c->setPort("\\B", B);
- c->setParam("\\B_WIDTH", GetSize(B));
+ c->setPort(ID(B), B);
+ c->setParam(ID(B_WIDTH), GetSize(B));
}
}
- if (!opt_memx && c->type.in("$memrd", "$memwr", "$meminit")) {
- IdString memid = c->getParam("\\MEMID").decode_string();
+ if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
+ IdString memid = c->getParam(ID(MEMID)).decode_string();
RTLIL::Memory *mem = module->memories.at(memid);
if (mem->start_offset >= 0) {
- int cur_addrbits = c->getParam("\\ABITS").as_int();
+ int cur_addrbits = c->getParam(ID(ABITS)).as_int();
int max_addrbits = ceil_log2(mem->start_offset + mem->size);
if (cur_addrbits > max_addrbits) {
log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
cur_addrbits-max_addrbits, cur_addrbits,
- c->type == "$memrd" ? "read" : c->type == "$memwr" ? "write" : "init",
+ c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
log_id(module), log_id(c), log_id(memid));
- c->setParam("\\ABITS", max_addrbits);
- c->setPort("\\ADDR", c->getPort("\\ADDR").extract(0, max_addrbits));
+ c->setParam(ID(ABITS), max_addrbits);
+ c->setPort(ID(ADDR), c->getPort(ID(ADDR)).extract(0, max_addrbits));
}
}
}
projects / yosys.git / commitdiff