ls2: Added not about transistor count estimation.

diff --git a/HDL_workflow/ls2.mdwn b/HDL_workflow/ls2.mdwn
index 50db6f8760a0791db6ccffddb23b627b7f8f3217..3d8521dc7eef15452e8c339cc44c75fe235a2f8d 100644 (file)
--- a/HDL_workflow/ls2.mdwn
+++ b/HDL_workflow/ls2.mdwn
@@ -110,3 +110,15 @@ After that you can compile microwatt-verilator:
 
        export FPGA_TARGET=verilator
        make microwatt-verilator
+
+# Estimating transistor count using yosys
+
+Use yosys to run synthesis and using `stat` to view gate/transistor count:
+
+    cd src/ls2/
+    yosys
+    yosys> read_verilog ls2.v external_core_top.v ../uart16550/rtl/verilog/*.v
+    yosys> synth
+    yosys> tee -a stat_cmos.log stat -tech cmos
+
+Then you can view the resulting log file afterwards. Bare in mind `synth` will probably take a while. **TODO: Find multi-threaded option**