neon.md (neon_vget_lanev2di): Handle big-endian targets.

2015-08-04  Christophe Lyon  <christophe.lyon@linaro.org>

	* config/arm/neon.md (neon_vget_lanev2di): Handle big-endian
	targets.

From-SVN: r226574

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 41ccf74b890d68b8fa7fa33f568ad29e9337354c..49751a7eddc00fb120e91ab04e18ce1f13f3261e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-08-04  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       * config/arm/neon.md (neon_vget_lanev2di): Handle big-endian
+       targets.
+
 2015-08-04  Nathan Sidwell  <nathan@codesourcery.com>
 
        * config/nvptx/nvptx.h (struct nvptx_pseudo_info): Delete.

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 4af74ce96ede0f7dbbea1ba95f938b5facdf3570..b1bf26a9451250e2041c3a2573653487b5246998 100644 (file)
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2731,7 +2731,22 @@
    (match_operand:SI 2 "immediate_operand" "")]
   "TARGET_NEON"
 {
-  int lane = INTVAL (operands[2]);
+  int lane;
+
+if (BYTES_BIG_ENDIAN)
+    {
+      /* The intrinsics are defined in terms of a model where the
+        element ordering in memory is vldm order, whereas the generic
+        RTL is defined in terms of a model where the element ordering
+        in memory is array order.  Convert the lane number to conform
+        to this model.  */
+      unsigned int elt = INTVAL (operands[2]);
+      unsigned int reg_nelts = 2;
+      elt ^= reg_nelts - 1;
+      operands[2] = GEN_INT (elt);
+    }
+
+  lane = INTVAL (operands[2]);
   gcc_assert ((lane ==0) || (lane == 1));
   emit_move_insn (operands[0], lane == 0
                                ? gen_lowpart (DImode, operands[1])