Reject wide ports in some passes that will never support them.

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index bc0504d6479d4b6ddcba10b65f9b14cbb7ba98f5..999836882ee6c8802e278cc72f27ca3c2705bc75 100644 (file)
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -728,10 +728,19 @@ struct BtorWorker
                                log_error("Memory %s.%s has mixed async/sync write ports.\n",
                                                log_id(module), log_id(mem->memid));
 
-                       for (auto &port : mem->rd_ports)
+                       for (auto &port : mem->rd_ports) {
                                if (port.clk_enable)
-                                       log_error("Memory %s.%s has sync read ports.\n",
+                                       log_error("Memory %s.%s has sync read ports.  Please use memory_nordff to convert them first.\n",
+                                                       log_id(module), log_id(mem->memid));
+                               if (port.wide_log2)
+                                       log_error("Memory %s.%s has wide read ports.  Please use memory_narrow to convert them first.\n",
+                                                       log_id(module), log_id(mem->memid));
+                       }
+                       for (auto &port : mem->wr_ports) {
+                               if (port.wide_log2)
+                                       log_error("Memory %s.%s has wide write ports.  Please use memory_narrow to convert them first.\n",
                                                        log_id(module), log_id(mem->memid));
+                       }
 
                        int data_sid = get_bv_sid(mem->width);
                        int bool_sid = get_bv_sid(1);

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index f99becacffa9ef9481f6884fd5dd0e4ba23405a1..dee24d0e2295a5ddac48f971fc2297e9c1e7abb5 100644 (file)
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -993,6 +993,8 @@ struct FirrtlWorker
 
                                if (port.clk_enable)
                                        log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
+                               if (port.wide_log2 != 0)
+                                       log_error("Wide read port %d on memory %s.%s.  Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid));
 
                                std::ostringstream rpe;
 
@@ -1014,6 +1016,8 @@ struct FirrtlWorker
 
                                if (!port.clk_enable)
                                        log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
+                               if (port.wide_log2 != 0)
+                                       log_error("Wide write port %d on memory %s.%s.  Use memory_narrow to convert them first.\n", i, log_id(module), log_id(mem.memid));
                                if (!port.clk_polarity)
                                        log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
                                for (int i = 1; i < GetSize(port.en); i++)

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index e0f43d6865d83011ce67254aa3d08a86b74bc5d9..4dee0d4fbc9d6f08563f6a59ed2131f046756435 100644 (file)
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -715,6 +715,12 @@ struct Smt2Worker
                                        has_sync_wr = true;
                                else
                                        has_async_wr = true;
+                               if (port.wide_log2)
+                                       log_error("Memory %s.%s has wide write ports. This is not supported by \"write_smt2\".  Use memory_narrow to convert them first.\n", log_id(cell), log_id(module));
+                       }
+                       for (auto &port : mem->rd_ports) {
+                               if (port.wide_log2)
+                                       log_error("Memory %s.%s has wide read ports. This is not supported by \"write_smt2\".  Use memory_narrow to convert them first.\n", log_id(cell), log_id(module));
                        }
                        if (has_async_wr && has_sync_wr)
                                log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module));

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index c6948fdbadb2ca3802b00d9b347243c2e4a03b54..a860fc693c6f3072596f54f475f98ebe3448af08 100644 (file)
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1057,6 +1057,20 @@ void handle_memory(Mem &mem, const rules_t &rules)
                log(" %s=%d", it.first.c_str(), it.second);
        log("\n");
 
+       for (auto &port : mem.rd_ports) {
+               if (port.wide_log2) {
+                       log("Wide read ports are not supported, skipping.\n");
+                       return;
+               }
+       }
+
+       for (auto &port : mem.wr_ports) {
+               if (port.wide_log2) {
+                       log("Wide write ports are not supported, skipping.\n");
+                       return;
+               }
+       }
+
        pool<pair<IdString, int>> failed_brams;
        dict<pair<int, int>, tuple<int, int, int>> best_rule_cache;