(no commit message)

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index c0edc7beb687166a4ce7f5c213d63a2167ef1493..6d707b5ed4c340094110c0c5bbaa5ab2c4d56c7f 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -270,6 +270,13 @@ like Standard RISC-V as far as the instruction execution order is
 concerned, regardless of whether it is PC, PCVBLK, VL or SUBVL that
 is currently being incremented.
 
+This.is extremely important. Exceptions
+**MUST** be raised one at a time and in
+strict sequential program order.
+
+No instructions are permitted to be out of
+sequence, therefore no exceptions are permitted to be, either.
+
 # Hints
 
 With Simple-V being capable of issuing *parallel* instructions where