[[sv/ldst]], be set to an arbitrary value. Deterministic behaviour
is *required*.
+Important also to note is that reduce mode is implied by Data-Dependent Fail-First.
+In other words where normally if the destination is Scalar, the looping
+terminates at the first result, Data-Dependent Fail-First *continues*
+just as it does in reduce mode. This allows effectively *conditional*
+reduction (one register is both a source and destination) where testing of
+each result gives an option to exit.
+
**Apparent contradictory behaviour compared to Rc=1,VLi=0**
In [[openpower/sv/normal]] mode when Rc=1 and VLi=0 the Vector of