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diff --git a/cole.mdwn b/cole.mdwn
index 1cbb26f8cec1346456d7e82ceac2c0cc169c636f..0786f8b8a839f30e7aed2ab154374414e00efdbd 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -13,13 +13,9 @@ move things along from one stage to the next
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
 
 ## List of things that need more fleshed out bug reports:
@@ -27,9 +23,11 @@ move things along from one stage to the next
 - Scoreboard documentation
   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
+
 - LDST documentation
   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
+
 ## Completed but not yet submitted
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG