xilinx_dsp: another typo; move xilinx specific test

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 20925c0dc8d6c15203cab033b81fbe73c07dbfd0..af47ab111d3d1c2fe3bd5a0418af69edcae778c1 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -460,7 +460,7 @@ arg argD argQ clock
 
 code
        dff = nullptr;
-       if (argQ.empty() == 0)
+       if (argQ.empty())
                reject;
        for (const auto &c : argQ.chunks()) {
                // Abandon matches when 'Q' is a constant

diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys
new file mode 100644 (file)
index 0000000..15cab51
--- /dev/null
+++ b/tests/arch/xilinx/bug1462.ys
@@ -0,0 +1,11 @@
+read_verilog << EOF
+module top(...);
+input wire [31:0] A;
+output wire [31:0] P;
+
+assign P = A * 32'h12300000;
+
+endmodule
+EOF
+
+synth_xilinx

diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys
deleted file mode 100644 (file)
index 15cab51..0000000
--- a/tests/various/bug1462.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog << EOF
-module top(...);
-input wire [31:0] A;
-output wire [31:0] P;
-
-assign P = A * 32'h12300000;
-
-endmodule
-EOF
-
-synth_xilinx