Specify Spike ISA explicitly

diff --git a/benchmarks/Makefile b/benchmarks/Makefile
index ce9d4f9713b27c12ff14ee386bba4ad0be36d741..bc179279c8c49c10c325858a0feed67f2c82a16a 100644 (file)
--- a/benchmarks/Makefile
+++ b/benchmarks/Makefile
@@ -55,7 +55,7 @@ RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
 RISCV_LINK_MT ?= $(RISCV_GCC) -T $(src_dir)/common/test-mt.ld
 RISCV_LINK_OPTS ?= -nostdlib -nostartfiles -ffast-math -lgcc
 RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data
-RISCV_SIM ?= spike
+RISCV_SIM ?= spike --isa=rv$(XLEN)gc
 
 VPATH += $(addprefix $(src_dir)/, $(bmarks))
 VPATH += $(src_dir)/common

diff --git a/isa/Makefile b/isa/Makefile
index 1afa4d6cd4501c0f7b26eb67431658cc715b4c62..3ed1b60f995869564c549604e48e51032834b633 100644 (file)
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -43,10 +43,10 @@ vpath %.S $(src_dir)
        $(RISCV_OBJDUMP) $< > $@
 
 %.out: %
-       $(RISCV_SIM) $< 2> $@
+       $(RISCV_SIM) --isa=rv64gc $< 2> $@
 
 %.out32: %
-       $(RISCV_SIM) --isa=RV32 $< 2> $@
+       $(RISCV_SIM) --isa=rv32gc $< 2> $@
 
 define compile_template