CSKY: Change mvtc and mulsw's ISA flag.

gas/
	* config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
	(CSKY_ISA_860): Likewise.

include/
	* opcode/csky.h (CSKY_ISA_DSPE60): Define.

opcodes/
	* csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
	ISA flag.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 897d42b2445b74b4eb9a15c5aeb769d5e6d698d3..94c3bbb4cdd4db7099fbb5a8a0caca02506500cd 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+       * config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
+       (CSKY_ISA_860): Likewise.
+
 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 
        * config/tc-csky.c (float_abi): New.

diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index 25f77131d34fb5af159671b497bf87250ac6d90a..2d57bd246984c9f406048108bc37fcc626b4f334 100644 (file)
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -611,7 +611,7 @@ const struct csky_cpu_info csky_cpus[] =
 
   /* CK801 series.  */
 #define CSKY_ISA_801    CSKYV2_ISA_E1
-#define CSKYV2_ISA_DSP  (CSKY_ISA_DSP | CSKY_ISA_DSP_1E2)
+#define CSKYV2_ISA_DSP  (CSKY_ISA_DSP | CSKY_ISA_DSP_1E2 | CSKY_ISA_DSPE60)
   {"ck801", CSKY_ARCH_801, CSKY_ISA_801},
   {"ck801t", CSKY_ARCH_801, CSKY_ISA_801 | CSKY_ISA_TRUST},
 
@@ -708,7 +708,7 @@ const struct csky_cpu_info csky_cpus[] =
   {"ck810ftv", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST},
 
   /* CK860 Series.  */
-#define CSKY_ISA_860    (CSKY_ISA_810 | CSKYV2_ISA_10E60 | CSKYV2_ISA_3E3R3)
+#define CSKY_ISA_860    (CSKY_ISA_810 | CSKYV2_ISA_10E60 | CSKYV2_ISA_3E3R3 | CSKY_ISA_DSPE60)
 #define CSKY_ISA_860F (CSKY_ISA_860 | CSKY_ISA_FLOAT_7E60)
   {"ck860", CSKY_ARCH_860, CSKY_ISA_860},
   {"ck860f", CSKY_ARCH_860, CSKY_ISA_860F},

diff --git a/include/ChangeLog b/include/ChangeLog
index 33998eb1dfa6cbe8324f24718aafd7389dfbf836..28779bc6e486ef1cf6c344197751fd0ea0bdecae 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+       * opcode/csky.h (CSKY_ISA_DSPE60): Define.
+
 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 
        * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.

diff --git a/include/opcode/csky.h b/include/opcode/csky.h
index 1ad7f581ab67aee98766d93aed3619443b09947b..421454383e8e5d1f057bc48ba2060b9542fe75d8 100644 (file)
--- a/include/opcode/csky.h
+++ b/include/opcode/csky.h
@@ -47,6 +47,7 @@
 #define CSKY_ISA_DSP        (1L << 20)
 #define CSKY_ISA_DSP_1E2    (1L << 21)
 #define CSKY_ISA_DSP_ENHANCE (1L << 22)
+#define CSKY_ISA_DSPE60     (1L << 23)
 
 /* Base float instruction (803f & 810f).  */
 #define CSKY_ISA_FLOAT_E1   (1L << 25)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4f416bf7f9429aa84868ffeb3abc25ed6f019791..bd5a284949d06e49adc462f2ce5fbb472e40efa2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+       * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
+       ISA flag.
+
 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 
        * csky-dis.c (csky_output_operand): Add handlers for

diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index fac30ae61db3c047287f82d43fb00ed7ddd5a2ee..5a6068c329cb7750778bdd831df3f37834662d88 100644 (file)
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -2687,7 +2687,7 @@ const struct csky_opcode csky_v2_opcodes[] =
          CSKY_ISA_DSP),
     OP32 ("mvtc",
          OPCODE_INFO0 (0xc4009a00),
-         CSKY_ISA_DSP),
+         CSKY_ISA_DSPE60),
     OP32 ("mfhi",
          OPCODE_INFO1 (0xc4009c20,
                        (0_4, AREG, OPRND_SHIFT_0_BIT)),
@@ -4119,7 +4119,7 @@ const struct csky_opcode csky_v2_opcodes[] =
           OPCODE_INFO2 (0xc4009420,
                         (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT),
                         (21_25, AREG, OPRND_SHIFT_0_BIT)),
-          CSKY_ISA_DSP),
+          CSKY_ISA_DSPE60),
     OP16_OP32 ("ld.b",
               SOPCODE_INFO2 (0x8000,
                              (5_7, GREG0_7, OPRND_SHIFT_0_BIT),