Collect parameters in hierarchy -generate (and do nothing with them)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 04274990d9f286a2255e5054bb47805b536bf1dd..8ef169ce919923abe471cdcf9265238700300a96 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -50,17 +50,21 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
        for (auto &celltype : found_celltypes)
        {
                std::set<std::string> portnames;
+               std::set<std::string> parameters;
                std::map<std::string, int> portwidths;
                log("Generate module for cell type %s:\n", celltype.c_str());
 
                for (auto i1 : design->modules)
                for (auto i2 : i1.second->cells)
-                       if (i2.second->type == celltype)
+                       if (i2.second->type == celltype) {
                                for (auto &conn : i2.second->connections) {
                                        if (conn.first[0] != '$')
                                                portnames.insert(conn.first);
                                        portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width);
                                }
+                               for (auto &para : i2.second->parameters)
+                                       parameters.insert(para.first);
+                       }
 
                for (auto &decl : portdecls)
                        if (decl.index > 0)
@@ -121,6 +125,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
                        mod->add(wire);
                }
 
+               for (auto &para : parameters)
+                       log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
+
                log("  module %s created.\n", RTLIL::id2cstr(mod->name));
        }
 }