Bugfix in Verific front-end

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1ec6a7c0a3782dc65cda7d04ac010597e2fa3e61..d2440f699b145431637d47387d2199b050d39b67 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -773,8 +773,11 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
                        }
                        IdString port_name_id = RTLIL::escape_id(port_name);
                        auto &sigvec = cell_port_conns[port_name_id];
-                       if (GetSize(sigvec) <= port_offset)
-                               sigvec.resize(port_offset+1, State::Sz);
+                       if (GetSize(sigvec) <= port_offset) {
+                               SigSpec zwires = module->addWire(NEW_ID, port_offset+1-GetSize(sigvec));
+                               for (auto bit : zwires)
+                                       sigvec.push_back(bit);
+                       }
                        sigvec[port_offset] = net_map.at(pr->GetNet());
                }