xilinx_ise: add lock cycle to bitgen

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 5a2f6719a940a5a43d2303f28fc8d83d858047cf..04cc7cb01f204a077d65be7a4d885d2d39b367d7 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -101,7 +101,7 @@ xst -ifn {build_name}.xst
 ngdbuild -uc {build_name}.ucf {build_name}.ngc
 map -ol high -w {build_name}.ngd
 par -ol high -w {build_name}.ncd {build_name}-routed.ncd
-bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit
+bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit
 """.format(build_name=build_name, xilinx_settings_file=xilinx_settings_file)
        build_script_file = "build_" + build_name + ".sh"
        tools.write_to_file(build_script_file, build_script_contents)