mem: Add a header latency parameter to the XBar

The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.

Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30054
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index deed98f164a52aaf29683c1f5f052733f1e2645f..84aae9948f0d1a3d416b2e0453f0dd76f5527c30 100644 (file)
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
+# Copyright (c) 2012, 2015, 2017, 2019-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -68,6 +68,11 @@ class BaseXBar(ClockedObject):
     forward_latency = Param.Cycles("Forward latency")
     response_latency = Param.Cycles("Response latency")
 
+    # The XBar uses one Layer per master. Each Layer forwards a packet
+    # to its destination and is occupied for header_latency + size /
+    # width cycles
+    header_latency = Param.Cycles(1, "Header latency")
+
     # Width governing the throughput of the crossbar
     width = Param.Unsigned("Datapath width per port (bytes)")
 

diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 952bd414156c3a91c49b14ee8726fcf11a893624..7fb9c346eaf11fcfdbe8b0c3d54417eb9ca361a2 100644 (file)
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2019 ARM Limited
+ * Copyright (c) 2011-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -180,7 +180,7 @@ CoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
     calcPacketTiming(pkt, xbar_delay);
 
     // determine how long to be crossbar layer is busy
-    Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+    Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
 
     // is this the destination point for this packet? (e.g. true if
     // this xbar is the PoC for a cache maintenance operation to the
@@ -471,7 +471,7 @@ CoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
     calcPacketTiming(pkt, xbar_delay);
 
     // determine how long to be crossbar layer is busy
-    Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+    Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
 
     if (snoopFilter && !system->bypassCaches()) {
         // let the snoop filter inspect the response and update its state
@@ -619,7 +619,7 @@ CoherentXBar::recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id)
     calcPacketTiming(pkt, xbar_delay);
 
     // determine how long to be crossbar layer is busy
-    Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+    Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;
 
     // forward it either as a snoop response or a normal response
     if (forwardAsSnoop) {

diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 99202161f671f6ae423d8449b63092e8af965339..f0b4ba3a7d221a0231c164457127e47ee22540cc 100644 (file)
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@ BaseXBar::BaseXBar(const BaseXBarParams *p)
       frontendLatency(p->frontend_latency),
       forwardLatency(p->forward_latency),
       responseLatency(p->response_latency),
+      headerLatency(p->header_latency),
       width(p->width),
       gotAddrRanges(p->port_default_connection_count +
                           p->port_master_connection_count, false),

diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 4488f74bcdd2f1402bcab3ada12783d84ac992e1..086d7f41e3a7dc4702c8dc55d54437c1cc5e683f 100644 (file)
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -307,6 +307,8 @@ class BaseXBar : public ClockedObject
     const Cycles frontendLatency;
     const Cycles forwardLatency;
     const Cycles responseLatency;
+    /** Cycles the layer is occupied processing the packet header */
+    const Cycles headerLatency;
     /** the width of the xbar in bytes */
     const uint32_t width;