build/xilinx/vivado: use build_name as top in synth_design

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 032b78bbec673e77cab835fcb3267cc9bc66d83a..f199c075d9eec9c78d4df88f46daadef319baf75 100644 (file)
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -87,7 +87,7 @@ class XilinxVivadoToolchain:
 
         tcl.append("read_xdc {}.xdc".format(build_name))
         tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
-        tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths)))
+        tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
         tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
         tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
         tcl.append("place_design")