Copy Verific vdbs files to Yosys "share" data directory

diff --git a/Makefile b/Makefile
index 325f25a1772073be308b8795c38609721dacbd8b..45bdc47acd7ba62bd069218c0136a195b958f517 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -92,7 +92,7 @@ endif
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
 VERIFIC_COMPONENTS ?= verilog vhdl database util containers
-CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -D'VERIFIC_DIR="$(VERIFIC_DIR)"'
+CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS))
 endif
 

diff --git a/frontends/verific/Makefile.inc b/frontends/verific/Makefile.inc
index 74a669ef49c3dfbd8db157a3764434b479bf947e..eca23e58c5eb61a38983ac2bb93b3c7d86a1da60 100644 (file)
--- a/frontends/verific/Makefile.inc
+++ b/frontends/verific/Makefile.inc
@@ -1 +1,16 @@
+
 OBJS += frontends/verific/verific.o
+
+ifeq ($(ENABLE_VERIFIC),1)
+
+EXTRA_TARGETS += share/verific
+
+share/verific:
+       rm -rf share/verific.new
+       mkdir -p share/verific.new
+       cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs share/verific.new/vhdl_vdbs_1993
+       cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008 share/verific.new/vhdl_vdbs_2008
+       mv share/verific.new share/verific
+
+endif
+

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c78d19f24f0a0432c61a1640784f61d0261323f2..bc6abc5f86c6ae471fa67c082308ff748a5a4832 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -27,7 +27,7 @@
 #include <string.h>
 #include <dirent.h>
 
-#ifdef VERIFIC_DIR
+#ifdef YOSYS_ENABLE_VERIFIC
 
 #include "veri_file.h"
 #include "vhdl_file.h"
@@ -482,7 +482,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
        }
 }
 
-#endif /* VERIFIC_DIR */
+#endif /* YOSYS_ENABLE_VERIFIC */
 
 struct VerificPass : public Pass {
        VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
@@ -509,7 +509,7 @@ struct VerificPass : public Pass {
                log("Visit http://verific.com/ for more information on Verific.\n");
                log("\n");
        }
-#ifdef VERIFIC_DIR
+#ifdef YOSYS_ENABLE_VERIFIC
        virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
        {
                log_header("Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n");
@@ -553,7 +553,7 @@ struct VerificPass : public Pass {
                }
 
                if (args.size() > 1 && args[1] == "-vhdl87") {
-                       vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
+                       vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
                        for (size_t argidx = 2; argidx < args.size(); argidx++)
                                if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87))
                                        log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
@@ -561,7 +561,7 @@ struct VerificPass : public Pass {
                }
 
                if (args.size() > 1 && args[1] == "-vhdl93") {
-                       vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
+                       vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
                        for (size_t argidx = 2; argidx < args.size(); argidx++)
                                if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93))
                                        log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
@@ -569,7 +569,7 @@ struct VerificPass : public Pass {
                }
 
                if (args.size() > 1 && args[1] == "-vhdl2k") {
-                       vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
+                       vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
                        for (size_t argidx = 2; argidx < args.size(); argidx++)
                                if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K))
                                        log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
@@ -577,7 +577,7 @@ struct VerificPass : public Pass {
                }
 
                if (args.size() > 1 && args[1] == "-vhdl2008") {
-                       vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
+                       vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
                        for (size_t argidx = 2; argidx < args.size(); argidx++)
                                if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008))
                                        log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
@@ -617,7 +617,7 @@ struct VerificPass : public Pass {
 
                log_cmd_error("Missing or unsupported mode parameter.\n");
        }
-#else /* VERIFIC_DIR */
+#else /* YOSYS_ENABLE_VERIFIC */
        virtual void execute(std::vector<std::string>, RTLIL::Design *) {
                log_cmd_error("This version of Yosys is built without Verific support.\n");
        }