riscv: print .2byte or .4byte before an unknown instruction encoding

When the RISC-V disassembler encounters an unknown instruction, it
currently just prints the value of the bytes, like this:

  Dump of assembler code for function custom_insn:
     0x00010132 <+0>:	addi	sp,sp,-16
     0x00010134 <+2>:	sw	s0,12(sp)
     0x00010136 <+4>:	addi	s0,sp,16
     0x00010138 <+6>:	0x52018b
     0x0001013c <+10>:	0x9c45

My proposal, in this patch, is to change the behaviour to this:

  Dump of assembler code for function custom_insn:
     0x00010132 <+0>:	addi	sp,sp,-16
     0x00010134 <+2>:	sw	s0,12(sp)
     0x00010136 <+4>:	addi	s0,sp,16
     0x00010138 <+6>:	.4byte	0x52018b
     0x0001013c <+10>:	.2byte	0x9c45

Adding the .4byte and .2byte opcodes.  The benefit that I see here is
that in the patched version of the tools, the disassembler output can
be fed back into the assembler and it should assemble to the same
binary format.  Before the patch, the disassembler output is invalid
assembly.

I've started a RISC-V specific test file under binutils so that I can
add a test for this change.

binutils/ChangeLog:

	* testsuite/binutils-all/riscv/riscv.exp: New file.
	* testsuite/binutils-all/riscv/unknown.d: New file.
	* testsuite/binutils-all/riscv/unknown.s: New file.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
	before an unknown instruction, '%d' is replaced with the
	instruction length.

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 858df6570baea6d46a1b1de7b82191de7136f89e..b9ac30976e4a71eb2b83c7808883119f27d34c2b 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,9 @@
+2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * testsuite/binutils-all/riscv/riscv.exp: New file.
+       * testsuite/binutils-all/riscv/unknown.d: New file.
+       * testsuite/binutils-all/riscv/unknown.s: New file.
+
 2021-09-07  Luis Machado  <luis.machado@linaro.org>
 
        Revert: [AArch64] MTE corefile support

diff --git a/binutils/testsuite/binutils-all/riscv/riscv.exp b/binutils/testsuite/binutils-all/riscv/riscv.exp
new file mode 100644 (file)
index 0000000..8f0b7dc
--- /dev/null
+++ b/binutils/testsuite/binutils-all/riscv/riscv.exp
@@ -0,0 +1,29 @@
+# Copyright (C) 2021 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+if ![istarget "riscv*-*-*"] then {
+    return
+}
+
+set tempfile tmpdir/riscvtemp.o
+set copyfile tmpdir/riscvcopy
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach t $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $t]
+    run_dump_test [file rootname $t]
+}

diff --git a/binutils/testsuite/binutils-all/riscv/unknown.d b/binutils/testsuite/binutils-all/riscv/unknown.d
new file mode 100644 (file)
index 0000000..6479116
--- /dev/null
+++ b/binutils/testsuite/binutils-all/riscv/unknown.d
@@ -0,0 +1,11 @@
+#as: -march=rv32ic
+#objdump: -d
+# Test the disassembly of unknown instruction encodings, specifically,
+# ensure that we generate a .?byte opcode.
+
+#...
+Disassembly of section \.text:
+
+[0-9a-f]+ <\.text>:
+   [0-9a-f]+:  0052018b                \.4byte 0x52018b
+   [0-9a-f]+:  9c45                    \.2byte 0x9c45

diff --git a/binutils/testsuite/binutils-all/riscv/unknown.s b/binutils/testsuite/binutils-all/riscv/unknown.s
new file mode 100644 (file)
index 0000000..df92904
--- /dev/null
+++ b/binutils/testsuite/binutils-all/riscv/unknown.s
@@ -0,0 +1,27 @@
+/* Copyright (C) 2021 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+        .text
+       /* The following instruction is in the area set aside for
+          custom instruction extensions.  As such it is unlikely that
+           an upstream extension should ever clash with this.  */
+       .insn r 0x0b, 0x0, 0x0, x3, x4, x5
+        /* Unlike the above, the following is just a reserved
+          instruction encoding.  This means that in the future an
+          extension to the compressed instruction set might use this
+          encoding.  If/when that happens we'll need to find a
+          different unused encoding within the compressed instruction
+          space.  */
+       .insn ca 0x1, 0x27, 0x2, x8, x9

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ca3206dda6d5cb7212ee8a29c1739a430f3fcb4d..a32af60864ddbeb060789c27ad65c523cfef8f19 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
+       before an unknown instruction, '%d' is replaced with the
+       instruction length.
+
 2021-09-02  Nick Clifton  <nickc@redhat.com>
 
        PR 28292

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 57198c7b6b5e1fa6b3e35e48f2359ce63166c4fd..2e28ba77e601c62b4a1bfb16d596321b236b45f2 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -570,7 +570,29 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
   /* We did not find a match, so just print the instruction bits.  */
   info->insn_type = dis_noninsn;
-  (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
+  switch (insnlen)
+    {
+    case 2:
+    case 4:
+    case 8:
+      (*info->fprintf_func) (info->stream, ".%dbyte\t0x%llx",
+                             insnlen, (unsigned long long) word);
+      break;
+    default:
+      {
+        int i;
+        (*info->fprintf_func) (info->stream, ".byte\t");
+        for (i = 0; i < insnlen; ++i)
+          {
+            if (i > 0)
+              (*info->fprintf_func) (info->stream, ", ");
+            (*info->fprintf_func) (info->stream, "0x%02x",
+                                   (unsigned int) (word & 0xff));
+            word >>= 8;
+          }
+      }
+      break;
+    }
   return insnlen;
 }