const bool m_all_instructions;
const uint32_t m_num_vnets;
+
+ public:
ProfilerStats rubyProfilerStats;
};
m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
m_mandatory_queue_latency(p.mandatory_queue_latency),
memoryPort(csprintf("%s.memory", name()), this),
- addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
+ addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
+ stats(this)
{
if (m_version == 0) {
// Combine the statistics from all controllers
void
AbstractController::init()
{
- m_delayHistogram.init(10);
+ stats.m_delayHistogram.init(10);
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
- m_delayVCHistogram.push_back(new Stats::Histogram());
- m_delayVCHistogram[i]->init(10);
+ stats.m_delayVCHistogram.push_back(new Stats::Histogram(this));
+ stats.m_delayVCHistogram[i]->init(10);
}
if (getMemReqQueue()) {
void
AbstractController::resetStats()
{
- m_delayHistogram.reset();
+ stats.m_delayHistogram.reset();
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
- m_delayVCHistogram[i]->reset();
+ stats.m_delayVCHistogram[i]->reset();
}
}
AbstractController::regStats()
{
ClockedObject::regStats();
-
- m_fully_busy_cycles
- .name(name() + ".fully_busy_cycles")
- .desc("cycles for which number of transistions == max transitions")
- .flags(Stats::nozero);
}
void
AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
{
- assert(virtualNetwork < m_delayVCHistogram.size());
- m_delayHistogram.sample(delay);
- m_delayVCHistogram[virtualNetwork]->sample(delay);
+ assert(virtualNetwork < stats.m_delayVCHistogram.size());
+ stats.m_delayHistogram.sample(delay);
+ stats.m_delayVCHistogram[virtualNetwork]->sample(delay);
}
void
: RequestPort(_name, _controller, id), controller(_controller)
{
}
+
+AbstractController::
+ControllerStats::ControllerStats(Stats::Group *parent)
+ : Stats::Group(parent),
+ m_fully_busy_cycles(this, "fully_busy_cycles",
+ "cycles for which number of transistions == max "
+ "transitions"),
+ m_delayHistogram(this, "delay_histogram")
+{
+ m_fully_busy_cycles
+ .flags(Stats::nozero);
+ m_delayHistogram
+ .flags(Stats::nozero);
+}
MachineID getMachineID() const { return m_machineID; }
RequestorID getRequestorId() const { return m_id; }
- Stats::Histogram& getDelayHist() { return m_delayHistogram; }
+ Stats::Histogram& getDelayHist() { return stats.m_delayHistogram; }
Stats::Histogram& getDelayVCHist(uint32_t index)
- { return *(m_delayVCHistogram[index]); }
+ { return *(stats.m_delayVCHistogram[index]); }
bool respondsTo(Addr addr)
{
std::unordered_map<Addr, TransMapPair> m_inTrans;
std::unordered_map<Addr, TransMapPair> m_outTrans;
- // Initialized by the SLICC compiler for all combinations of event and
- // states. Only histograms with samples will appear in the stats
- std::vector<std::vector<std::vector<Stats::Histogram*>>> m_inTransLatHist;
-
- // Initialized by the SLICC compiler for all events.
- // Only histograms with samples will appear in the stats.
- std::vector<Stats::Histogram*> m_outTransLatHist;
-
/**
* Profiles an event that initiates a protocol transactions for a specific
* line (e.g. events triggered by incoming request messages).
{
auto iter = m_inTrans.find(addr);
assert(iter != m_inTrans.end());
- m_inTransLatHist[iter->second.transaction]
- [iter->second.state]
- [(unsigned)finalState]->sample(
- ticksToCycles(curTick() - iter->second.time));
+ stats.m_inTransLatHist[iter->second.transaction]
+ [iter->second.state]
+ [(unsigned)finalState]->sample(
+ ticksToCycles(curTick() - iter->second.time));
m_inTrans.erase(iter);
}
{
auto iter = m_outTrans.find(addr);
assert(iter != m_outTrans.end());
- m_outTransLatHist[iter->second.transaction]->sample(
+ stats.m_outTransLatHist[iter->second.transaction]->sample(
ticksToCycles(curTick() - iter->second.time));
m_outTrans.erase(iter);
}
Cycles m_recycle_latency;
const Cycles m_mandatory_queue_latency;
- //! Counter for the number of cycles when the transitions carried out
- //! were equal to the maximum allowed
- Stats::Scalar m_fully_busy_cycles;
-
- //! Histogram for profiling delay for the messages this controller
- //! cares for
- Stats::Histogram m_delayHistogram;
- std::vector<Stats::Histogram *> m_delayVCHistogram;
-
/**
* Port that forwards requests and receives responses from the
* memory controller.
NetDest downstreamDestinations;
+ public:
+ struct ControllerStats : public Stats::Group
+ {
+ ControllerStats(Stats::Group *parent);
+
+ // Initialized by the SLICC compiler for all combinations of event and
+ // states. Only histograms with samples will appear in the stats
+ std::vector<std::vector<std::vector<Stats::Histogram*>>>
+ m_inTransLatHist;
+
+ // Initialized by the SLICC compiler for all events.
+ // Only histograms with samples will appear in the stats.
+ std::vector<Stats::Histogram*> m_outTransLatHist;
+
+ //! Counter for the number of cycles when the transitions carried out
+ //! were equal to the maximum allowed
+ Stats::Scalar m_fully_busy_cycles;
+
+ //! Histogram for profiling delay for the messages this controller
+ //! cares for
+ Stats::Histogram m_delayHistogram;
+ std::vector<Stats::Histogram *> m_delayVCHistogram;
+ } stats;
+
};
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
{
AbstractController::regStats();
+ // For each type of controllers, one controller of that type is picked
+ // to aggregate stats of all controllers of that type.
if (m_version == 0) {
+
+ Profiler *profiler = params().ruby_system->getProfiler();
+ Stats::Group *profilerStatsPtr = &profiler->rubyProfilerStats;
+
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
- Stats::Vector *t = new Stats::Vector();
+ std::string stat_name =
+ "${c_ident}." + ${ident}_Event_to_string(event);
+ Stats::Vector *t =
+ new Stats::Vector(profilerStatsPtr, stat_name.c_str());
t->init(m_num_controllers);
- t->name(params().ruby_system->name() + ".${c_ident}." +
- ${ident}_Event_to_string(event));
t->flags(Stats::pdf | Stats::total | Stats::oneline |
Stats::nozero);
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
-
- Stats::Vector *t = new Stats::Vector();
+ std::string stat_name = "${c_ident}." +
+ ${ident}_State_to_string(state) +
+ "." + ${ident}_Event_to_string(event);
+ Stats::Vector *t =
+ new Stats::Vector(profilerStatsPtr, stat_name.c_str());
t->init(m_num_controllers);
- t->name(params().ruby_system->name() + ".${c_ident}." +
- ${ident}_State_to_string(state) +
- "." + ${ident}_Event_to_string(event));
-
t->flags(Stats::pdf | Stats::total | Stats::oneline |
Stats::nozero);
transVec[state].push_back(t);
}
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
- Stats::Histogram* t = new Stats::Histogram;
- m_outTransLatHist.push_back(t);
+ std::string stat_name =
+ "outTransLatHist." + ${ident}_Event_to_string(event);
+ Stats::Histogram* t = new Stats::Histogram(&stats, stat_name.c_str());
+ stats.m_outTransLatHist.push_back(t);
t->init(5);
- t->name(name() + ".outTransLatHist." +
- ${ident}_Event_to_string(event));
t->flags(Stats::pdf | Stats::total |
Stats::oneline | Stats::nozero);
}
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
- m_inTransLatHist.emplace_back();
+ stats.m_inTransLatHist.emplace_back();
for (${ident}_State initial_state = ${ident}_State_FIRST;
initial_state < ${ident}_State_NUM; ++initial_state) {
- m_inTransLatHist.back().emplace_back();
+ stats.m_inTransLatHist.back().emplace_back();
for (${ident}_State final_state = ${ident}_State_FIRST;
final_state < ${ident}_State_NUM; ++final_state) {
- Stats::Histogram* t = new Stats::Histogram;
- m_inTransLatHist.back().back().push_back(t);
+ std::string stat_name = "inTransLatHist." +
+ ${ident}_Event_to_string(event) + "." +
+ ${ident}_State_to_string(initial_state) + "." +
+ ${ident}_State_to_string(final_state);
+ Stats::Histogram* t =
+ new Stats::Histogram(&stats, stat_name.c_str());
+ stats.m_inTransLatHist.back().back().push_back(t);
t->init(5);
- t->name(name() + ".inTransLatHist." +
- ${ident}_Event_to_string(event) + "." +
- ${ident}_State_to_string(initial_state) + "." +
- ${ident}_State_to_string(final_state));
t->flags(Stats::pdf | Stats::total |
Stats::oneline | Stats::nozero);
}
assert(counter <= m_transitions_per_cycle);
if (counter == m_transitions_per_cycle) {
// Count how often we are fully utilized
- m_fully_busy_cycles++;
+ stats.m_fully_busy_cycles++;
// Wakeup in another cycle and try again
scheduleEvent(Cycles(1));
projects / gem5.git / commitdiff