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radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use
authorVincent Lejeune <vljn@ovi.com>
Tue, 4 Sep 2012 14:49:25 +0000 (16:49 +0200)
committerVincent Lejeune <vljn@ovi.com>
Tue, 4 Sep 2012 15:44:48 +0000 (17:44 +0200)
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
src/gallium/drivers/radeon/AMDGPUInstrInfo.h patch | blob | history
src/gallium/drivers/radeon/R600ISelLowering.cpp patch | blob | history

diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
index 264311962bae2c7026a129e7d006f8923c014ba7..a30807678836aca9f56dc63a6a52f685a254be17 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
@@ -25,8 +25,8 @@
 #define GET_INSTRINFO_ENUM
 #include "AMDGPUGenInstrInfo.inc"
 
-#define OPCODE_IS_ZERO_INT 0x00000045
-#define OPCODE_IS_NOT_ZERO_INT 0x00000042
+#define OPCODE_IS_ZERO_INT 0x00000042
+#define OPCODE_IS_NOT_ZERO_INT 0x00000045
 #define OPCODE_IS_ZERO 0x00000020
 #define OPCODE_IS_NOT_ZERO 0x00000023
 
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index fec9d4e257c256b0eb552ee00982d7688bcf967f..7c939354318b041ed418504f7769841896d55720 100644 (file)
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -207,7 +207,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
                 .addReg(AMDGPU::PREDICATE_BIT)
                 .addOperand(MI->getOperand(1))
-                .addImm(OPCODE_IS_ZERO)
+                .addImm(OPCODE_IS_NOT_ZERO)
                 .addImm(0); // Flags
       TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
       BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
@@ -221,7 +221,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
               .addReg(AMDGPU::PREDICATE_BIT)
               .addOperand(MI->getOperand(1))
-              .addImm(OPCODE_IS_ZERO_INT)
+              .addImm(OPCODE_IS_NOT_ZERO_INT)
               .addImm(0); // Flags
       TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
       BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))