tests: Removed 40.perlbmk tests
authorBobby R. Bruce <bbruce@ucdavis.edu>
Tue, 14 Jan 2020 20:18:36 +0000 (12:18 -0800)
committerBobby R. Bruce <bbruce@ucdavis.edu>
Fri, 24 Jan 2020 05:48:14 +0000 (05:48 +0000)
In an effort to cleanup the old tests, and migrate useful tests to be
executed via `test/main.py`, it has been decided that the
`test/long/se/40.perlbmk` tests should be removed.

Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: I3c7ea79717c90acf0656f30b878eb3f9f33fdb70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24403
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
17 files changed:
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout [deleted file]
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt [deleted file]
tests/long/se/40.perlbmk/test.py [deleted file]

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
deleted file mode 100644 (file)
index bcc7e80..0000000
+++ /dev/null
@@ -1,997 +0,0 @@
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-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib mdred.makerand.pl
-cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr
deleted file mode 100755 (executable)
index c1f3592..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: fcntl64(3, 2) passed through to host
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
deleted file mode 100755 (executable)
index 2e501ad..0000000
+++ /dev/null
@@ -1,653 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 21:05:24
-gem5 executing on e108600-lin, pid 17596
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/minor-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
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-344000: 124118372
-343000: 2046377904
-342000: 1395427716
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-339000: 2291884417
-338000: 351940574
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-335000: 371500747
-334000: 969922131
-333000: 240854580
-332000: 1644465214
-331000: 1539846168
-330000: 940087216
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-328000: 2281687201
-327000: 3030170550
-326000: 3648503863
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-322000: 2334905107
-321000: 1597704047
-320000: 302297707
-319000: 3209203690
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-317000: 2868907580
-316000: 2808087076
-315000: 4034586233
-314000: 3694191694
-313000: 2001671958
-312000: 559582279
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-307000: 2446376687
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-302000: 971356234
-301000: 481382543
-300000: 2647080988
-299000: 4065744916
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-296000: 485492098
-295000: 217516816
-294000: 4050820137
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-292000: 1686691079
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-290000: 3746020838
-289000: 1641967381
-288000: 3492475215
-287000: 3154885393
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-285000: 3589739293
-284000: 3558041700
-283000: 4130142319
-282000: 3132446063
-281000: 982677436
-280000: 799322395
-279000: 151715214
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-277000: 1712470933
-276000: 3807622752
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-272000: 1131025394
-271000: 1375475855
-270000: 553294237
-269000: 4091487177
-268000: 2841855980
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-266000: 454385594
-265000: 3757482634
-264000: 3856197465
-263000: 1084605457
-262000: 2552759023
-261000: 3786548799
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-258000: 76233700
-257000: 476168167
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-254000: 1240074303
-253000: 1771564446
-252000: 710374418
-251000: 821383716
-250000: 3157726088
-249000: 3083379502
-248000: 2563632690
-247000: 33723341
-246000: 3303336748
-245000: 4110677892
-244000: 3811702913
-243000: 53856215
-242000: 243571468
-241000: 52177779
-240000: 46805590
-239000: 1622010618
-238000: 1321640849
-237000: 3106837291
-236000: 4102944642
-235000: 137904396
-234000: 339510135
-233000: 88415957
-232000: 3157666382
-231000: 2571005912
-230000: 3586247649
-229000: 4172761781
-228000: 2463305780
-227000: 956927307
-226000: 2169861547
-225000: 1751989251
-224000: 673059158
-223000: 2782464516
-222000: 3741392140
-221000: 2856154963
-220000: 3778376854
-219000: 1538476717
-218000: 2879698522
-217000: 3734645735
-216000: 1899042577
-215000: 371356008
-214000: 2416663698
-213000: 1595919347
-212000: 2816045438
-211000: 132438808
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-209000: 834913667
-208000: 2707567283
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-206000: 3696516104
-205000: 1427952551
-204000: 280496321
-203000: 1185678745
-202000: 3461951699
-201000: 1369208434
-200000: 3900136261
-199000: 870818876
-198000: 327248310
-197000: 3116959470
-196000: 1544241188
-195000: 1568248814
-194000: 2978831302
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-190000: 3878512103
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-188000: 1873588815
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-184000: 1568401301
-183000: 525792402
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-179000: 4172125462
-178000: 2108738993
-177000: 2084782857
-176000: 3956924509
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-173000: 458250029
-172000: 2635215219
-171000: 1801029767
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-169000: 370704281
-168000: 177963345
-167000: 924067814
-166000: 3577678376
-165000: 3717789117
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-162000: 3172510171
-161000: 417992786
-160000: 2591600214
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-155000: 2246563682
-154000: 2304045306
-153000: 2647353543
-152000: 2043381015
-151000: 3952056867
-150000: 2644058641
-149000: 3477151018
-148000: 1740210241
-147000: 3314851112
-146000: 1604832482
-145000: 2572410736
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-143000: 889666293
-142000: 1024747903
-141000: 226685285
-140000: 3149168519
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-137000: 1417402331
-136000: 422304488
-135000: 2595894054
-134000: 4266597695
-133000: 1116326556
-132000: 3537080833
-131000: 2181246909
-130000: 1241997223
-129000: 628191304
-128000: 3074132403
-127000: 2112958836
-126000: 1371260930
-125000: 2272975771
-124000: 1379085607
-123000: 1998991877
-122000: 2760271255
-121000: 3784187756
-120000: 311188417
-119000: 1123593459
-118000: 1249155194
-117000: 908703020
-116000: 3765244393
-115000: 3040869794
-114000: 437536659
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-111000: 1263143640
-110000: 1384687523
-109000: 1727931349
-108000: 2861733388
-107000: 963829093
-106000: 431354627
-105000: 3568623360
-104000: 2957399361
-103000: 1071045618
-102000: 3968457714
-101000: 3448338394
-100000: 2586060251
-99000: 3401651822
-98000: 1579089478
-97000: 3722618916
-96000: 759319595
-95000: 1269278712
-94000: 150489448
-93000: 390013662
-92000: 3663029784
-91000: 555197170
-90000: 166476858
-89000: 1658807720
-88000: 3430520531
-87000: 2946861093
-86000: 3000600326
-85000: 300034452
-84000: 2813719249
-83000: 3009927425
-82000: 1127728469
-81000: 2667791855
-80000: 2632316050
-79000: 2180301200
-78000: 418999983
-77000: 4254858933
-76000: 2728734498
-75000: 1863202698
-74000: 4226419921
-73000: 1917572494
-72000: 3117082625
-71000: 1032601538
-70000: 2992135524
-69000: 670119660
-68000: 638731522
-67000: 1460114012
-66000: 1232274665
-65000: 3667669961
-64000: 191277965
-63000: 3868442802
-62000: 700664540
-61000: 2271087482
-60000: 3274078227
-59000: 159900296
-58000: 2778747772
-57000: 2788477153
-56000: 3965957780
-55000: 2276993918
-54000: 1986966104
-53000: 3416414682
-52000: 2162594060
-51000: 2947744069
-50000: 4024793290
-49000: 631161701
-48000: 728285173
-47000: 1487641693
-46000: 4049519424
-45000: 613160608
-44000: 1566126172
-43000: 3731725133
-42000: 2746368727
-41000: 4168967735
-40000: 1319649932
-39000: 2964978784
-38000: 967937134
-37000: 3116555742
-36000: 2279790642
-35000: 2852914953
-34000: 1040410911
-33000: 226200467
-32000: 1765748697
-31000: 1418838964
-30000: 1362983292
-29000: 2877029789
-28000: 583076938
-27000: 2797138728
-26000: 3033567067
-25000: 3902265889
-24000: 3287868661
-23000: 2411740885
-22000: 2747756860
-21000: 1889759908
-20000: 2975722149
-19000: 3027693370
-18000: 2418258302
-17000: 490864179
-16000: 1944489573
-15000: 4212838860
-14000: 1782397962
-13000: 1981080238
-12000: 1213651424
-11000: 1407527546
-10000: 661520991
-9000: 143129551
-8000: 3293448370
-7000: 764314400
-6000: 2246553770
-5000: 2459308892
-4000: 3776833152
-3000: 2208260083
-2000: 2845746745
-1000: 2068042552
-0: 290958364
-Exiting @ tick 525654485500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
deleted file mode 100644 (file)
index 98887b4..0000000
+++ /dev/null
@@ -1,943 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.525648                       # Number of seconds simulated
-sim_ticks                                525647850500                       # Number of ticks simulated
-final_tick                               525647850500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 304424                       # Simulator instruction rate (inst/s)
-host_op_rate                                   374786                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              249775392                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 281156                       # Number of bytes of host memory used
-host_seconds                                  2104.48                       # Real time elapsed on the host
-sim_insts                                   640655085                       # Number of instructions simulated
-sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            164544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18474496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18639040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       164544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          164544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2571                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288664                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291235                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               313031                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             35146146                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                35459177                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          313031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             313031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           8047730                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                8047730                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           8047730                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              313031                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            35146146                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               43506907                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291235                       # Number of read requests accepted
-system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      291235                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18619136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228224                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18639040                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18288                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18134                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18217                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18185                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18292                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18424                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18179                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17990                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18031                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18051                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18108                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18204                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18211                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18269                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18079                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18262                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    525647749500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291235                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290544                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       368                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      890                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       102644                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      222.570282                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     147.559533                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     262.016403                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          36015     35.09%     35.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        41909     40.83%     75.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13148     12.81%     88.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1006      0.98%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          491      0.48%     90.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1034      1.01%     91.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          399      0.39%     91.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          481      0.47%     92.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8161      7.95%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         102644                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.515182                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.167653                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.604541                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4016     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4018                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.442509                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.422441                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.830286                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3129     77.87%     77.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                889     22.13%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4018                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15528676000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               20983501000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1454620000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       53377.09                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  72127.09                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          35.42                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           8.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       35.46                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        8.05                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.34                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.28                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        28.92                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202546                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51789                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.62                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.35                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1471030.52                       # Average gap between requests
-system.physmem.pageHitRate                      71.24                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  366410520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  194736630                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1040362260                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                173638080                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           28886236080.000008                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             8300918550                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             1634993280                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy       57345491820                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy       51305938080                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy        64928910000                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             214198815120                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              407.494892                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           503139346250                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE     3209706000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12289528000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   243772297750                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 133609273250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      7009209500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 125757836000                       # Time in different power states
-system.physmem_1.actEnergy                  366546180                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  194797350                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1036835100                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                171226440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           28725815040.000008                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             8187694890                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             1628706720                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy       56919000150                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy       51113801760                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy        65311053315                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             213675530385                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              406.499389                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           503405920500                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE     3197022000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12221338000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   245475081750                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 133108808000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      6823284750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 124822316000                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               147257105                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98226689                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1384794                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             89640439                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                63297158                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.612280                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19276056                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1321                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups        15995188                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits           15989428                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses             5760                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted      1280093                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.numSyscalls                   673                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1051295701                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   640655085                       # Number of instructions committed
-system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       8620171                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.640970                       # CPI: cycles per instruction
-system.cpu.ipc                               0.609396                       # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu               385757467     48.91%     48.91% # Class of committed instruction
-system.cpu.op_class_0::IntMult                5173441      0.66%     49.56% # Class of committed instruction
-system.cpu.op_class_0::IntDiv                       0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd                     0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp                     0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt                     0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatMult                    0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc                 0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv                     0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc                    0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt                    0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd                      0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc                   0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu                      0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp                      0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt                      0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc                     0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdMult                     0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc                  0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdShift                    0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt                     0      0.00%     49.56% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd            637528      0.08%     49.65% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     49.65% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp           3187668      0.40%     50.05% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt           2550131      0.32%     50.37% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     50.37% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc         10203074      1.29%     51.67% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     51.67% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     51.67% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     51.67% # Class of committed instruction
-system.cpu.op_class_0::MemRead              245222568     31.09%     82.76% # Class of committed instruction
-system.cpu.op_class_0::MemWrite             125149823     15.87%     98.62% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead           7018370      0.89%     99.51% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite          3830674      0.49%    100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total                788730744                       # Class of committed instruction
-system.cpu.tickCycles                       955914808                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        95380893                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            778100                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.107040                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378447440                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782196                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.826867                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         850680500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.107040                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999050                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999050                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          969                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1388                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1537                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759379166                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759379166                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    249618713                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249618713                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3484                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          3484                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     378432478                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378432478                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    378435962                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378435962                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       713192                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        713192                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       850904                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         850904                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       851045                       # number of overall misses
-system.cpu.dcache.overall_misses::total        851045                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  37264745000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  37264745000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10940214000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10940214000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  48204959000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  48204959000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  48204959000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  48204959000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250331905                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250331905                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3625                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3625                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    379283382                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379283382                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    379287007                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379287007                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002849                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002849                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038897                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.038897                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002243                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002243                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002244                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002244                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56651.465970                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 56642.080031                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks        88684                       # number of writebacks
-system.cpu.dcache.writebacks::total             88684                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          457                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          457                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        68847                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68847                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        68847                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68847                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712735                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712735                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       782057                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782057                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       782196                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782196                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  36543095500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  36543095500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5486426000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5486426000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1802000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1802000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  42029521500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  42029521500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  42031323500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  42031323500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038345                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038345                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements             24889                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1710.890314                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           257795451                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             26639                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           9677.369684                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1710.890314                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.835396                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.835396                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1750                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1598                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.854492                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         515670821                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        515670821                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    257795451                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       257795451                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     257795451                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        257795451                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    257795451                       # number of overall hits
-system.cpu.icache.overall_hits::total       257795451                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        26640                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         26640                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        26640                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          26640                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        26640                       # number of overall misses
-system.cpu.icache.overall_misses::total         26640                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    538801500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    538801500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    538801500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    538801500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    538801500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    538801500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    257822091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    257822091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    257822091                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    257822091                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    257822091                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    257822091                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000103                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000103                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000103                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000103                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000103                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000103                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20225.281532                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20225.281532                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20225.281532                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20225.281532                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20225.281532                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20225.281532                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks        24889                       # number of writebacks
-system.cpu.icache.writebacks::total             24889                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        26640                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        26640                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        26640                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        26640                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        26640                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        26640                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    512162500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    512162500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    512162500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    512162500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    512162500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    512162500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000103                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000103                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000103                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19225.319069                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19225.319069                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19225.319069                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19225.319069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19225.319069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19225.319069                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           258839                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32651.545544                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1316953                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291607                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.516191                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       3958663000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    40.523746                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    90.271478                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.750321                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.001237                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002755                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.992455                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996446                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2912                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29227                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13160335                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13160335                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks        88684                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        88684                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        23557                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        23557                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        24064                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        24064                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490275                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       490275                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        24064                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       493506                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          517570                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        24064                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       493506                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         517570                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66091                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66091                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2576                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2576                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222599                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222599                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2576                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       288690                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        291266                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2576                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       288690                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       291266                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5348515000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5348515000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    218253000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    218253000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  30325726000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  30325726000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    218253000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  35674241000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  35892494000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    218253000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  35674241000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  35892494000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        88684                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        88684                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        23557                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        23557                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        26640                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        26640                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712874                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       712874                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        26640                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       782196                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       808836                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        26640                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       782196                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       808836                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.096697                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.096697                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312256                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312256                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.096697                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.369076                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.360105                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.096697                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.369076                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.360105                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80926.525548                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80926.525548                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.543478                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 123229.261225                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 123229.261225                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            4                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           26                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           26                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           26                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           30                       # number of overall MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2572                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2572                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222573                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222573                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2572                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288664                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       291236                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2572                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288664                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       291236                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4687605000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4687605000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    192261000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    192261000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  28098015500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  28098015500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    192261000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  32785620500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  32977881500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    192261000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  32785620500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  32977881500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.096547                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096547                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312219                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312219                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.096547                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.369043                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.360068                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096547                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.369043                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.360068                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      1611825                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       803048                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3234                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2033                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2018                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp        739513                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       154782                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        24889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       882157                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        26640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       712874                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        78168                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2342492                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2420660                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3297792                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55736320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           59034112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      258839                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4230272                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      1067675                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.005002                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.070750                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1062349     99.50%     99.50% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5311      0.50%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                 15      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1067675                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      919485500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      39960496                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1173306974                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests        548040                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       256844                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 525647850500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp             225144                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190707                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225144                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839275                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 839275                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22869312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22869312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            291235                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  291235    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              291235                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           917214500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1553534250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
deleted file mode 100644 (file)
index 721f1a5..0000000
+++ /dev/null
@@ -1,962 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=16
-LSQCheckLoads=true
-LSQDepCheckShift=0
-SQEntries=16
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=2
-decodeWidth=3
-default_p_state=UNDEFINED
-dispatchWidth=6
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=16
-fetchQueueSize=32
-fetchToDecodeDelay=3
-fetchTrapLatency=1
-fetchWidth=3
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=32
-numPhysCCRegs=640
-numPhysFloatRegs=192
-numPhysIntRegs=128
-numROBEntries=40
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=1
-renameToROBDelay=1
-renameWidth=3
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BiModeBP
-BTBEntries=2048
-BTBTagSize=18
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1 opList2
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList1.opList2]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
-
-[system.cpu.fuPool.FUList4.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=9
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList20]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList21]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList22]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList23]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=9
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList24]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=33
-pipelined=false
-
-[system.cpu.fuPool.FUList4.opList25]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList26]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList27]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=perlbmk -I. -I lib mdred.makerand.pl
-cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
deleted file mode 100755 (executable)
index a0d2c5e..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-warn: fcntl64(3, 2) passed through to host
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
deleted file mode 100755 (executable)
index 6aa2449..0000000
+++ /dev/null
@@ -1,650 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 04:18:56
-gem5 started Apr  3 2017 04:19:11
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 3566
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-637000: 2581848540
-636000: 4117852332
-635000: 329081094
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-0: 290958364
-Exiting @ tick 339069355000 because exiting with last active thread context
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
deleted file mode 100644 (file)
index 51dd3b6..0000000
+++ /dev/null
@@ -1,1286 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.339069                      
-sim_ticks                                339069355000                      
-final_tick                               339069355000                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 210410                      
-host_op_rate                                   259043                      
-host_tick_rate                              111361442                      
-host_mem_usage                                 288088                      
-host_seconds                                  3044.76                      
-sim_insts                                   640649299                      
-sim_ops                                     788724958                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 339069355000                      
-system.physmem.bytes_read::cpu.inst            272000                      
-system.physmem.bytes_read::cpu.data          48065856                      
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12979392                      
-system.physmem.bytes_read::total             61317248                      
-system.physmem.bytes_inst_read::cpu.inst       272000                      
-system.physmem.bytes_inst_read::total          272000                      
-system.physmem.bytes_written::writebacks      4246400                      
-system.physmem.bytes_written::total           4246400                      
-system.physmem.num_reads::cpu.inst               4250                      
-system.physmem.num_reads::cpu.data             751029                      
-system.physmem.num_reads::cpu.l2cache.prefetcher       202803                      
-system.physmem.num_reads::total                958082                      
-system.physmem.num_writes::writebacks           66350                      
-system.physmem.num_writes::total                66350                      
-system.physmem.bw_read::cpu.inst               802196                      
-system.physmem.bw_read::cpu.data            141758184                      
-system.physmem.bw_read::cpu.l2cache.prefetcher     38279461                      
-system.physmem.bw_read::total               180839840                      
-system.physmem.bw_inst_read::cpu.inst          802196                      
-system.physmem.bw_inst_read::total             802196                      
-system.physmem.bw_write::writebacks          12523692                      
-system.physmem.bw_write::total               12523692                      
-system.physmem.bw_total::writebacks          12523692                      
-system.physmem.bw_total::cpu.inst              802196                      
-system.physmem.bw_total::cpu.data           141758184                      
-system.physmem.bw_total::cpu.l2cache.prefetcher     38279461                      
-system.physmem.bw_total::total              193363532                      
-system.physmem.readReqs                        958083                      
-system.physmem.writeReqs                        66350                      
-system.physmem.readBursts                      958083                      
-system.physmem.writeBursts                      66350                      
-system.physmem.bytesReadDRAM                 61296960                      
-system.physmem.bytesReadWrQ                     20352                      
-system.physmem.bytesWritten                   4240000                      
-system.physmem.bytesReadSys                  61317312                      
-system.physmem.bytesWrittenSys                4246400                      
-system.physmem.servicedByWrQ                      318                      
-system.physmem.mergedWrBursts                      71                      
-system.physmem.neitherReadNorWriteReqs              0                      
-system.physmem.perBankRdBursts::0               19910                      
-system.physmem.perBankRdBursts::1               19573                      
-system.physmem.perBankRdBursts::2              657828                      
-system.physmem.perBankRdBursts::3               21032                      
-system.physmem.perBankRdBursts::4               19718                      
-system.physmem.perBankRdBursts::5               21045                      
-system.physmem.perBankRdBursts::6               19700                      
-system.physmem.perBankRdBursts::7               20038                      
-system.physmem.perBankRdBursts::8               19491                      
-system.physmem.perBankRdBursts::9               20101                      
-system.physmem.perBankRdBursts::10              19540                      
-system.physmem.perBankRdBursts::11              19692                      
-system.physmem.perBankRdBursts::12              19618                      
-system.physmem.perBankRdBursts::13              21105                      
-system.physmem.perBankRdBursts::14              19493                      
-system.physmem.perBankRdBursts::15              19881                      
-system.physmem.perBankWrBursts::0                4272                      
-system.physmem.perBankWrBursts::1                4107                      
-system.physmem.perBankWrBursts::2                4147                      
-system.physmem.perBankWrBursts::3                4153                      
-system.physmem.perBankWrBursts::4                4251                      
-system.physmem.perBankWrBursts::5                4229                      
-system.physmem.perBankWrBursts::6                4174                      
-system.physmem.perBankWrBursts::7                4096                      
-system.physmem.perBankWrBursts::8                4096                      
-system.physmem.perBankWrBursts::9                4095                      
-system.physmem.perBankWrBursts::10               4095                      
-system.physmem.perBankWrBursts::11               4097                      
-system.physmem.perBankWrBursts::12               4098                      
-system.physmem.perBankWrBursts::13               4094                      
-system.physmem.perBankWrBursts::14               4095                      
-system.physmem.perBankWrBursts::15               4151                      
-system.physmem.numRdRetry                           0                      
-system.physmem.numWrRetry                           0                      
-system.physmem.totGap                    339069344500                      
-system.physmem.readPktSize::0                       0                      
-system.physmem.readPktSize::1                       0                      
-system.physmem.readPktSize::2                       0                      
-system.physmem.readPktSize::3                       0                      
-system.physmem.readPktSize::4                       0                      
-system.physmem.readPktSize::5                       0                      
-system.physmem.readPktSize::6                  958083                      
-system.physmem.writePktSize::0                      0                      
-system.physmem.writePktSize::1                      0                      
-system.physmem.writePktSize::2                      0                      
-system.physmem.writePktSize::3                      0                      
-system.physmem.writePktSize::4                      0                      
-system.physmem.writePktSize::5                      0                      
-system.physmem.writePktSize::6                  66350                      
-system.physmem.rdQLenPdf::0                    765133                      
-system.physmem.rdQLenPdf::1                    120601                      
-system.physmem.rdQLenPdf::2                     15570                      
-system.physmem.rdQLenPdf::3                      6690                      
-system.physmem.rdQLenPdf::4                      6457                      
-system.physmem.rdQLenPdf::5                      7738                      
-system.physmem.rdQLenPdf::6                      9158                      
-system.physmem.rdQLenPdf::7                     10207                      
-system.physmem.rdQLenPdf::8                      6741                      
-system.physmem.rdQLenPdf::9                      3672                      
-system.physmem.rdQLenPdf::10                     2435                      
-system.physmem.rdQLenPdf::11                     1581                      
-system.physmem.rdQLenPdf::12                     1116                      
-system.physmem.rdQLenPdf::13                      666                      
-system.physmem.rdQLenPdf::14                        0                      
-system.physmem.rdQLenPdf::15                        0                      
-system.physmem.rdQLenPdf::16                        0                      
-system.physmem.rdQLenPdf::17                        0                      
-system.physmem.rdQLenPdf::18                        0                      
-system.physmem.rdQLenPdf::19                        0                      
-system.physmem.rdQLenPdf::20                        0                      
-system.physmem.rdQLenPdf::21                        0                      
-system.physmem.rdQLenPdf::22                        0                      
-system.physmem.rdQLenPdf::23                        0                      
-system.physmem.rdQLenPdf::24                        0                      
-system.physmem.rdQLenPdf::25                        0                      
-system.physmem.rdQLenPdf::26                        0                      
-system.physmem.rdQLenPdf::27                        0                      
-system.physmem.rdQLenPdf::28                        0                      
-system.physmem.rdQLenPdf::29                        0                      
-system.physmem.rdQLenPdf::30                        0                      
-system.physmem.rdQLenPdf::31                        0                      
-system.physmem.wrQLenPdf::0                         1                      
-system.physmem.wrQLenPdf::1                         1                      
-system.physmem.wrQLenPdf::2                         1                      
-system.physmem.wrQLenPdf::3                         1                      
-system.physmem.wrQLenPdf::4                         1                      
-system.physmem.wrQLenPdf::5                         1                      
-system.physmem.wrQLenPdf::6                         1                      
-system.physmem.wrQLenPdf::7                         1                      
-system.physmem.wrQLenPdf::8                         1                      
-system.physmem.wrQLenPdf::9                         1                      
-system.physmem.wrQLenPdf::10                        1                      
-system.physmem.wrQLenPdf::11                        1                      
-system.physmem.wrQLenPdf::12                        1                      
-system.physmem.wrQLenPdf::13                        1                      
-system.physmem.wrQLenPdf::14                        1                      
-system.physmem.wrQLenPdf::15                      511                      
-system.physmem.wrQLenPdf::16                      556                      
-system.physmem.wrQLenPdf::17                      857                      
-system.physmem.wrQLenPdf::18                     1405                      
-system.physmem.wrQLenPdf::19                     2061                      
-system.physmem.wrQLenPdf::20                     2611                      
-system.physmem.wrQLenPdf::21                     3025                      
-system.physmem.wrQLenPdf::22                     3538                      
-system.physmem.wrQLenPdf::23                     4041                      
-system.physmem.wrQLenPdf::24                     4482                      
-system.physmem.wrQLenPdf::25                     4954                      
-system.physmem.wrQLenPdf::26                     5339                      
-system.physmem.wrQLenPdf::27                     5747                      
-system.physmem.wrQLenPdf::28                     6156                      
-system.physmem.wrQLenPdf::29                     6357                      
-system.physmem.wrQLenPdf::30                     4787                      
-system.physmem.wrQLenPdf::31                     4236                      
-system.physmem.wrQLenPdf::32                     4138                      
-system.physmem.wrQLenPdf::33                      191                      
-system.physmem.wrQLenPdf::34                      168                      
-system.physmem.wrQLenPdf::35                      135                      
-system.physmem.wrQLenPdf::36                      120                      
-system.physmem.wrQLenPdf::37                      116                      
-system.physmem.wrQLenPdf::38                       89                      
-system.physmem.wrQLenPdf::39                       84                      
-system.physmem.wrQLenPdf::40                       75                      
-system.physmem.wrQLenPdf::41                       73                      
-system.physmem.wrQLenPdf::42                       60                      
-system.physmem.wrQLenPdf::43                       58                      
-system.physmem.wrQLenPdf::44                       51                      
-system.physmem.wrQLenPdf::45                       45                      
-system.physmem.wrQLenPdf::46                       44                      
-system.physmem.wrQLenPdf::47                       32                      
-system.physmem.wrQLenPdf::48                       26                      
-system.physmem.wrQLenPdf::49                       29                      
-system.physmem.wrQLenPdf::50                       22                      
-system.physmem.wrQLenPdf::51                       15                      
-system.physmem.wrQLenPdf::52                       12                      
-system.physmem.wrQLenPdf::53                       10                      
-system.physmem.wrQLenPdf::54                        6                      
-system.physmem.wrQLenPdf::55                        1                      
-system.physmem.wrQLenPdf::56                        1                      
-system.physmem.wrQLenPdf::57                        0                      
-system.physmem.wrQLenPdf::58                        0                      
-system.physmem.wrQLenPdf::59                        0                      
-system.physmem.wrQLenPdf::60                        0                      
-system.physmem.wrQLenPdf::61                        0                      
-system.physmem.wrQLenPdf::62                        0                      
-system.physmem.wrQLenPdf::63                        0                      
-system.physmem.bytesPerActivate::samples       196319                      
-system.physmem.bytesPerActivate::mean      333.816859                      
-system.physmem.bytesPerActivate::gmean     191.183939                      
-system.physmem.bytesPerActivate::stdev     355.380336                      
-system.physmem.bytesPerActivate::0-127          65406     33.32%     33.32%
-system.physmem.bytesPerActivate::128-255        61086     31.12%     64.43%
-system.physmem.bytesPerActivate::256-383        15476      7.88%     72.31%
-system.physmem.bytesPerActivate::384-511         3179      1.62%     73.93%
-system.physmem.bytesPerActivate::512-639         3479      1.77%     75.71%
-system.physmem.bytesPerActivate::640-767         2336      1.19%     76.90%
-system.physmem.bytesPerActivate::768-895         2511      1.28%     78.18%
-system.physmem.bytesPerActivate::896-1023        34323     17.48%     95.66%
-system.physmem.bytesPerActivate::1024-1151         8523      4.34%    100.00%
-system.physmem.bytesPerActivate::total         196319                      
-system.physmem.rdPerTurnAround::samples          4003                      
-system.physmem.rdPerTurnAround::mean       214.941294                      
-system.physmem.rdPerTurnAround::gmean       35.155298                      
-system.physmem.rdPerTurnAround::stdev     2727.024521                      
-system.physmem.rdPerTurnAround::0-4095           3978     99.38%     99.38%
-system.physmem.rdPerTurnAround::4096-8191           12      0.30%     99.68%
-system.physmem.rdPerTurnAround::8192-12287            3      0.07%     99.75%
-system.physmem.rdPerTurnAround::12288-16383            4      0.10%     99.85%
-system.physmem.rdPerTurnAround::16384-20479            1      0.02%     99.88%
-system.physmem.rdPerTurnAround::32768-36863            1      0.02%     99.90%
-system.physmem.rdPerTurnAround::36864-40959            1      0.02%     99.93%
-system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.95%
-system.physmem.rdPerTurnAround::69632-73727            1      0.02%     99.98%
-system.physmem.rdPerTurnAround::126976-131071            1      0.02%    100.00%
-system.physmem.rdPerTurnAround::total            4003                      
-system.physmem.wrPerTurnAround::samples          4003                      
-system.physmem.wrPerTurnAround::mean        16.550087                      
-system.physmem.wrPerTurnAround::gmean       16.475287                      
-system.physmem.wrPerTurnAround::stdev        1.816460                      
-system.physmem.wrPerTurnAround::16               3400     84.94%     84.94%
-system.physmem.wrPerTurnAround::17                 19      0.47%     85.41%
-system.physmem.wrPerTurnAround::18                373      9.32%     94.73%
-system.physmem.wrPerTurnAround::19                 54      1.35%     96.08%
-system.physmem.wrPerTurnAround::20                 20      0.50%     96.58%
-system.physmem.wrPerTurnAround::21                 27      0.67%     97.25%
-system.physmem.wrPerTurnAround::22                 15      0.37%     97.63%
-system.physmem.wrPerTurnAround::23                 21      0.52%     98.15%
-system.physmem.wrPerTurnAround::24                 14      0.35%     98.50%
-system.physmem.wrPerTurnAround::25                 14      0.35%     98.85%
-system.physmem.wrPerTurnAround::26                 14      0.35%     99.20%
-system.physmem.wrPerTurnAround::27                  6      0.15%     99.35%
-system.physmem.wrPerTurnAround::28                  7      0.17%     99.53%
-system.physmem.wrPerTurnAround::29                  6      0.15%     99.68%
-system.physmem.wrPerTurnAround::30                  1      0.02%     99.70%
-system.physmem.wrPerTurnAround::31                  3      0.07%     99.78%
-system.physmem.wrPerTurnAround::32                  4      0.10%     99.88%
-system.physmem.wrPerTurnAround::33                  1      0.02%     99.90%
-system.physmem.wrPerTurnAround::34                  2      0.05%     99.95%
-system.physmem.wrPerTurnAround::35                  1      0.02%     99.98%
-system.physmem.wrPerTurnAround::38                  1      0.02%    100.00%
-system.physmem.wrPerTurnAround::total            4003                      
-system.physmem.totQLat                    27518767878                      
-system.physmem.totMemAccLat               45476861628                      
-system.physmem.totBusLat                   4788825000                      
-system.physmem.avgQLat                       28732.28                      
-system.physmem.avgBusLat                      5000.00                      
-system.physmem.avgMemAccLat                  47482.28                      
-system.physmem.avgRdBW                         180.78                      
-system.physmem.avgWrBW                          12.50                      
-system.physmem.avgRdBWSys                      180.84                      
-system.physmem.avgWrBWSys                       12.52                      
-system.physmem.peakBW                        12800.00                      
-system.physmem.busUtil                           1.51                      
-system.physmem.busUtilRead                       1.41                      
-system.physmem.busUtilWrite                      0.10                      
-system.physmem.avgRdQLen                         1.09                      
-system.physmem.avgWrQLen                        25.37                      
-system.physmem.readRowHits                     804881                      
-system.physmem.writeRowHits                     22802                      
-system.physmem.readRowHitRate                   84.04                      
-system.physmem.writeRowHitRate                  34.40                      
-system.physmem.avgGap                       330982.45                      
-system.physmem.pageHitRate                      80.82                      
-system.physmem_0.actEnergy                  901474980                      
-system.physmem_0.preEnergy                  479122545                      
-system.physmem_0.readEnergy                5703739020                      
-system.physmem_0.writeEnergy                174499380                      
-system.physmem_0.refreshEnergy           27325665120.000008                      
-system.physmem_0.actBackEnergy            14491103160                      
-system.physmem_0.preBackEnergy              673386240                      
-system.physmem_0.actPowerDownEnergy      138371323560                      
-system.physmem_0.prePowerDownEnergy         679220160                      
-system.physmem_0.selfRefreshEnergy       661319340.000000                      
-system.physmem_0.totalEnergy             189506984115                      
-system.physmem_0.averagePower              558.903308                      
-system.physmem_0.totalIdleTime           305432505529                      
-system.physmem_0.memoryStateTime::IDLE      523884278                      
-system.physmem_0.memoryStateTime::REF     11566244000                      
-system.physmem_0.memoryStateTime::SREF      219111500                      
-system.physmem_0.memoryStateTime::PRE_PDN   1768844578                      
-system.physmem_0.memoryStateTime::ACT     21546721193                      
-system.physmem_0.memoryStateTime::ACT_PDN 303444549451                      
-system.physmem_1.actEnergy                  500335500                      
-system.physmem_1.preEnergy                  265908060                      
-system.physmem_1.readEnergy                1134695940                      
-system.physmem_1.writeEnergy                171325620                      
-system.physmem_1.refreshEnergy           25432573920.000004                      
-system.physmem_1.actBackEnergy             6980276430                      
-system.physmem_1.preBackEnergy             1364879040                      
-system.physmem_1.actPowerDownEnergy       70621447890                      
-system.physmem_1.prePowerDownEnergy       30989177760                      
-system.physmem_1.selfRefreshEnergy        25472740305                      
-system.physmem_1.totalEnergy             162933984825                      
-system.physmem_1.averagePower              480.532913                      
-system.physmem_1.totalIdleTime           320205691246                      
-system.physmem_1.memoryStateTime::IDLE     2610959521                      
-system.physmem_1.memoryStateTime::REF     10814464000                      
-system.physmem_1.memoryStateTime::SREF    84633345250                      
-system.physmem_1.memoryStateTime::PRE_PDN  80700935022                      
-system.physmem_1.memoryStateTime::ACT      5438217483                      
-system.physmem_1.memoryStateTime::ACT_PDN 154871433724                      
-system.pwrStateResidencyTicks::UNDEFINED 339069355000                      
-system.cpu.branchPred.lookups               175312537                      
-system.cpu.branchPred.condPredicted         119126010                      
-system.cpu.branchPred.condIncorrect           4023429                      
-system.cpu.branchPred.BTBLookups             95987051                      
-system.cpu.branchPred.BTBHits                67762694                      
-system.cpu.branchPred.BTBCorrect                    0                      
-system.cpu.branchPred.BTBHitPct             70.595662                      
-system.cpu.branchPred.usedRAS                18784914                      
-system.cpu.branchPred.RASInCorrect            1299715                      
-system.cpu.branchPred.indirectLookups        16714738                      
-system.cpu.branchPred.indirectHits           16702890                      
-system.cpu.branchPred.indirectMisses            11848                      
-system.cpu.branchPredindirectMispredicted      1279488                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                      
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000                      
-system.cpu.dtb.walker.walks                         0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin::total            0                      
-system.cpu.dtb.inst_hits                            0                      
-system.cpu.dtb.inst_misses                          0                      
-system.cpu.dtb.read_hits                            0                      
-system.cpu.dtb.read_misses                          0                      
-system.cpu.dtb.write_hits                           0                      
-system.cpu.dtb.write_misses                         0                      
-system.cpu.dtb.flush_tlb                            0                      
-system.cpu.dtb.flush_tlb_mva                        0                      
-system.cpu.dtb.flush_tlb_mva_asid                   0                      
-system.cpu.dtb.flush_tlb_asid                       0                      
-system.cpu.dtb.flush_entries                        0                      
-system.cpu.dtb.align_faults                         0                      
-system.cpu.dtb.prefetch_faults                      0                      
-system.cpu.dtb.domain_faults                        0                      
-system.cpu.dtb.perms_faults                         0                      
-system.cpu.dtb.read_accesses                        0                      
-system.cpu.dtb.write_accesses                       0                      
-system.cpu.dtb.inst_accesses                        0                      
-system.cpu.dtb.hits                                 0                      
-system.cpu.dtb.misses                               0                      
-system.cpu.dtb.accesses                             0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                      
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-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000                      
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-system.cpu.fetch.MiscStallCycles                 2728                      
-system.cpu.fetch.PendingTrapStallCycles            17                      
-system.cpu.fetch.IcacheWaitRetryStallCycles         3109                      
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-system.cpu.fetch.branchRate                  0.258520                      
-system.cpu.fetch.rate                        1.215526                      
-system.cpu.decode.IdleCycles                 75794919                      
-system.cpu.decode.BlockedCycles             258105460                      
-system.cpu.decode.RunCycles                 277738151                      
-system.cpu.decode.UnblockCycles              62003234                      
-system.cpu.decode.SquashCycles                4027602                      
-system.cpu.decode.BranchResolved             64856939                      
-system.cpu.decode.BranchMispred                 14426                      
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-system.cpu.rename.serializeStallCycles         209680                      
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-system.cpu.rename.IQFullEvents                2218296                      
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-system.cpu.rename.int_rename_lookups       1001843328                      
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-system.cpu.rename.serializingInsts               6852                      
-system.cpu.rename.tempSerializingInsts           6837                      
-system.cpu.rename.skidInsts                 138250974                      
-system.cpu.memDep0.insertedLoads            271864033                      
-system.cpu.memDep0.insertedStores           160594184                      
-system.cpu.memDep0.conflictingLoads           6150346                      
-system.cpu.memDep0.conflictingStores         12039275                      
-system.cpu.iq.iqInstsAdded                  899826395                      
-system.cpu.iq.iqNonSpecInstsAdded               12582                      
-system.cpu.iq.iqInstsIssued                 860048195                      
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-system.cpu.iq.iqSquashedInstsExamined       111114018                      
-system.cpu.iq.iqSquashedOperandsExamined    244270336                      
-system.cpu.iq.iqSquashedNonSpecRemoved            428                      
-system.cpu.iq.issued_per_cycle::samples     677669366                      
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-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     24.22%
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-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00%
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-system.cpu.iq.FU_type_0::FloatMemWrite        3831959      0.45%    100.00%
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-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00%
-system.cpu.iq.FU_type_0::total              860048195                      
-system.cpu.iq.rate                           1.268248                      
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-system.cpu.iq.fu_busy_rate                   0.322783                      
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-system.cpu.iq.int_alu_accesses             1100523479                      
-system.cpu.iq.fp_alu_accesses                37133365                      
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-system.cpu.iew.lsq.thread0.ignoredResponses          150                      
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-system.cpu.iew.lsq.thread0.rescheduledLoads      1918749                      
-system.cpu.iew.lsq.thread0.cacheBlocked         18225                      
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-system.cpu.iew.iewSquashCycles                4027602                      
-system.cpu.iew.iewBlockCycles                10592950                      
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-system.cpu.iew.iewIQFullEvents                    932                      
-system.cpu.iew.iewLSQFullEvents                  3107                      
-system.cpu.iew.memOrderViolationEvents          18653                      
-system.cpu.iew.predictedTakenIncorrect        3297561                      
-system.cpu.iew.predictedNotTakenIncorrect      3294434                      
-system.cpu.iew.branchMispredicts              6591995                      
-system.cpu.iew.iewExecutedInsts             850188945                      
-system.cpu.iew.iewExecLoadInsts             263367686                      
-system.cpu.iew.iewExecSquashedInsts           9859250                      
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-system.cpu.iew.exec_nop                          9996                      
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-system.cpu.iew.exec_stores                  152692299                      
-system.cpu.iew.exec_rate                     1.253710                      
-system.cpu.iew.wb_sent                      846316526                      
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-system.cpu.iew.wb_producers                 486213090                      
-system.cpu.iew.wb_consumers                 804713496                      
-system.cpu.iew.wb_rate                       1.246035                      
-system.cpu.iew.wb_fanout                     0.604206                      
-system.cpu.commit.commitSquashedInsts       103170323                      
-system.cpu.commit.commitNonSpecStalls           12154                      
-system.cpu.commit.branchMispredicts           4009286                      
-system.cpu.commit.committed_per_cycle::samples    663080037                      
-system.cpu.commit.committed_per_cycle::mean     1.189495                      
-system.cpu.commit.committed_per_cycle::stdev     2.047357                      
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-system.cpu.commit.committed_per_cycle::2     51343947      7.74%     84.65%
-system.cpu.commit.committed_per_cycle::3     28225650      4.26%     88.91%
-system.cpu.commit.committed_per_cycle::4     14387181      2.17%     91.08%
-system.cpu.commit.committed_per_cycle::5     14772519      2.23%     93.31%
-system.cpu.commit.committed_per_cycle::6      7871150      1.19%     94.49%
-system.cpu.commit.committed_per_cycle::7      6554658      0.99%     95.48%
-system.cpu.commit.committed_per_cycle::8     29951867      4.52%    100.00%
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00%
-system.cpu.commit.committed_per_cycle::min_value            0                      
-system.cpu.commit.committed_per_cycle::max_value            8                      
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-system.cpu.commit.committedInsts            640654411                      
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-system.cpu.toL2Bus.snoops                      553229                      
-system.cpu.toL2Bus.snoopTraffic               4266048                      
-system.cpu.toL2Bus.snoop_fanout::samples      5291746                      
-system.cpu.toL2Bus.snoop_fanout::mean        0.121883                      
-system.cpu.toL2Bus.snoop_fanout::stdev       0.327151                      
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00%
-system.cpu.toL2Bus.snoop_fanout::0            4646773     87.81%     87.81%
-system.cpu.toL2Bus.snoop_fanout::1             644972     12.19%    100.00%
-system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value            0                      
-system.cpu.toL2Bus.snoop_fanout::max_value            2                      
-system.cpu.toL2Bus.snoop_fanout::total        5291746                      
-system.cpu.toL2Bus.reqLayer0.occupancy     9475188000                      
-system.cpu.toL2Bus.reqLayer0.utilization          2.8                      
-system.cpu.toL2Bus.respLayer0.occupancy    2972215996                      
-system.cpu.toL2Bus.respLayer0.utilization          0.9                      
-system.cpu.toL2Bus.respLayer1.occupancy    4135722477                      
-system.cpu.toL2Bus.respLayer1.utilization          1.2                      
-system.membus.snoop_filter.tot_requests       1255754                      
-system.membus.snoop_filter.hit_single_requests       941197                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 339069355000                      
-system.membus.trans_dist::ReadResp             956694                      
-system.membus.trans_dist::WritebackDirty        66350                      
-system.membus.trans_dist::CleanEvict           231013                      
-system.membus.trans_dist::UpgradeReq              308                      
-system.membus.trans_dist::ReadExReq              1387                      
-system.membus.trans_dist::ReadExResp             1387                      
-system.membus.trans_dist::ReadSharedReq        956696                      
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2213835                      
-system.membus.pkt_count::total                2213835                      
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65563584                      
-system.membus.pkt_size::total                65563584                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples            958391                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0                  958391    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total              958391                      
-system.membus.reqLayer0.occupancy          1760245062                      
-system.membus.reqLayer0.utilization               0.5                      
-system.membus.respLayer1.occupancy         5035040414                      
-system.membus.respLayer1.utilization              1.5                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
deleted file mode 100644 (file)
index 8d15582..0000000
+++ /dev/null
@@ -1,330 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=perlbmk -I. -I lib mdred.makerand.pl
-cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
deleted file mode 100755 (executable)
index 92c7443..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-warn: fcntl64(3, 2) passed through to host
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
deleted file mode 100755 (executable)
index 2146043..0000000
+++ /dev/null
@@ -1,650 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 17:55:48
-gem5 started Apr  3 2017 17:56:15
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54237
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-637000: 2581848540
-636000: 4117852332
-635000: 329081094
-634000: 545393176
-633000: 3107247613
-632000: 897887463
-631000: 806367477
-630000: 1682157095
-629000: 1188376072
-628000: 4076707785
-627000: 3521684454
-626000: 3144526095
-625000: 1399223384
-624000: 3380494826
-623000: 4086509498
-622000: 1473819475
-621000: 638751284
-620000: 3149483163
-619000: 1489851375
-618000: 1447059134
-617000: 136329498
-616000: 1288452788
-615000: 3949816816
-614000: 318984246
-613000: 1019963195
-612000: 2875280299
-611000: 2997394777
-610000: 4014932807
-609000: 2291235006
-608000: 355450951
-607000: 201970399
-606000: 3626124461
-605000: 2207253273
-604000: 2243886712
-603000: 46791684
-602000: 3176322294
-601000: 1120582847
-600000: 411705454
-599000: 3162380308
-598000: 2732375303
-597000: 1376844609
-596000: 3003023122
-595000: 3869968535
-594000: 1327286554
-593000: 160655029
-592000: 2038558826
-591000: 3948772976
-590000: 439262378
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-587000: 4240182727
-586000: 2283602206
-585000: 1129811410
-584000: 2831949168
-583000: 1224559023
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-579000: 1974816198
-578000: 449576701
-577000: 1424873035
-576000: 2370444290
-575000: 1743089134
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-572000: 2449219691
-571000: 3774476172
-570000: 1111630327
-569000: 121721805
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-546000: 3065674956
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-541000: 521956271
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-536000: 432804999
-535000: 1021857051
-534000: 2644812356
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-531000: 3976696839
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-528000: 320399857
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-504000: 3950453295
-503000: 4186097241
-502000: 327518343
-501000: 3052462710
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-498000: 3613195151
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-433000: 692226634
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-430000: 2183000701
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-428000: 941117387
-427000: 3805851413
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-0: 290958364
-Exiting @ tick 395726778500 because exiting with last active thread context
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
deleted file mode 100644 (file)
index b1e10c0..0000000
+++ /dev/null
@@ -1,262 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.395727                      
-sim_ticks                                395726778500                      
-final_tick                               395726778500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 761557                      
-host_op_rate                                   937577                      
-host_tick_rate                              470407263                      
-host_mem_usage                                 279508                      
-host_seconds                                   841.24                      
-sim_insts                                   640654411                      
-sim_ops                                     788730070                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500                      
-system.physmem.bytes_read::cpu.inst        2573511596                      
-system.physmem.bytes_read::cpu.data        1144718516                      
-system.physmem.bytes_read::total           3718230112                      
-system.physmem.bytes_inst_read::cpu.inst   2573511596                      
-system.physmem.bytes_inst_read::total      2573511596                      
-system.physmem.bytes_written::cpu.data      523317413                      
-system.physmem.bytes_written::total         523317413                      
-system.physmem.num_reads::cpu.inst          643377899                      
-system.physmem.num_reads::cpu.data          250335238                      
-system.physmem.num_reads::total             893713137                      
-system.physmem.num_writes::cpu.data         128957216                      
-system.physmem.num_writes::total            128957216                      
-system.physmem.bw_read::cpu.inst           6503253598                      
-system.physmem.bw_read::cpu.data           2892699151                      
-system.physmem.bw_read::total              9395952748                      
-system.physmem.bw_inst_read::cpu.inst      6503253598                      
-system.physmem.bw_inst_read::total         6503253598                      
-system.physmem.bw_write::cpu.data          1322421027                      
-system.physmem.bw_write::total             1322421027                      
-system.physmem.bw_total::cpu.inst          6503253598                      
-system.physmem.bw_total::cpu.data          4215120178                      
-system.physmem.bw_total::total            10718373776                      
-system.pwrStateResidencyTicks::UNDEFINED 395726778500                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                      
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-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                      
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500                      
-system.cpu.dtb.walker.walks                         0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin::total            0                      
-system.cpu.dtb.inst_hits                            0                      
-system.cpu.dtb.inst_misses                          0                      
-system.cpu.dtb.read_hits                            0                      
-system.cpu.dtb.read_misses                          0                      
-system.cpu.dtb.write_hits                           0                      
-system.cpu.dtb.write_misses                         0                      
-system.cpu.dtb.flush_tlb                            0                      
-system.cpu.dtb.flush_tlb_mva                        0                      
-system.cpu.dtb.flush_tlb_mva_asid                   0                      
-system.cpu.dtb.flush_tlb_asid                       0                      
-system.cpu.dtb.flush_entries                        0                      
-system.cpu.dtb.align_faults                         0                      
-system.cpu.dtb.prefetch_faults                      0                      
-system.cpu.dtb.domain_faults                        0                      
-system.cpu.dtb.perms_faults                         0                      
-system.cpu.dtb.read_accesses                        0                      
-system.cpu.dtb.write_accesses                       0                      
-system.cpu.dtb.inst_accesses                        0                      
-system.cpu.dtb.hits                                 0                      
-system.cpu.dtb.misses                               0                      
-system.cpu.dtb.accesses                             0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.hits              0                      
-system.cpu.istage2_mmu.stage2_tlb.misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500                      
-system.cpu.itb.walker.walks                         0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.itb.walker.walkRequestOrigin::total            0                      
-system.cpu.itb.inst_hits                            0                      
-system.cpu.itb.inst_misses                          0                      
-system.cpu.itb.read_hits                            0                      
-system.cpu.itb.read_misses                          0                      
-system.cpu.itb.write_hits                           0                      
-system.cpu.itb.write_misses                         0                      
-system.cpu.itb.flush_tlb                            0                      
-system.cpu.itb.flush_tlb_mva                        0                      
-system.cpu.itb.flush_tlb_mva_asid                   0                      
-system.cpu.itb.flush_tlb_asid                       0                      
-system.cpu.itb.flush_entries                        0                      
-system.cpu.itb.align_faults                         0                      
-system.cpu.itb.prefetch_faults                      0                      
-system.cpu.itb.domain_faults                        0                      
-system.cpu.itb.perms_faults                         0                      
-system.cpu.itb.read_accesses                        0                      
-system.cpu.itb.write_accesses                       0                      
-system.cpu.itb.inst_accesses                        0                      
-system.cpu.itb.hits                                 0                      
-system.cpu.itb.misses                               0                      
-system.cpu.itb.accesses                             0                      
-system.cpu.workload.numSyscalls                   673                      
-system.cpu.pwrStateResidencyTicks::ON    395726778500                      
-system.cpu.numCycles                        791453558                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.committedInsts                   640654411                      
-system.cpu.committedOps                     788730070                      
-system.cpu.num_int_alu_accesses             682251400                      
-system.cpu.num_fp_alu_accesses               24239771                      
-system.cpu.num_func_calls                    37261296                      
-system.cpu.num_conditional_control_insts     91575866                      
-system.cpu.num_int_insts                    682251400                      
-system.cpu.num_fp_insts                      24239771                      
-system.cpu.num_int_register_reads          1268495038                      
-system.cpu.num_int_register_writes          468423268                      
-system.cpu.num_fp_register_reads             28064643                      
-system.cpu.num_fp_register_writes            21684311                      
-system.cpu.num_cc_register_reads           2369173294                      
-system.cpu.num_cc_register_writes           351919006                      
-system.cpu.num_mem_refs                     381221435                      
-system.cpu.num_load_insts                   252240938                      
-system.cpu.num_store_insts                  128980497                      
-system.cpu.num_idle_cycles                          0                      
-system.cpu.num_busy_cycles                  791453558                      
-system.cpu.not_idle_fraction                        1                      
-system.cpu.idle_fraction                            0                      
-system.cpu.Branches                         137364860                      
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00%
-system.cpu.op_class::IntAlu                 385757467     48.91%     48.91%
-system.cpu.op_class::IntMult                  5173441      0.66%     49.56%
-system.cpu.op_class::IntDiv                         0      0.00%     49.56%
-system.cpu.op_class::FloatAdd                       0      0.00%     49.56%
-system.cpu.op_class::FloatCmp                       0      0.00%     49.56%
-system.cpu.op_class::FloatCvt                       0      0.00%     49.56%
-system.cpu.op_class::FloatMult                      0      0.00%     49.56%
-system.cpu.op_class::FloatMultAcc                   0      0.00%     49.56%
-system.cpu.op_class::FloatDiv                       0      0.00%     49.56%
-system.cpu.op_class::FloatMisc                      0      0.00%     49.56%
-system.cpu.op_class::FloatSqrt                      0      0.00%     49.56%
-system.cpu.op_class::SimdAdd                        0      0.00%     49.56%
-system.cpu.op_class::SimdAddAcc                     0      0.00%     49.56%
-system.cpu.op_class::SimdAlu                        0      0.00%     49.56%
-system.cpu.op_class::SimdCmp                        0      0.00%     49.56%
-system.cpu.op_class::SimdCvt                        0      0.00%     49.56%
-system.cpu.op_class::SimdMisc                       0      0.00%     49.56%
-system.cpu.op_class::SimdMult                       0      0.00%     49.56%
-system.cpu.op_class::SimdMultAcc                    0      0.00%     49.56%
-system.cpu.op_class::SimdShift                      0      0.00%     49.56%
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.56%
-system.cpu.op_class::SimdSqrt                       0      0.00%     49.56%
-system.cpu.op_class::SimdFloatAdd              637528      0.08%     49.65%
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.65%
-system.cpu.op_class::SimdFloatCmp             3187668      0.40%     50.05%
-system.cpu.op_class::SimdFloatCvt             2550131      0.32%     50.37%
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.37%
-system.cpu.op_class::SimdFloatMisc           10203074      1.29%     51.67%
-system.cpu.op_class::SimdFloatMult                  0      0.00%     51.67%
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.67%
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.67%
-system.cpu.op_class::MemRead                245222568     31.09%     82.76%
-system.cpu.op_class::MemWrite               125149823     15.87%     98.62%
-system.cpu.op_class::FloatMemRead             7018370      0.89%     99.51%
-system.cpu.op_class::FloatMemWrite            3830674      0.49%    100.00%
-system.cpu.op_class::IprAccess                      0      0.00%    100.00%
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
-system.cpu.op_class::total                  788730744                      
-system.membus.snoop_filter.tot_requests             0                      
-system.membus.snoop_filter.hit_single_requests            0                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500                      
-system.membus.trans_dist::ReadReq           893703778                      
-system.membus.trans_dist::ReadResp          893709517                      
-system.membus.trans_dist::WriteReq          128951477                      
-system.membus.trans_dist::WriteResp         128951477                      
-system.membus.trans_dist::SoftPFReq              3620                      
-system.membus.trans_dist::SoftPFResp             3620                      
-system.membus.trans_dist::LoadLockedReq          5739                      
-system.membus.trans_dist::StoreCondReq           5739                      
-system.membus.trans_dist::StoreCondResp          5739                      
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1286755798                      
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    758584908                      
-system.membus.pkt_count::total             2045340706                      
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2573511596                      
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   1668035929                      
-system.membus.pkt_size::total              4241547525                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples        1022670353                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0              1022670353    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total          1022670353                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
deleted file mode 100644 (file)
index b546914..0000000
+++ /dev/null
@@ -1,499 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=perlbmk -I. -I lib mdred.makerand.pl
-cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
deleted file mode 100755 (executable)
index 92c7443..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0.  Starting simulation...
-warn: fcntl64(3, 2) passed through to host
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
deleted file mode 100755 (executable)
index e660db3..0000000
+++ /dev/null
@@ -1,650 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 17:55:48
-gem5 started Apr  3 2017 18:24:09
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59398
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
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-52000: 2162594060
-51000: 2947744069
-50000: 4024793290
-49000: 631161701
-48000: 728285173
-47000: 1487641693
-46000: 4049519424
-45000: 613160608
-44000: 1566126172
-43000: 3731725133
-42000: 2746368727
-41000: 4168967735
-40000: 1319649932
-39000: 2964978784
-38000: 967937134
-37000: 3116555742
-36000: 2279790642
-35000: 2852914953
-34000: 1040410911
-33000: 226200467
-32000: 1765748697
-31000: 1418838964
-30000: 1362983292
-29000: 2877029789
-28000: 583076938
-27000: 2797138728
-26000: 3033567067
-25000: 3902265889
-24000: 3287868661
-23000: 2411740885
-22000: 2747756860
-21000: 1889759908
-20000: 2975722149
-19000: 3027693370
-18000: 2418258302
-17000: 490864179
-16000: 1944489573
-15000: 4212838860
-14000: 1782397962
-13000: 1981080238
-12000: 1213651424
-11000: 1407527546
-10000: 661520991
-9000: 143129551
-8000: 3293448370
-7000: 764314400
-6000: 2246553770
-5000: 2459308892
-4000: 3776833152
-3000: 2208260083
-2000: 2845746745
-1000: 2068042552
-0: 290958364
-Exiting @ tick 1046047111500 because exiting with last active thread context
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
deleted file mode 100644 (file)
index be07be0..0000000
+++ /dev/null
@@ -1,686 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.046047                      
-sim_ticks                                1046047111500                      
-final_tick                               1046047111500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 550252                      
-host_op_rate                                   676018                      
-host_tick_rate                              900249421                      
-host_mem_usage                                 289500                      
-host_seconds                                  1161.95                      
-sim_insts                                   639366787                      
-sim_ops                                     785501035                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.physmem.bytes_read::cpu.inst            112576                      
-system.physmem.bytes_read::cpu.data          18471424                      
-system.physmem.bytes_read::total             18584000                      
-system.physmem.bytes_inst_read::cpu.inst       112576                      
-system.physmem.bytes_inst_read::total          112576                      
-system.physmem.bytes_written::writebacks      4230272                      
-system.physmem.bytes_written::total           4230272                      
-system.physmem.num_reads::cpu.inst               1759                      
-system.physmem.num_reads::cpu.data             288616                      
-system.physmem.num_reads::total                290375                      
-system.physmem.num_writes::writebacks           66098                      
-system.physmem.num_writes::total                66098                      
-system.physmem.bw_read::cpu.inst               107620                      
-system.physmem.bw_read::cpu.data             17658310                      
-system.physmem.bw_read::total                17765930                      
-system.physmem.bw_inst_read::cpu.inst          107620                      
-system.physmem.bw_inst_read::total             107620                      
-system.physmem.bw_write::writebacks           4044055                      
-system.physmem.bw_write::total                4044055                      
-system.physmem.bw_total::writebacks           4044055                      
-system.physmem.bw_total::cpu.inst              107620                      
-system.physmem.bw_total::cpu.data            17658310                      
-system.physmem.bw_total::total               21809985                      
-system.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                      
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                      
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu.dtb.walker.walks                         0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.dtb.walker.walkRequestOrigin::total            0                      
-system.cpu.dtb.inst_hits                            0                      
-system.cpu.dtb.inst_misses                          0                      
-system.cpu.dtb.read_hits                            0                      
-system.cpu.dtb.read_misses                          0                      
-system.cpu.dtb.write_hits                           0                      
-system.cpu.dtb.write_misses                         0                      
-system.cpu.dtb.flush_tlb                            0                      
-system.cpu.dtb.flush_tlb_mva                        0                      
-system.cpu.dtb.flush_tlb_mva_asid                   0                      
-system.cpu.dtb.flush_tlb_asid                       0                      
-system.cpu.dtb.flush_entries                        0                      
-system.cpu.dtb.align_faults                         0                      
-system.cpu.dtb.prefetch_faults                      0                      
-system.cpu.dtb.domain_faults                        0                      
-system.cpu.dtb.perms_faults                         0                      
-system.cpu.dtb.read_accesses                        0                      
-system.cpu.dtb.write_accesses                       0                      
-system.cpu.dtb.inst_accesses                        0                      
-system.cpu.dtb.hits                                 0                      
-system.cpu.dtb.misses                               0                      
-system.cpu.dtb.accesses                             0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                      
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                      
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                      
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                      
-system.cpu.istage2_mmu.stage2_tlb.hits              0                      
-system.cpu.istage2_mmu.stage2_tlb.misses            0                      
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                      
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu.itb.walker.walks                         0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                      
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                      
-system.cpu.itb.walker.walkRequestOrigin::total            0                      
-system.cpu.itb.inst_hits                            0                      
-system.cpu.itb.inst_misses                          0                      
-system.cpu.itb.read_hits                            0                      
-system.cpu.itb.read_misses                          0                      
-system.cpu.itb.write_hits                           0                      
-system.cpu.itb.write_misses                         0                      
-system.cpu.itb.flush_tlb                            0                      
-system.cpu.itb.flush_tlb_mva                        0                      
-system.cpu.itb.flush_tlb_mva_asid                   0                      
-system.cpu.itb.flush_tlb_asid                       0                      
-system.cpu.itb.flush_entries                        0                      
-system.cpu.itb.align_faults                         0                      
-system.cpu.itb.prefetch_faults                      0                      
-system.cpu.itb.domain_faults                        0                      
-system.cpu.itb.perms_faults                         0                      
-system.cpu.itb.read_accesses                        0                      
-system.cpu.itb.write_accesses                       0                      
-system.cpu.itb.inst_accesses                        0                      
-system.cpu.itb.hits                                 0                      
-system.cpu.itb.misses                               0                      
-system.cpu.itb.accesses                             0                      
-system.cpu.workload.numSyscalls                   673                      
-system.cpu.pwrStateResidencyTicks::ON    1046047111500                      
-system.cpu.numCycles                       2092094223                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.committedInsts                   639366787                      
-system.cpu.committedOps                     785501035                      
-system.cpu.num_int_alu_accesses             682251400                      
-system.cpu.num_fp_alu_accesses               24239771                      
-system.cpu.num_func_calls                    37261296                      
-system.cpu.num_conditional_control_insts     91575866                      
-system.cpu.num_int_insts                    682251400                      
-system.cpu.num_fp_insts                      24239771                      
-system.cpu.num_int_register_reads          1272307653                      
-system.cpu.num_int_register_writes          468423268                      
-system.cpu.num_fp_register_reads             28064643                      
-system.cpu.num_fp_register_writes            21684311                      
-system.cpu.num_cc_register_reads           3116296060                      
-system.cpu.num_cc_register_writes           351919006                      
-system.cpu.num_mem_refs                     381221435                      
-system.cpu.num_load_insts                   252240938                      
-system.cpu.num_store_insts                  128980497                      
-system.cpu.num_idle_cycles                          0                      
-system.cpu.num_busy_cycles                 2092094223                      
-system.cpu.not_idle_fraction                        1                      
-system.cpu.idle_fraction                            0                      
-system.cpu.Branches                         137364860                      
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00%
-system.cpu.op_class::IntAlu                 385757467     48.91%     48.91%
-system.cpu.op_class::IntMult                  5173441      0.66%     49.56%
-system.cpu.op_class::IntDiv                         0      0.00%     49.56%
-system.cpu.op_class::FloatAdd                       0      0.00%     49.56%
-system.cpu.op_class::FloatCmp                       0      0.00%     49.56%
-system.cpu.op_class::FloatCvt                       0      0.00%     49.56%
-system.cpu.op_class::FloatMult                      0      0.00%     49.56%
-system.cpu.op_class::FloatMultAcc                   0      0.00%     49.56%
-system.cpu.op_class::FloatDiv                       0      0.00%     49.56%
-system.cpu.op_class::FloatMisc                      0      0.00%     49.56%
-system.cpu.op_class::FloatSqrt                      0      0.00%     49.56%
-system.cpu.op_class::SimdAdd                        0      0.00%     49.56%
-system.cpu.op_class::SimdAddAcc                     0      0.00%     49.56%
-system.cpu.op_class::SimdAlu                        0      0.00%     49.56%
-system.cpu.op_class::SimdCmp                        0      0.00%     49.56%
-system.cpu.op_class::SimdCvt                        0      0.00%     49.56%
-system.cpu.op_class::SimdMisc                       0      0.00%     49.56%
-system.cpu.op_class::SimdMult                       0      0.00%     49.56%
-system.cpu.op_class::SimdMultAcc                    0      0.00%     49.56%
-system.cpu.op_class::SimdShift                      0      0.00%     49.56%
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     49.56%
-system.cpu.op_class::SimdSqrt                       0      0.00%     49.56%
-system.cpu.op_class::SimdFloatAdd              637528      0.08%     49.65%
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     49.65%
-system.cpu.op_class::SimdFloatCmp             3187668      0.40%     50.05%
-system.cpu.op_class::SimdFloatCvt             2550131      0.32%     50.37%
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     50.37%
-system.cpu.op_class::SimdFloatMisc           10203074      1.29%     51.67%
-system.cpu.op_class::SimdFloatMult                  0      0.00%     51.67%
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     51.67%
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     51.67%
-system.cpu.op_class::MemRead                245222568     31.09%     82.76%
-system.cpu.op_class::MemWrite               125149823     15.87%     98.62%
-system.cpu.op_class::FloatMemRead             7018370      0.89%     99.51%
-system.cpu.op_class::FloatMemWrite            3830674      0.49%    100.00%
-system.cpu.op_class::IprAccess                      0      0.00%    100.00%
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
-system.cpu.op_class::total                  788730744                      
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu.dcache.tags.replacements            778046                      
-system.cpu.dcache.tags.tagsinuse          4093.536872                      
-system.cpu.dcache.tags.total_refs           378510311                      
-system.cpu.dcache.tags.sampled_refs            782142                      
-system.cpu.dcache.tags.avg_refs            483.940654                      
-system.cpu.dcache.tags.warmup_cycle        1048273500                      
-system.cpu.dcache.tags.occ_blocks::cpu.data  4093.536872                      
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999399                      
-system.cpu.dcache.tags.occ_percent::total     0.999399                      
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          122                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          591                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1037                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2319                      
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                      
-system.cpu.dcache.tags.tag_accesses         759367050                      
-system.cpu.dcache.tags.data_accesses        759367050                      
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu.dcache.ReadReq_hits::cpu.data    249613198                      
-system.cpu.dcache.ReadReq_hits::total       249613198                      
-system.cpu.dcache.WriteReq_hits::cpu.data    128882154                      
-system.cpu.dcache.WriteReq_hits::total      128882154                      
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3481                      
-system.cpu.dcache.SoftPFReq_hits::total          3481                      
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                      
-system.cpu.dcache.LoadLockedReq_hits::total         5739                      
-system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                      
-system.cpu.dcache.StoreCondReq_hits::total         5739                      
-system.cpu.dcache.demand_hits::cpu.data     378495352                      
-system.cpu.dcache.demand_hits::total        378495352                      
-system.cpu.dcache.overall_hits::cpu.data    378498833                      
-system.cpu.dcache.overall_hits::total       378498833                      
-system.cpu.dcache.ReadReq_misses::cpu.data       712681                      
-system.cpu.dcache.ReadReq_misses::total        712681                      
-system.cpu.dcache.WriteReq_misses::cpu.data        69323                      
-system.cpu.dcache.WriteReq_misses::total        69323                      
-system.cpu.dcache.SoftPFReq_misses::cpu.data          139                      
-system.cpu.dcache.SoftPFReq_misses::total          139                      
-system.cpu.dcache.demand_misses::cpu.data       782004                      
-system.cpu.dcache.demand_misses::total         782004                      
-system.cpu.dcache.overall_misses::cpu.data       782143                      
-system.cpu.dcache.overall_misses::total        782143                      
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  20392265000                      
-system.cpu.dcache.ReadReq_miss_latency::total  20392265000                      
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4205904500                      
-system.cpu.dcache.WriteReq_miss_latency::total   4205904500                      
-system.cpu.dcache.demand_miss_latency::cpu.data  24598169500                      
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-system.cpu.l2cache.blocked_cycles::no_mshrs            0                      
-system.cpu.l2cache.blocked_cycles::no_targets            0                      
-system.cpu.l2cache.blocked::no_mshrs                0                      
-system.cpu.l2cache.blocked::no_targets              0                      
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.l2cache.writebacks::writebacks        66098                      
-system.cpu.l2cache.writebacks::total            66098                      
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                      
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1759                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1759                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222523                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222523                      
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1759                      
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288616                      
-system.cpu.l2cache.demand_mshr_misses::total       290375                      
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1759                      
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288616                      
-system.cpu.l2cache.overall_mshr_misses::total       290375                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3337749500                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3337749500                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     88922500                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     88922500                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  11237690000                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  11237690000                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     88922500                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14575439500                      
-system.cpu.l2cache.demand_mshr_miss_latency::total  14664362000                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     88922500                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14575439500                      
-system.cpu.l2cache.overall_mshr_miss_latency::total  14664362000                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953407                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953407                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.172316                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.172316                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312173                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312173                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.172316                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.369007                      
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.366473                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.172316                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.369007                      
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.366473                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903                      
-system.cpu.toL2Bus.snoop_filter.tot_requests      1579165                      
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       786845                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1110                      
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1590                      
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1583                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            7                      
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.cpu.toL2Bus.trans_dist::ReadResp        723027                      
-system.cpu.toL2Bus.trans_dist::WritebackDirty       155065                      
-system.cpu.toL2Bus.trans_dist::WritebackClean         8769                      
-system.cpu.toL2Bus.trans_dist::CleanEvict       880772                      
-system.cpu.toL2Bus.trans_dist::ReadExReq        69323                      
-system.cpu.toL2Bus.trans_dist::ReadExResp        69323                      
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        10208                      
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       712819                      
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        29185                      
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2342330                      
-system.cpu.toL2Bus.pkt_count::total           2371515                      
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1214528                      
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55750976                      
-system.cpu.toL2Bus.pkt_size::total           56965504                      
-system.cpu.toL2Bus.snoops                      257791                      
-system.cpu.toL2Bus.snoopTraffic               4230272                      
-system.cpu.toL2Bus.snoop_fanout::samples      1050141                      
-system.cpu.toL2Bus.snoop_fanout::mean        0.002606                      
-system.cpu.toL2Bus.snoop_fanout::stdev       0.051116                      
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00%
-system.cpu.toL2Bus.snoop_fanout::0            1047411     99.74%     99.74%
-system.cpu.toL2Bus.snoop_fanout::1               2723      0.26%    100.00%
-system.cpu.toL2Bus.snoop_fanout::2                  7      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value            0                      
-system.cpu.toL2Bus.snoop_fanout::max_value            2                      
-system.cpu.toL2Bus.snoop_fanout::total        1050141                      
-system.cpu.toL2Bus.reqLayer0.occupancy      887318500                      
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                      
-system.cpu.toL2Bus.respLayer0.occupancy      15312000                      
-system.cpu.toL2Bus.respLayer0.utilization          0.0                      
-system.cpu.toL2Bus.respLayer1.occupancy    1173213000                      
-system.cpu.toL2Bus.respLayer1.utilization          0.1                      
-system.membus.snoop_filter.tot_requests        546577                      
-system.membus.snoop_filter.hit_single_requests       256223                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500                      
-system.membus.trans_dist::ReadResp             224282                      
-system.membus.trans_dist::WritebackDirty        66098                      
-system.membus.trans_dist::CleanEvict           190103                      
-system.membus.trans_dist::ReadExReq             66093                      
-system.membus.trans_dist::ReadExResp            66093                      
-system.membus.trans_dist::ReadSharedReq        224282                      
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       836951                      
-system.membus.pkt_count::total                 836951                      
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22814272                      
-system.membus.pkt_size::total                22814272                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples            290376                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0                  290376    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total              290376                      
-system.membus.reqLayer0.occupancy           811341000                      
-system.membus.reqLayer0.utilization               0.1                      
-system.membus.respLayer1.occupancy         1451875000                      
-system.membus.respLayer1.utilization              0.1                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/test.py b/tests/long/se/40.perlbmk/test.py
deleted file mode 100644 (file)
index 2d97c80..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
-
-m5.util.addToPath('../configs/common')
-from cpu2000 import perlbmk_makerand
-
-workload = perlbmk_makerand(isa, opsys, 'mdred')
-root.system.cpu[0].workload = workload.makeProcess()