Update test with a/b reset
authorEddie Hung <eddie@fpgeh.com>
Wed, 11 Sep 2019 17:13:13 +0000 (10:13 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 11 Sep 2019 17:13:13 +0000 (10:13 -0700)
tests/xilinx/macc.v

index c6ad2a578a268d2a7acc1eff59d71c5a6ee12f22..5dc99ab8eca47b4d3dcd566087341be50c8ccf62 100644 (file)
@@ -61,10 +61,12 @@ always @(posedge clk) begin
                // Store accumulation result into a register
                adder_out <= adder_out + mult_reg;
        end
-    if (rst) begin
+       if (rst) begin
+               a_reg <= 0;
+               b_reg <= 0;
                mult_reg <= 0;
                adder_out <= 0;
-    end
+       end
 end
 
 // Output accumulation result