from migen.genlib.cordic import Cordic
from mibuild.tools import mkdir_noerror
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
class CordicImpl(Module):
self.platform.build(self, build_name=self.name)
class Platform(XilinxPlatform):
+ default_clk_name = "clk"
+ default_clk_period = 20.0
+
_io = [
("clk", 0, Pins("AB13")),
- ("rst", 0, Pins("V5")),
("do", 0,
Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3",
"U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4",
),
]
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
- lambda p: SimpleCRG(p, "clk", "rst"))
+ XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", self._io)
if __name__ == "__main__":
default = dict(width=16, guard=0, eval_mode="pipelined",
return vns
def add_period_constraint(self, clk, period):
+ # TODO: handle differential clk
self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
+++ /dev/null
-from migen.fhdl.std import *
-
-class SimpleCRG(Module):
- def __init__(self, platform, clk_name, rst_name, rst_invert=False):
- reset_less = rst_name is None
- self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
- self._clk = platform.request(clk_name)
- self.comb += self.cd_sys.clk.eq(self._clk)
-
- if not reset_less:
- if rst_invert:
- self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
- else:
- self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
from migen.fhdl.std import *
from migen.fhdl.structure import _Fragment
from migen.genlib.record import Record
+from migen.genlib.io import CRG
from migen.fhdl import verilog, edif
from migen.util.misc import autotype
return self.platform_commands
class GenericPlatform:
- def __init__(self, device, io, default_crg_factory=None, connectors=[], name=None):
+ def __init__(self, device, io, connectors=[], name=None):
self.device = device
self.constraint_manager = ConstraintManager(io, connectors)
- self.default_crg_factory = default_crg_factory
if name is None:
name = self.__module__.split(".")[-1]
self.name = name
def lookup_request(self, *args, **kwargs):
return self.constraint_manager.lookup_request(*args, **kwargs)
+ def add_period_constraint(self, clk, period):
+ raise NotImplementedError
+
def add_platform_command(self, *args, **kwargs):
return self.constraint_manager.add_platform_command(*args, **kwargs)
raise ConstraintError("Already finalized")
# if none exists, create a default clock domain and drive it
if not fragment.clock_domains:
- if self.default_crg_factory is None:
- raise NotImplementedError("No clock/reset generator defined by either platform or user")
- crg = self.default_crg_factory(self)
+ if not hasattr(self, "default_clk_name"):
+ raise NotImplementedError("No default clock and no clock domain defined")
+ crg = CRG(self.request(self.default_clk_name))
fragment += crg.get_fragment()
self.do_finalize(fragment, *args, **kwargs)
self.finalized = True
def do_finalize(self, fragment, *args, **kwargs):
- """overload this and e.g. add_platform_command()'s after the
- modules had their say"""
- pass
+ """overload this and e.g. add_platform_command()'s after the modules had their say"""
+ if hasattr(self, "default_clk_period"):
+ try:
+ self.add_period_constraint(self.lookup_request(self.default_clk_name), self.default_clk_period)
+ except ConstraintError:
+ pass
def add_source(self, filename, language=None):
if language is None:
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
_ios = [
default_clk_period = 10
def __init__(self):
- XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
- lambda p: SimpleCRG(p, "clk0", None), _connectors)
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk0"), 10)
- except ConstraintError:
- pass
+ XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors)
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
_ios = [
default_clk_period = 10.526
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios,
- lambda p: SimpleCRG(p, "clk3", None), _connectors)
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk3"), 10.526)
- except ConstraintError:
- pass
+ XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors)
# License: BSD
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.altera.quartus import AlteraQuartusPlatform
from mibuild.altera.programmer import USBBlaster
default_clk_period = 20
def __init__(self):
- AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io,
- lambda p: SimpleCRG(p, "clk50", None))
+ AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io)
def create_programmer(self):
return USBBlaster()
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk50"), 20)
- except ConstraintError:
- pass
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
from mibuild.xilinx.ise import XilinxISEToolchain
-from mibuild.xilinx.common import CRG_DS
_io = [
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
default_clk_period = 6.4
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
- XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io,
- default_crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset"),
- connectors=_connectors,
+ XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
self.programmer = programmer
raise ValueError("{} programmer is not supported".format(programmer))
def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
- except ConstraintError:
- pass
+ XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
_io = [
default_clk_period = 10
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io,
- lambda p: SimpleCRG(p, "clk_y3", "user_btn"))
+ XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io)
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
"""
def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk_y3"), 10)
- except ConstraintError:
- pass
+ XilinxPlatform.do_finalize(self, fragment)
try:
eth_clocks = self.lookup_request("eth_clocks")
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import UrJTAG
default_clk_period = 20
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
- lambda p: SimpleCRG(p, "clk50", None))
+ XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
def create_programmer(self):
return UrJTAG("fjmem-m1.bit")
def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk50"), 20)
- except ConstraintError:
- pass
+ XilinxPlatform.do_finalize(self, fragment)
try:
eth_clocks = self.lookup_request("eth_clocks")
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import UrJTAG
default_clk_period = 20
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
- lambda p: SimpleCRG(p, "clk50", None))
+ XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def create_programmer(self):
return UrJTAG("fjmem-mixxeo.bit")
def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk50"), 20)
- except ConstraintError:
- pass
+ XilinxPlatform.do_finalize(self, fragment)
try:
eth_clocks = self.lookup_request("eth_clocks")
from mibuild.generic_platform import *
-from mibuild.xilinx.common import CRG_DS
from mibuild.xilinx import XilinxPlatform
_io = [
default_clk_period = 5
def __init__(self):
- XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
- lambda p: CRG_DS(p, "clk200", "user_btn"))
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk200").p, 5)
- except ConstraintError:
- pass
+ XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io)
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import XC3SProg
default_clk_period = 31.25
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
- lambda p: SimpleCRG(p, "clk32", None), _connectors)
+ XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors)
def create_programmer(self):
return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit")
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk32"), 31.25)
- except ConstraintError:
- pass
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import XC3SProg
default_clk_period = 20
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io,
- lambda p: SimpleCRG(p, "clk50", None), _connectors)
+ XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
def create_programmer(self):
return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk50"), 20.)
- except ConstraintError:
- pass
from mibuild.generic_platform import *
-from mibuild.xilinx.common import CRG_DS
from mibuild.xilinx import XilinxPlatform
_io = [
default_clk_period = 10
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
- lambda p: CRG_DS(p, "clk100", "gpio"))
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk100").p, 10)
- except ConstraintError:
- pass
+ XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io)
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.sim.verilator import VerilatorPlatform
class SimPins(Pins):
from mibuild.generic_platform import *
-from mibuild.xilinx.common import CRG_DS
from mibuild.xilinx import XilinxPlatform
_io = [
default_clk_period = 15.625
def __init__(self):
- XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
- lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))
+ XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
def do_finalize(self, fragment):
- try:
- self.add_platform_command("""
-NET "{clk64}" TNM_NET = "GRPclk64";
-TIMESPEC "TSclk64" = PERIOD "GRPclk64" 15.625 ns HIGH 50%;
-""", clk64=self.lookup_request("clk64"))
- except ConstraintError:
- pass
+ XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("""
TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
# Bank 34 and 35 voltage depend on J18 jumper setting
default_clk_period = 10
def __init__(self):
- XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io,
- lambda p: SimpleCRG(p, "clk100", None))
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk100"), 10)
- except ConstraintError:
- pass
+ XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io)
from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
from mibuild.xilinx import XilinxPlatform
_io = [
default_clk_period = 20
def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io,
- lambda p: SimpleCRG(p, "clk_if", "rst"))
+ XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io)
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk_if"), 20)
- except ConstraintError:
- pass
+ XilinxPlatform.do_finalize(self, fragment)
try:
clk_if = self.lookup_request("clk_if")
return self.toolchain.build(self, *args, **kwargs)
def add_period_constraint(self, clk, period):
+ if hasattr(clk, "p"):
+ clk = clk.p
self.toolchain.add_period_constraint(self, clk, period)
@staticmethod
def lower(dr):
raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
+
+class CRG(Module):
+ def __init__(self, clk):
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_por = ClockDomain(reset_less=True)
+
+ if hasattr(clk, "p"):
+ clk_se = Signal()
+ self.specials += DifferentialInput(clk.p, clk.n, clk_se)
+ clk = clk_se
+
+ # Power on Reset (vendor agnostic)
+ rst_n = Signal()
+ self.sync.por += rst_n.eq(1)
+ self.comb += [
+ self.cd_sys.clk.eq(clk),
+ self.cd_por.clk.eq(clk),
+ self.cd_sys.rst.eq(~rst_n)
+ ]
projects / litex.git / commitdiff