#define SPI_REG_CTRL_RESET 0x01 /* reset all registers */
#define SPI_REG_CTRL_MANUAL_CS 0x02 /* assert CS, enable manual mode */
#define SPI_REG_CTRL_CKDIV_SHIFT 8 /* clock div */
-#define SPI_REG_CTRL_CKDIV_MASK 0xff
+#define SPI_REG_CTRL_CKDIV_MASK (0xff << SPI_REG_CTRL_CKDIV_SHIFT)
#define SPI_REG_AUTO_CFG 0x08 /* Automatic map configuration */
#define SPI_REG_AUTO_CFG_CMD_SHIFT 0 /* Command to use for reads */
-#define SPI_REG_AUTO_CFG_CMD_MASK 0xff
+#define SPI_REG_AUTO_CFG_CMD_MASK (0xff << SPI_REG_AUTO_CFG_CMD_SHIFT)
#define SPI_REG_AUTO_CFG_DUMMIES_SHIFT 8 /* # dummy cycles */
-#define SPI_REG_AUTO_CFG_DUMMIES_MASK 0x7
+#define SPI_REG_AUTO_CFG_DUMMIES_MASK (0x7 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT)
#define SPI_REG_AUTO_CFG_MODE_SHIFT 11 /* SPI wire mode */
-#define SPI_REG_AUTO_CFG_MODE_MASK 0x3
+#define SPI_REG_AUTO_CFG_MODE_MASK (0x3 << SPI_REG_AUTO_CFG_MODE_SHIFT)
#define SPI_REG_AUT_CFG_MODE_SINGLE (0 << 11)
#define SPI_REG_AUT_CFG_MODE_DUAL (2 << 11)
#define SPI_REG_AUT_CFG_MODE_QUAD (3 << 11)
#define SPI_REG_AUTO_CFG_ADDR4 (1u << 13) /* 3 or 4 addr bytes */
#define SPI_REG_AUTO_CFG_CKDIV_SHIFT 16 /* clock div */
-#define SPI_REG_AUTO_CFG_CKDIV_MASK 0xff
+#define SPI_REG_AUTO_CFG_CKDIV_MASK (0xff << SPI_REG_AUTO_CFG_CKDIV_SHIFT)
+#define SPI_REG_AUTO_CFG_CSTOUT_SHIFT 24 /* CS timeout */
+#define SPI_REG_AUTO_CFG_CSTOUT_MASK (0x3f << SPI_REG_AUTO_CFG_CSTOUT_SHIFT)
#endif /* __MICROWATT_SOC_H */
* limitations under the License.
*/
-#define STACK_TOP 0xf0004000
+#define STACK_TOP 0xff004000
#define FIXUP_ENDIAN \
tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
LOAD_IMM64(%r12, main)
mtctr %r12,
bctrl
- ba 0
+ mtctr %r3
+ bctr
/* XXX: litedram init should not take exceptions, maybe we could get
* rid of these to save space, along with a core tweak to suppress
--- /dev/null
+/*-\r
+ * Copyright (c) 1996-1998 John D. Polstra.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * $FreeBSD$\r
+ */\r
+\r
+#ifndef _SYS_ELF64_H_\r
+#define _SYS_ELF64_H_ 1\r
+\r
+#include <elf_common.h>\r
+\r
+/*\r
+ * ELF definitions common to all 64-bit architectures.\r
+ */\r
+\r
+typedef uint64_t Elf64_Addr;\r
+typedef uint16_t Elf64_Half;\r
+typedef uint64_t Elf64_Off;\r
+typedef int32_t Elf64_Sword;\r
+typedef int64_t Elf64_Sxword;\r
+typedef uint32_t Elf64_Word;\r
+typedef uint64_t Elf64_Lword;\r
+typedef uint64_t Elf64_Xword;\r
+\r
+/*\r
+ * Types of dynamic symbol hash table bucket and chain elements.\r
+ *\r
+ * This is inconsistent among 64 bit architectures, so a machine dependent\r
+ * typedef is required.\r
+ */\r
+\r
+typedef Elf64_Word Elf64_Hashelt;\r
+\r
+/* Non-standard class-dependent datatype used for abstraction. */\r
+typedef Elf64_Xword Elf64_Size;\r
+typedef Elf64_Sxword Elf64_Ssize;\r
+\r
+/*\r
+ * ELF header.\r
+ */\r
+\r
+typedef struct {\r
+ unsigned char e_ident[EI_NIDENT]; /* File identification. */\r
+ Elf64_Half e_type; /* File type. */\r
+ Elf64_Half e_machine; /* Machine architecture. */\r
+ Elf64_Word e_version; /* ELF format version. */\r
+ Elf64_Addr e_entry; /* Entry point. */\r
+ Elf64_Off e_phoff; /* Program header file offset. */\r
+ Elf64_Off e_shoff; /* Section header file offset. */\r
+ Elf64_Word e_flags; /* Architecture-specific flags. */\r
+ Elf64_Half e_ehsize; /* Size of ELF header in bytes. */\r
+ Elf64_Half e_phentsize; /* Size of program header entry. */\r
+ Elf64_Half e_phnum; /* Number of program header entries. */\r
+ Elf64_Half e_shentsize; /* Size of section header entry. */\r
+ Elf64_Half e_shnum; /* Number of section header entries. */\r
+ Elf64_Half e_shstrndx; /* Section name strings section. */\r
+} Elf64_Ehdr;\r
+\r
+/*\r
+ * Section header.\r
+ */\r
+\r
+typedef struct {\r
+ Elf64_Word sh_name; /* Section name (index into the\r
+ section header string table). */\r
+ Elf64_Word sh_type; /* Section type. */\r
+ Elf64_Xword sh_flags; /* Section flags. */\r
+ Elf64_Addr sh_addr; /* Address in memory image. */\r
+ Elf64_Off sh_offset; /* Offset in file. */\r
+ Elf64_Xword sh_size; /* Size in bytes. */\r
+ Elf64_Word sh_link; /* Index of a related section. */\r
+ Elf64_Word sh_info; /* Depends on section type. */\r
+ Elf64_Xword sh_addralign; /* Alignment in bytes. */\r
+ Elf64_Xword sh_entsize; /* Size of each entry in section. */\r
+} Elf64_Shdr;\r
+\r
+/*\r
+ * Program header.\r
+ */\r
+\r
+typedef struct {\r
+ Elf64_Word p_type; /* Entry type. */\r
+ Elf64_Word p_flags; /* Access permission flags. */\r
+ Elf64_Off p_offset; /* File offset of contents. */\r
+ Elf64_Addr p_vaddr; /* Virtual address in memory image. */\r
+ Elf64_Addr p_paddr; /* Physical address (not used). */\r
+ Elf64_Xword p_filesz; /* Size of contents in file. */\r
+ Elf64_Xword p_memsz; /* Size of contents in memory. */\r
+ Elf64_Xword p_align; /* Alignment in memory and file. */\r
+} Elf64_Phdr;\r
+\r
+/*\r
+ * Dynamic structure. The ".dynamic" section contains an array of them.\r
+ */\r
+\r
+typedef struct {\r
+ Elf64_Sxword d_tag; /* Entry type. */\r
+ union {\r
+ Elf64_Xword d_val; /* Integer value. */\r
+ Elf64_Addr d_ptr; /* Address value. */\r
+ } d_un;\r
+} Elf64_Dyn;\r
+\r
+/*\r
+ * Relocation entries.\r
+ */\r
+\r
+/* Relocations that don't need an addend field. */\r
+typedef struct {\r
+ Elf64_Addr r_offset; /* Location to be relocated. */\r
+ Elf64_Xword r_info; /* Relocation type and symbol index. */\r
+} Elf64_Rel;\r
+\r
+/* Relocations that need an addend field. */\r
+typedef struct {\r
+ Elf64_Addr r_offset; /* Location to be relocated. */\r
+ Elf64_Xword r_info; /* Relocation type and symbol index. */\r
+ Elf64_Sxword r_addend; /* Addend. */\r
+} Elf64_Rela;\r
+\r
+/* Macros for accessing the fields of r_info. */\r
+#define ELF64_R_SYM(info) ((info) >> 32)\r
+#define ELF64_R_TYPE(info) ((info) & 0xffffffffL)\r
+\r
+/* Macro for constructing r_info from field values. */\r
+#define ELF64_R_INFO(sym, type) (((sym) << 32) + ((type) & 0xffffffffL))\r
+\r
+#define ELF64_R_TYPE_DATA(info) (((Elf64_Xword)(info)<<32)>>40)\r
+#define ELF64_R_TYPE_ID(info) (((Elf64_Xword)(info)<<56)>>56)\r
+#define ELF64_R_TYPE_INFO(data, type) \\r
+ (((Elf64_Xword)(data)<<8)+(Elf64_Xword)(type))\r
+\r
+/*\r
+ * Note entry header\r
+ */\r
+typedef Elf_Note Elf64_Nhdr;\r
+\r
+/*\r
+ * Move entry\r
+ */\r
+typedef struct {\r
+ Elf64_Lword m_value; /* symbol value */\r
+ Elf64_Xword m_info; /* size + index */\r
+ Elf64_Xword m_poffset; /* symbol offset */\r
+ Elf64_Half m_repeat; /* repeat count */\r
+ Elf64_Half m_stride; /* stride info */\r
+} Elf64_Move;\r
+\r
+#define ELF64_M_SYM(info) ((info)>>8)\r
+#define ELF64_M_SIZE(info) ((unsigned char)(info))\r
+#define ELF64_M_INFO(sym, size) (((sym)<<8)+(unsigned char)(size))\r
+\r
+/*\r
+ * Hardware/Software capabilities entry\r
+ */\r
+typedef struct {\r
+ Elf64_Xword c_tag; /* how to interpret value */\r
+ union {\r
+ Elf64_Xword c_val;\r
+ Elf64_Addr c_ptr;\r
+ } c_un;\r
+} Elf64_Cap;\r
+\r
+/*\r
+ * Symbol table entries.\r
+ */\r
+\r
+typedef struct {\r
+ Elf64_Word st_name; /* String table index of name. */\r
+ unsigned char st_info; /* Type and binding information. */\r
+ unsigned char st_other; /* Reserved (not used). */\r
+ Elf64_Half st_shndx; /* Section index of symbol. */\r
+ Elf64_Addr st_value; /* Symbol value. */\r
+ Elf64_Xword st_size; /* Size of associated object. */\r
+} Elf64_Sym;\r
+\r
+/* Macros for accessing the fields of st_info. */\r
+#define ELF64_ST_BIND(info) ((info) >> 4)\r
+#define ELF64_ST_TYPE(info) ((info) & 0xf)\r
+\r
+/* Macro for constructing st_info from field values. */\r
+#define ELF64_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf))\r
+\r
+/* Macro for accessing the fields of st_other. */\r
+#define ELF64_ST_VISIBILITY(oth) ((oth) & 0x3)\r
+\r
+/* Structures used by Sun & GNU-style symbol versioning. */\r
+typedef struct {\r
+ Elf64_Half vd_version;\r
+ Elf64_Half vd_flags;\r
+ Elf64_Half vd_ndx;\r
+ Elf64_Half vd_cnt;\r
+ Elf64_Word vd_hash;\r
+ Elf64_Word vd_aux;\r
+ Elf64_Word vd_next;\r
+} Elf64_Verdef;\r
+\r
+typedef struct {\r
+ Elf64_Word vda_name;\r
+ Elf64_Word vda_next;\r
+} Elf64_Verdaux;\r
+\r
+typedef struct {\r
+ Elf64_Half vn_version;\r
+ Elf64_Half vn_cnt;\r
+ Elf64_Word vn_file;\r
+ Elf64_Word vn_aux;\r
+ Elf64_Word vn_next;\r
+} Elf64_Verneed;\r
+\r
+typedef struct {\r
+ Elf64_Word vna_hash;\r
+ Elf64_Half vna_flags;\r
+ Elf64_Half vna_other;\r
+ Elf64_Word vna_name;\r
+ Elf64_Word vna_next;\r
+} Elf64_Vernaux;\r
+\r
+typedef Elf64_Half Elf64_Versym;\r
+\r
+typedef struct {\r
+ Elf64_Half si_boundto; /* direct bindings - symbol bound to */\r
+ Elf64_Half si_flags; /* per symbol flags */\r
+} Elf64_Syminfo;\r
+\r
+#endif /* !_SYS_ELF64_H_ */\r
--- /dev/null
+/*-
+ * Copyright (c) 2000, 2001, 2008, 2011, David E. O'Brien
+ * Copyright (c) 1998 John D. Polstra.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _SYS_ELF_COMMON_H_
+#define _SYS_ELF_COMMON_H_ 1
+
+/*
+ * ELF definitions that are independent of architecture or word size.
+ */
+
+/*
+ * Note header. The ".note" section contains an array of notes. Each
+ * begins with this header, aligned to a word boundary. Immediately
+ * following the note header is n_namesz bytes of name, padded to the
+ * next word boundary. Then comes n_descsz bytes of descriptor, again
+ * padded to a word boundary. The values of n_namesz and n_descsz do
+ * not include the padding.
+ */
+
+typedef struct {
+ uint32_t n_namesz; /* Length of name. */
+ uint32_t n_descsz; /* Length of descriptor. */
+ uint32_t n_type; /* Type of this note. */
+} Elf_Note;
+
+/*
+ * The header for GNU-style hash sections.
+ */
+
+typedef struct {
+ uint32_t gh_nbuckets; /* Number of hash buckets. */
+ uint32_t gh_symndx; /* First visible symbol in .dynsym. */
+ uint32_t gh_maskwords; /* #maskwords used in bloom filter. */
+ uint32_t gh_shift2; /* Bloom filter shift count. */
+} Elf_GNU_Hash_Header;
+
+/* Indexes into the e_ident array. Keep synced with
+ http://www.sco.com/developers/gabi/latest/ch4.eheader.html */
+#define EI_MAG0 0 /* Magic number, byte 0. */
+#define EI_MAG1 1 /* Magic number, byte 1. */
+#define EI_MAG2 2 /* Magic number, byte 2. */
+#define EI_MAG3 3 /* Magic number, byte 3. */
+#define EI_CLASS 4 /* Class of machine. */
+#define EI_DATA 5 /* Data format. */
+#define EI_VERSION 6 /* ELF format version. */
+#define EI_OSABI 7 /* Operating system / ABI identification */
+#define EI_ABIVERSION 8 /* ABI version */
+#define OLD_EI_BRAND 8 /* Start of architecture identification. */
+#define EI_PAD 9 /* Start of padding (per SVR4 ABI). */
+#define EI_NIDENT 16 /* Size of e_ident array. */
+
+/* Values for the magic number bytes. */
+#define ELFMAG0 0x7f
+#define ELFMAG1 'E'
+#define ELFMAG2 'L'
+#define ELFMAG3 'F'
+#define ELFMAG "\177ELF" /* magic string */
+#define SELFMAG 4 /* magic string size */
+
+/* Values for e_ident[EI_VERSION] and e_version. */
+#define EV_NONE 0
+#define EV_CURRENT 1
+
+/* Values for e_ident[EI_CLASS]. */
+#define ELFCLASSNONE 0 /* Unknown class. */
+#define ELFCLASS32 1 /* 32-bit architecture. */
+#define ELFCLASS64 2 /* 64-bit architecture. */
+
+/* Values for e_ident[EI_DATA]. */
+#define ELFDATANONE 0 /* Unknown data format. */
+#define ELFDATA2LSB 1 /* 2's complement little-endian. */
+#define ELFDATA2MSB 2 /* 2's complement big-endian. */
+
+/* Values for e_ident[EI_OSABI]. */
+#define ELFOSABI_NONE 0 /* UNIX System V ABI */
+#define ELFOSABI_HPUX 1 /* HP-UX operating system */
+#define ELFOSABI_NETBSD 2 /* NetBSD */
+#define ELFOSABI_LINUX 3 /* GNU/Linux */
+#define ELFOSABI_HURD 4 /* GNU/Hurd */
+#define ELFOSABI_86OPEN 5 /* 86Open common IA32 ABI */
+#define ELFOSABI_SOLARIS 6 /* Solaris */
+#define ELFOSABI_AIX 7 /* AIX */
+#define ELFOSABI_IRIX 8 /* IRIX */
+#define ELFOSABI_FREEBSD 9 /* FreeBSD */
+#define ELFOSABI_TRU64 10 /* TRU64 UNIX */
+#define ELFOSABI_MODESTO 11 /* Novell Modesto */
+#define ELFOSABI_OPENBSD 12 /* OpenBSD */
+#define ELFOSABI_OPENVMS 13 /* Open VMS */
+#define ELFOSABI_NSK 14 /* HP Non-Stop Kernel */
+#define ELFOSABI_AROS 15 /* Amiga Research OS */
+#define ELFOSABI_ARM 97 /* ARM */
+#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */
+
+#define ELFOSABI_SYSV ELFOSABI_NONE /* symbol used in old spec */
+#define ELFOSABI_MONTEREY ELFOSABI_AIX /* Monterey */
+
+/* e_ident */
+#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
+ (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
+ (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
+ (ehdr).e_ident[EI_MAG3] == ELFMAG3)
+
+/* Values for e_type. */
+#define ET_NONE 0 /* Unknown type. */
+#define ET_REL 1 /* Relocatable. */
+#define ET_EXEC 2 /* Executable. */
+#define ET_DYN 3 /* Shared object. */
+#define ET_CORE 4 /* Core file. */
+#define ET_LOOS 0xfe00 /* First operating system specific. */
+#define ET_HIOS 0xfeff /* Last operating system-specific. */
+#define ET_LOPROC 0xff00 /* First processor-specific. */
+#define ET_HIPROC 0xffff /* Last processor-specific. */
+
+/* Values for e_machine. */
+#define EM_NONE 0 /* Unknown machine. */
+#define EM_M32 1 /* AT&T WE32100. */
+#define EM_SPARC 2 /* Sun SPARC. */
+#define EM_386 3 /* Intel i386. */
+#define EM_68K 4 /* Motorola 68000. */
+#define EM_88K 5 /* Motorola 88000. */
+#define EM_860 7 /* Intel i860. */
+#define EM_MIPS 8 /* MIPS R3000 Big-Endian only. */
+#define EM_S370 9 /* IBM System/370. */
+#define EM_MIPS_RS3_LE 10 /* MIPS R3000 Little-Endian. */
+#define EM_PARISC 15 /* HP PA-RISC. */
+#define EM_VPP500 17 /* Fujitsu VPP500. */
+#define EM_SPARC32PLUS 18 /* SPARC v8plus. */
+#define EM_960 19 /* Intel 80960. */
+#define EM_PPC 20 /* PowerPC 32-bit. */
+#define EM_PPC64 21 /* PowerPC 64-bit. */
+#define EM_S390 22 /* IBM System/390. */
+#define EM_V800 36 /* NEC V800. */
+#define EM_FR20 37 /* Fujitsu FR20. */
+#define EM_RH32 38 /* TRW RH-32. */
+#define EM_RCE 39 /* Motorola RCE. */
+#define EM_ARM 40 /* ARM. */
+#define EM_SH 42 /* Hitachi SH. */
+#define EM_SPARCV9 43 /* SPARC v9 64-bit. */
+#define EM_TRICORE 44 /* Siemens TriCore embedded processor. */
+#define EM_ARC 45 /* Argonaut RISC Core. */
+#define EM_H8_300 46 /* Hitachi H8/300. */
+#define EM_H8_300H 47 /* Hitachi H8/300H. */
+#define EM_H8S 48 /* Hitachi H8S. */
+#define EM_H8_500 49 /* Hitachi H8/500. */
+#define EM_IA_64 50 /* Intel IA-64 Processor. */
+#define EM_MIPS_X 51 /* Stanford MIPS-X. */
+#define EM_COLDFIRE 52 /* Motorola ColdFire. */
+#define EM_68HC12 53 /* Motorola M68HC12. */
+#define EM_MMA 54 /* Fujitsu MMA. */
+#define EM_PCP 55 /* Siemens PCP. */
+#define EM_NCPU 56 /* Sony nCPU. */
+#define EM_NDR1 57 /* Denso NDR1 microprocessor. */
+#define EM_STARCORE 58 /* Motorola Star*Core processor. */
+#define EM_ME16 59 /* Toyota ME16 processor. */
+#define EM_ST100 60 /* STMicroelectronics ST100 processor. */
+#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ processor. */
+#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
+#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
+#define EM_PDSP 63 /* Sony DSP Processor. */
+#define EM_FX66 66 /* Siemens FX66 microcontroller. */
+#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16
+ microcontroller. */
+#define EM_ST7 68 /* STmicroelectronics ST7 8-bit
+ microcontroller. */
+#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller. */
+#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller. */
+#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller. */
+#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller. */
+#define EM_SVX 73 /* Silicon Graphics SVx. */
+#define EM_ST19 74 /* STMicroelectronics ST19 8-bit mc. */
+#define EM_VAX 75 /* Digital VAX. */
+#define EM_CRIS 76 /* Axis Communications 32-bit embedded
+ processor. */
+#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded
+ processor. */
+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor. */
+#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor. */
+#define EM_MMIX 80 /* Donald Knuth's educational 64-bit proc. */
+#define EM_HUANY 81 /* Harvard University machine-independent
+ object files. */
+#define EM_PRISM 82 /* SiTera Prism. */
+#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller. */
+#define EM_FR30 84 /* Fujitsu FR30. */
+#define EM_D10V 85 /* Mitsubishi D10V. */
+#define EM_D30V 86 /* Mitsubishi D30V. */
+#define EM_V850 87 /* NEC v850. */
+#define EM_M32R 88 /* Mitsubishi M32R. */
+#define EM_MN10300 89 /* Matsushita MN10300. */
+#define EM_MN10200 90 /* Matsushita MN10200. */
+#define EM_PJ 91 /* picoJava. */
+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor. */
+#define EM_ARC_A5 93 /* ARC Cores Tangent-A5. */
+#define EM_XTENSA 94 /* Tensilica Xtensa Architecture. */
+#define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor. */
+#define EM_TMM_GPP 96 /* Thompson Multimedia General Purpose
+ Processor. */
+#define EM_NS32K 97 /* National Semiconductor 32000 series. */
+#define EM_TPC 98 /* Tenor Network TPC processor. */
+#define EM_SNP1K 99 /* Trebia SNP 1000 processor. */
+#define EM_ST200 100 /* STMicroelectronics ST200 microcontroller. */
+#define EM_IP2K 101 /* Ubicom IP2xxx microcontroller family. */
+#define EM_MAX 102 /* MAX Processor. */
+#define EM_CR 103 /* National Semiconductor CompactRISC
+ microprocessor. */
+#define EM_F2MC16 104 /* Fujitsu F2MC16. */
+#define EM_MSP430 105 /* Texas Instruments embedded microcontroller
+ msp430. */
+#define EM_BLACKFIN 106 /* Analog Devices Blackfin (DSP) processor. */
+#define EM_SE_C33 107 /* S1C33 Family of Seiko Epson processors. */
+#define EM_SEP 108 /* Sharp embedded microprocessor. */
+#define EM_ARCA 109 /* Arca RISC Microprocessor. */
+#define EM_UNICORE 110 /* Microprocessor series from PKU-Unity Ltd.
+ and MPRC of Peking University */
+
+/* Non-standard or deprecated. */
+#define EM_486 6 /* Intel i486. */
+#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */
+#define EM_ALPHA_STD 41 /* Digital Alpha (standard value). */
+#define EM_ALPHA 0x9026 /* Alpha (written in the absence of an ABI) */
+
+/* Special section indexes. */
+#define SHN_UNDEF 0 /* Undefined, missing, irrelevant. */
+#define SHN_LORESERVE 0xff00 /* First of reserved range. */
+#define SHN_LOPROC 0xff00 /* First processor-specific. */
+#define SHN_HIPROC 0xff1f /* Last processor-specific. */
+#define SHN_LOOS 0xff20 /* First operating system-specific. */
+#define SHN_HIOS 0xff3f /* Last operating system-specific. */
+#define SHN_ABS 0xfff1 /* Absolute values. */
+#define SHN_COMMON 0xfff2 /* Common data. */
+#define SHN_XINDEX 0xffff /* Escape -- index stored elsewhere. */
+#define SHN_HIRESERVE 0xffff /* Last of reserved range. */
+
+/* sh_type */
+#define SHT_NULL 0 /* inactive */
+#define SHT_PROGBITS 1 /* program defined information */
+#define SHT_SYMTAB 2 /* symbol table section */
+#define SHT_STRTAB 3 /* string table section */
+#define SHT_RELA 4 /* relocation section with addends */
+#define SHT_HASH 5 /* symbol hash table section */
+#define SHT_DYNAMIC 6 /* dynamic section */
+#define SHT_NOTE 7 /* note section */
+#define SHT_NOBITS 8 /* no space section */
+#define SHT_REL 9 /* relocation section - no addends */
+#define SHT_SHLIB 10 /* reserved - purpose unknown */
+#define SHT_DYNSYM 11 /* dynamic symbol table section */
+#define SHT_INIT_ARRAY 14 /* Initialization function pointers. */
+#define SHT_FINI_ARRAY 15 /* Termination function pointers. */
+#define SHT_PREINIT_ARRAY 16 /* Pre-initialization function ptrs. */
+#define SHT_GROUP 17 /* Section group. */
+#define SHT_SYMTAB_SHNDX 18 /* Section indexes (see SHN_XINDEX). */
+#define SHT_LOOS 0x60000000 /* First of OS specific semantics */
+#define SHT_LOSUNW 0x6ffffff4
+#define SHT_SUNW_dof 0x6ffffff4
+#define SHT_SUNW_cap 0x6ffffff5
+#define SHT_SUNW_SIGNATURE 0x6ffffff6
+#define SHT_GNU_HASH 0x6ffffff6
+#define SHT_SUNW_ANNOTATE 0x6ffffff7
+#define SHT_SUNW_DEBUGSTR 0x6ffffff8
+#define SHT_SUNW_DEBUG 0x6ffffff9
+#define SHT_SUNW_move 0x6ffffffa
+#define SHT_SUNW_COMDAT 0x6ffffffb
+#define SHT_SUNW_syminfo 0x6ffffffc
+#define SHT_SUNW_verdef 0x6ffffffd
+#define SHT_GNU_verdef 0x6ffffffd /* Symbol versions provided */
+#define SHT_SUNW_verneed 0x6ffffffe
+#define SHT_GNU_verneed 0x6ffffffe /* Symbol versions required */
+#define SHT_SUNW_versym 0x6fffffff
+#define SHT_GNU_versym 0x6fffffff /* Symbol version table */
+#define SHT_HISUNW 0x6fffffff
+#define SHT_HIOS 0x6fffffff /* Last of OS specific semantics */
+#define SHT_LOPROC 0x70000000 /* reserved range for processor */
+#define SHT_AMD64_UNWIND 0x70000001 /* unwind information */
+#define SHT_ARM_EXIDX 0x70000001 /* Exception index table. */
+#define SHT_ARM_PREEMPTMAP 0x70000002 /* BPABI DLL dynamic linking
+ pre-emption map. */
+#define SHT_ARM_ATTRIBUTES 0x70000003 /* Object file compatibility
+ attributes. */
+#define SHT_ARM_DEBUGOVERLAY 0x70000004 /* See DBGOVL for details. */
+#define SHT_ARM_OVERLAYSECTION 0x70000005 /* See DBGOVL for details. */
+#define SHT_MIPS_REGINFO 0x70000006
+#define SHT_MIPS_OPTIONS 0x7000000d
+#define SHT_MIPS_DWARF 0x7000001e /* MIPS gcc uses MIPS_DWARF */
+#define SHT_HIPROC 0x7fffffff /* specific section header types */
+#define SHT_LOUSER 0x80000000 /* reserved range for application */
+#define SHT_HIUSER 0xffffffff /* specific indexes */
+
+/* Flags for sh_flags. */
+#define SHF_WRITE 0x1 /* Section contains writable data. */
+#define SHF_ALLOC 0x2 /* Section occupies memory. */
+#define SHF_EXECINSTR 0x4 /* Section contains instructions. */
+#define SHF_MERGE 0x10 /* Section may be merged. */
+#define SHF_STRINGS 0x20 /* Section contains strings. */
+#define SHF_INFO_LINK 0x40 /* sh_info holds section index. */
+#define SHF_LINK_ORDER 0x80 /* Special ordering requirements. */
+#define SHF_OS_NONCONFORMING 0x100 /* OS-specific processing required. */
+#define SHF_GROUP 0x200 /* Member of section group. */
+#define SHF_TLS 0x400 /* Section contains TLS data. */
+#define SHF_MASKOS 0x0ff00000 /* OS-specific semantics. */
+#define SHF_MASKPROC 0xf0000000 /* Processor-specific semantics. */
+
+/* Values for p_type. */
+#define PT_NULL 0 /* Unused entry. */
+#define PT_LOAD 1 /* Loadable segment. */
+#define PT_DYNAMIC 2 /* Dynamic linking information segment. */
+#define PT_INTERP 3 /* Pathname of interpreter. */
+#define PT_NOTE 4 /* Auxiliary information. */
+#define PT_SHLIB 5 /* Reserved (not used). */
+#define PT_PHDR 6 /* Location of program header itself. */
+#define PT_TLS 7 /* Thread local storage segment */
+#define PT_LOOS 0x60000000 /* First OS-specific. */
+#define PT_SUNW_UNWIND 0x6464e550 /* amd64 UNWIND program header */
+#define PT_GNU_EH_FRAME 0x6474e550
+#define PT_GNU_STACK 0x6474e551
+#define PT_GNU_RELRO 0x6474e552
+#define PT_LOSUNW 0x6ffffffa
+#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */
+#define PT_SUNWSTACK 0x6ffffffb /* describes the stack segment */
+#define PT_SUNWDTRACE 0x6ffffffc /* private */
+#define PT_SUNWCAP 0x6ffffffd /* hard/soft capabilities segment */
+#define PT_HISUNW 0x6fffffff
+#define PT_HIOS 0x6fffffff /* Last OS-specific. */
+#define PT_LOPROC 0x70000000 /* First processor-specific type. */
+#define PT_HIPROC 0x7fffffff /* Last processor-specific type. */
+
+/* Values for p_flags. */
+#define PF_X 0x1 /* Executable. */
+#define PF_W 0x2 /* Writable. */
+#define PF_R 0x4 /* Readable. */
+#define PF_MASKOS 0x0ff00000 /* Operating system-specific. */
+#define PF_MASKPROC 0xf0000000 /* Processor-specific. */
+
+/* Extended program header index. */
+#define PN_XNUM 0xffff
+
+/* Values for d_tag. */
+#define DT_NULL 0 /* Terminating entry. */
+#define DT_NEEDED 1 /* String table offset of a needed shared
+ library. */
+#define DT_PLTRELSZ 2 /* Total size in bytes of PLT relocations. */
+#define DT_PLTGOT 3 /* Processor-dependent address. */
+#define DT_HASH 4 /* Address of symbol hash table. */
+#define DT_STRTAB 5 /* Address of string table. */
+#define DT_SYMTAB 6 /* Address of symbol table. */
+#define DT_RELA 7 /* Address of ElfNN_Rela relocations. */
+#define DT_RELASZ 8 /* Total size of ElfNN_Rela relocations. */
+#define DT_RELAENT 9 /* Size of each ElfNN_Rela relocation entry. */
+#define DT_STRSZ 10 /* Size of string table. */
+#define DT_SYMENT 11 /* Size of each symbol table entry. */
+#define DT_INIT 12 /* Address of initialization function. */
+#define DT_FINI 13 /* Address of finalization function. */
+#define DT_SONAME 14 /* String table offset of shared object
+ name. */
+#define DT_RPATH 15 /* String table offset of library path. [sup] */
+#define DT_SYMBOLIC 16 /* Indicates "symbolic" linking. [sup] */
+#define DT_REL 17 /* Address of ElfNN_Rel relocations. */
+#define DT_RELSZ 18 /* Total size of ElfNN_Rel relocations. */
+#define DT_RELENT 19 /* Size of each ElfNN_Rel relocation. */
+#define DT_PLTREL 20 /* Type of relocation used for PLT. */
+#define DT_DEBUG 21 /* Reserved (not used). */
+#define DT_TEXTREL 22 /* Indicates there may be relocations in
+ non-writable segments. [sup] */
+#define DT_JMPREL 23 /* Address of PLT relocations. */
+#define DT_BIND_NOW 24 /* [sup] */
+#define DT_INIT_ARRAY 25 /* Address of the array of pointers to
+ initialization functions */
+#define DT_FINI_ARRAY 26 /* Address of the array of pointers to
+ termination functions */
+#define DT_INIT_ARRAYSZ 27 /* Size in bytes of the array of
+ initialization functions. */
+#define DT_FINI_ARRAYSZ 28 /* Size in bytes of the array of
+ termination functions. */
+#define DT_RUNPATH 29 /* String table offset of a null-terminated
+ library search path string. */
+#define DT_FLAGS 30 /* Object specific flag values. */
+#define DT_ENCODING 32 /* Values greater than or equal to DT_ENCODING
+ and less than DT_LOOS follow the rules for
+ the interpretation of the d_un union
+ as follows: even == 'd_ptr', odd == 'd_val'
+ or none */
+#define DT_PREINIT_ARRAY 32 /* Address of the array of pointers to
+ pre-initialization functions. */
+#define DT_PREINIT_ARRAYSZ 33 /* Size in bytes of the array of
+ pre-initialization functions. */
+#define DT_MAXPOSTAGS 34 /* number of positive tags */
+#define DT_LOOS 0x6000000d /* First OS-specific */
+#define DT_SUNW_AUXILIARY 0x6000000d /* symbol auxiliary name */
+#define DT_SUNW_RTLDINF 0x6000000e /* ld.so.1 info (private) */
+#define DT_SUNW_FILTER 0x6000000f /* symbol filter name */
+#define DT_SUNW_CAP 0x60000010 /* hardware/software */
+#define DT_HIOS 0x6ffff000 /* Last OS-specific */
+
+/*
+ * DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
+ * Dyn.d_un.d_val field of the Elf*_Dyn structure.
+ */
+#define DT_VALRNGLO 0x6ffffd00
+#define DT_CHECKSUM 0x6ffffdf8 /* elf checksum */
+#define DT_PLTPADSZ 0x6ffffdf9 /* pltpadding size */
+#define DT_MOVEENT 0x6ffffdfa /* move table entry size */
+#define DT_MOVESZ 0x6ffffdfb /* move table size */
+#define DT_FEATURE_1 0x6ffffdfc /* feature holder */
+#define DT_POSFLAG_1 0x6ffffdfd /* flags for DT_* entries, effecting */
+ /* the following DT_* entry. */
+ /* See DF_P1_* definitions */
+#define DT_SYMINSZ 0x6ffffdfe /* syminfo table size (in bytes) */
+#define DT_SYMINENT 0x6ffffdff /* syminfo entry size (in bytes) */
+#define DT_VALRNGHI 0x6ffffdff
+
+/*
+ * DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
+ * Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
+ *
+ * If any adjustment is made to the ELF object after it has been
+ * built, these entries will need to be adjusted.
+ */
+#define DT_ADDRRNGLO 0x6ffffe00
+#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table */
+#define DT_CONFIG 0x6ffffefa /* configuration information */
+#define DT_DEPAUDIT 0x6ffffefb /* dependency auditing */
+#define DT_AUDIT 0x6ffffefc /* object auditing */
+#define DT_PLTPAD 0x6ffffefd /* pltpadding (sparcv9) */
+#define DT_MOVETAB 0x6ffffefe /* move table */
+#define DT_SYMINFO 0x6ffffeff /* syminfo table */
+#define DT_ADDRRNGHI 0x6ffffeff
+
+#define DT_VERSYM 0x6ffffff0 /* Address of versym section. */
+#define DT_RELACOUNT 0x6ffffff9 /* number of RELATIVE relocations */
+#define DT_RELCOUNT 0x6ffffffa /* number of RELATIVE relocations */
+#define DT_FLAGS_1 0x6ffffffb /* state flags - see DF_1_* defs */
+#define DT_VERDEF 0x6ffffffc /* Address of verdef section. */
+#define DT_VERDEFNUM 0x6ffffffd /* Number of elems in verdef section */
+#define DT_VERNEED 0x6ffffffe /* Address of verneed section. */
+#define DT_VERNEEDNUM 0x6fffffff /* Number of elems in verneed section */
+
+#define DT_LOPROC 0x70000000 /* First processor-specific type. */
+#define DT_DEPRECATED_SPARC_REGISTER 0x7000001
+#define DT_AUXILIARY 0x7ffffffd /* shared library auxiliary name */
+#define DT_USED 0x7ffffffe /* ignored - same as needed */
+#define DT_FILTER 0x7fffffff /* shared library filter name */
+#define DT_HIPROC 0x7fffffff /* Last processor-specific type. */
+
+/* Values for DT_FLAGS */
+#define DF_ORIGIN 0x0001 /* Indicates that the object being loaded may
+ make reference to the $ORIGIN substitution
+ string */
+#define DF_SYMBOLIC 0x0002 /* Indicates "symbolic" linking. */
+#define DF_TEXTREL 0x0004 /* Indicates there may be relocations in
+ non-writable segments. */
+#define DF_BIND_NOW 0x0008 /* Indicates that the dynamic linker should
+ process all relocations for the object
+ containing this entry before transferring
+ control to the program. */
+#define DF_STATIC_TLS 0x0010 /* Indicates that the shared object or
+ executable contains code using a static
+ thread-local storage scheme. */
+
+/* Values for DT_FLAGS_1 */
+#define DF_1_BIND_NOW 0x00000001 /* Same as DF_BIND_NOW */
+#define DF_1_GLOBAL 0x00000002 /* Set the RTLD_GLOBAL for object */
+#define DF_1_NODELETE 0x00000008 /* Set the RTLD_NODELETE for object */
+#define DF_1_LOADFLTR 0x00000010 /* Immediate loading of filtees */
+#define DF_1_NOOPEN 0x00000040 /* Do not allow loading on dlopen() */
+#define DF_1_ORIGIN 0x00000080 /* Process $ORIGIN */
+#define DF_1_INTERPOSE 0x00000400 /* Interpose all objects but main */
+#define DF_1_NODEFLIB 0x00000800 /* Do not search default paths */
+
+/* Values for n_type. Used in core files. */
+#define NT_PRSTATUS 1 /* Process status. */
+#define NT_FPREGSET 2 /* Floating point registers. */
+#define NT_PRPSINFO 3 /* Process state info. */
+#define NT_THRMISC 7 /* Thread miscellaneous info. */
+#define NT_PROCSTAT_PROC 8 /* Procstat proc data. */
+#define NT_PROCSTAT_FILES 9 /* Procstat files data. */
+#define NT_PROCSTAT_VMMAP 10 /* Procstat vmmap data. */
+#define NT_PROCSTAT_GROUPS 11 /* Procstat groups data. */
+#define NT_PROCSTAT_UMASK 12 /* Procstat umask data. */
+#define NT_PROCSTAT_RLIMIT 13 /* Procstat rlimit data. */
+#define NT_PROCSTAT_OSREL 14 /* Procstat osreldate data. */
+#define NT_PROCSTAT_PSSTRINGS 15 /* Procstat ps_strings data. */
+#define NT_PROCSTAT_AUXV 16 /* Procstat auxv data. */
+
+/* Symbol Binding - ELFNN_ST_BIND - st_info */
+#define STB_LOCAL 0 /* Local symbol */
+#define STB_GLOBAL 1 /* Global symbol */
+#define STB_WEAK 2 /* like global - lower precedence */
+#define STB_LOOS 10 /* Reserved range for operating system */
+#define STB_HIOS 12 /* specific semantics. */
+#define STB_LOPROC 13 /* reserved range for processor */
+#define STB_HIPROC 15 /* specific semantics. */
+
+/* Symbol type - ELFNN_ST_TYPE - st_info */
+#define STT_NOTYPE 0 /* Unspecified type. */
+#define STT_OBJECT 1 /* Data object. */
+#define STT_FUNC 2 /* Function. */
+#define STT_SECTION 3 /* Section. */
+#define STT_FILE 4 /* Source file. */
+#define STT_COMMON 5 /* Uninitialized common block. */
+#define STT_TLS 6 /* TLS object. */
+#define STT_NUM 7
+#define STT_LOOS 10 /* Reserved range for operating system */
+#define STT_GNU_IFUNC 10
+#define STT_HIOS 12 /* specific semantics. */
+#define STT_LOPROC 13 /* reserved range for processor */
+#define STT_HIPROC 15 /* specific semantics. */
+
+/* Symbol visibility - ELFNN_ST_VISIBILITY - st_other */
+#define STV_DEFAULT 0x0 /* Default visibility (see binding). */
+#define STV_INTERNAL 0x1 /* Special meaning in relocatable objects. */
+#define STV_HIDDEN 0x2 /* Not visible. */
+#define STV_PROTECTED 0x3 /* Visible but not preemptible. */
+#define STV_EXPORTED 0x4
+#define STV_SINGLETON 0x5
+#define STV_ELIMINATE 0x6
+
+/* Special symbol table indexes. */
+#define STN_UNDEF 0 /* Undefined symbol index. */
+
+/* Symbol versioning flags. */
+#define VER_DEF_CURRENT 1
+#define VER_DEF_IDX(x) VER_NDX(x)
+
+#define VER_FLG_BASE 0x01
+#define VER_FLG_WEAK 0x02
+
+#define VER_NEED_CURRENT 1
+#define VER_NEED_WEAK (1u << 15)
+#define VER_NEED_HIDDEN VER_NDX_HIDDEN
+#define VER_NEED_IDX(x) VER_NDX(x)
+
+#define VER_NDX_LOCAL 0
+#define VER_NDX_GLOBAL 1
+#define VER_NDX_GIVEN 2
+
+#define VER_NDX_HIDDEN (1u << 15)
+#define VER_NDX(x) ((x) & ~(1u << 15))
+
+#define CA_SUNW_NULL 0
+#define CA_SUNW_HW_1 1 /* first hardware capabilities entry */
+#define CA_SUNW_SF_1 2 /* first software capabilities entry */
+
+/*
+ * Syminfo flag values
+ */
+#define SYMINFO_FLG_DIRECT 0x0001 /* symbol ref has direct association */
+ /* to object containing defn. */
+#define SYMINFO_FLG_PASSTHRU 0x0002 /* ignored - see SYMINFO_FLG_FILTER */
+#define SYMINFO_FLG_COPY 0x0004 /* symbol is a copy-reloc */
+#define SYMINFO_FLG_LAZYLOAD 0x0008 /* object containing defn should be */
+ /* lazily-loaded */
+#define SYMINFO_FLG_DIRECTBIND 0x0010 /* ref should be bound directly to */
+ /* object containing defn. */
+#define SYMINFO_FLG_NOEXTDIRECT 0x0020 /* don't let an external reference */
+ /* directly bind to this symbol */
+#define SYMINFO_FLG_FILTER 0x0002 /* symbol ref is associated to a */
+#define SYMINFO_FLG_AUXILIARY 0x0040 /* standard or auxiliary filter */
+
+/*
+ * Syminfo.si_boundto values.
+ */
+#define SYMINFO_BT_SELF 0xffff /* symbol bound to self */
+#define SYMINFO_BT_PARENT 0xfffe /* symbol bound to parent */
+#define SYMINFO_BT_NONE 0xfffd /* no special symbol binding */
+#define SYMINFO_BT_EXTERN 0xfffc /* symbol defined as external */
+#define SYMINFO_BT_LOWRESERVE 0xff00 /* beginning of reserved entries */
+
+/*
+ * Syminfo version values.
+ */
+#define SYMINFO_NONE 0 /* Syminfo version */
+#define SYMINFO_CURRENT 1
+#define SYMINFO_NUM 2
+
+/*
+ * Relocation types.
+ *
+ * All machine architectures are defined here to allow tools on one to
+ * handle others.
+ */
+
+#define R_386_NONE 0 /* No relocation. */
+#define R_386_32 1 /* Add symbol value. */
+#define R_386_PC32 2 /* Add PC-relative symbol value. */
+#define R_386_GOT32 3 /* Add PC-relative GOT offset. */
+#define R_386_PLT32 4 /* Add PC-relative PLT offset. */
+#define R_386_COPY 5 /* Copy data from shared object. */
+#define R_386_GLOB_DAT 6 /* Set GOT entry to data address. */
+#define R_386_JMP_SLOT 7 /* Set GOT entry to code address. */
+#define R_386_RELATIVE 8 /* Add load address of shared object. */
+#define R_386_GOTOFF 9 /* Add GOT-relative symbol address. */
+#define R_386_GOTPC 10 /* Add PC-relative GOT table address. */
+#define R_386_TLS_TPOFF 14 /* Negative offset in static TLS block */
+#define R_386_TLS_IE 15 /* Absolute address of GOT for -ve static TLS */
+#define R_386_TLS_GOTIE 16 /* GOT entry for negative static TLS block */
+#define R_386_TLS_LE 17 /* Negative offset relative to static TLS */
+#define R_386_TLS_GD 18 /* 32 bit offset to GOT (index,off) pair */
+#define R_386_TLS_LDM 19 /* 32 bit offset to GOT (index,zero) pair */
+#define R_386_TLS_GD_32 24 /* 32 bit offset to GOT (index,off) pair */
+#define R_386_TLS_GD_PUSH 25 /* pushl instruction for Sun ABI GD sequence */
+#define R_386_TLS_GD_CALL 26 /* call instruction for Sun ABI GD sequence */
+#define R_386_TLS_GD_POP 27 /* popl instruction for Sun ABI GD sequence */
+#define R_386_TLS_LDM_32 28 /* 32 bit offset to GOT (index,zero) pair */
+#define R_386_TLS_LDM_PUSH 29 /* pushl instruction for Sun ABI LD sequence */
+#define R_386_TLS_LDM_CALL 30 /* call instruction for Sun ABI LD sequence */
+#define R_386_TLS_LDM_POP 31 /* popl instruction for Sun ABI LD sequence */
+#define R_386_TLS_LDO_32 32 /* 32 bit offset from start of TLS block */
+#define R_386_TLS_IE_32 33 /* 32 bit offset to GOT static TLS offset entry */
+#define R_386_TLS_LE_32 34 /* 32 bit offset within static TLS block */
+#define R_386_TLS_DTPMOD32 35 /* GOT entry containing TLS index */
+#define R_386_TLS_DTPOFF32 36 /* GOT entry containing TLS offset */
+#define R_386_TLS_TPOFF32 37 /* GOT entry of -ve static TLS offset */
+#define R_386_IRELATIVE 42 /* PLT entry resolved indirectly at runtime */
+
+#define R_ARM_NONE 0 /* No relocation. */
+#define R_ARM_PC24 1
+#define R_ARM_ABS32 2
+#define R_ARM_REL32 3
+#define R_ARM_PC13 4
+#define R_ARM_ABS16 5
+#define R_ARM_ABS12 6
+#define R_ARM_THM_ABS5 7
+#define R_ARM_ABS8 8
+#define R_ARM_SBREL32 9
+#define R_ARM_THM_PC22 10
+#define R_ARM_THM_PC8 11
+#define R_ARM_AMP_VCALL9 12
+#define R_ARM_SWI24 13
+#define R_ARM_THM_SWI8 14
+#define R_ARM_XPC25 15
+#define R_ARM_THM_XPC22 16
+/* TLS relocations */
+#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */
+#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */
+#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */
+#define R_ARM_COPY 20 /* Copy data from shared object. */
+#define R_ARM_GLOB_DAT 21 /* Set GOT entry to data address. */
+#define R_ARM_JUMP_SLOT 22 /* Set GOT entry to code address. */
+#define R_ARM_RELATIVE 23 /* Add load address of shared object. */
+#define R_ARM_GOTOFF 24 /* Add GOT-relative symbol address. */
+#define R_ARM_GOTPC 25 /* Add PC-relative GOT table address. */
+#define R_ARM_GOT32 26 /* Add PC-relative GOT offset. */
+#define R_ARM_PLT32 27 /* Add PC-relative PLT offset. */
+#define R_ARM_GNU_VTENTRY 100
+#define R_ARM_GNU_VTINHERIT 101
+#define R_ARM_RSBREL32 250
+#define R_ARM_THM_RPC22 251
+#define R_ARM_RREL32 252
+#define R_ARM_RABS32 253
+#define R_ARM_RPC24 254
+#define R_ARM_RBASE 255
+
+/* Name Value Field Calculation */
+#define R_IA_64_NONE 0 /* None */
+#define R_IA_64_IMM14 0x21 /* immediate14 S + A */
+#define R_IA_64_IMM22 0x22 /* immediate22 S + A */
+#define R_IA_64_IMM64 0x23 /* immediate64 S + A */
+#define R_IA_64_DIR32MSB 0x24 /* word32 MSB S + A */
+#define R_IA_64_DIR32LSB 0x25 /* word32 LSB S + A */
+#define R_IA_64_DIR64MSB 0x26 /* word64 MSB S + A */
+#define R_IA_64_DIR64LSB 0x27 /* word64 LSB S + A */
+#define R_IA_64_GPREL22 0x2a /* immediate22 @gprel(S + A) */
+#define R_IA_64_GPREL64I 0x2b /* immediate64 @gprel(S + A) */
+#define R_IA_64_GPREL32MSB 0x2c /* word32 MSB @gprel(S + A) */
+#define R_IA_64_GPREL32LSB 0x2d /* word32 LSB @gprel(S + A) */
+#define R_IA_64_GPREL64MSB 0x2e /* word64 MSB @gprel(S + A) */
+#define R_IA_64_GPREL64LSB 0x2f /* word64 LSB @gprel(S + A) */
+#define R_IA_64_LTOFF22 0x32 /* immediate22 @ltoff(S + A) */
+#define R_IA_64_LTOFF64I 0x33 /* immediate64 @ltoff(S + A) */
+#define R_IA_64_PLTOFF22 0x3a /* immediate22 @pltoff(S + A) */
+#define R_IA_64_PLTOFF64I 0x3b /* immediate64 @pltoff(S + A) */
+#define R_IA_64_PLTOFF64MSB 0x3e /* word64 MSB @pltoff(S + A) */
+#define R_IA_64_PLTOFF64LSB 0x3f /* word64 LSB @pltoff(S + A) */
+#define R_IA_64_FPTR64I 0x43 /* immediate64 @fptr(S + A) */
+#define R_IA_64_FPTR32MSB 0x44 /* word32 MSB @fptr(S + A) */
+#define R_IA_64_FPTR32LSB 0x45 /* word32 LSB @fptr(S + A) */
+#define R_IA_64_FPTR64MSB 0x46 /* word64 MSB @fptr(S + A) */
+#define R_IA_64_FPTR64LSB 0x47 /* word64 LSB @fptr(S + A) */
+#define R_IA_64_PCREL60B 0x48 /* immediate60 form1 S + A - P */
+#define R_IA_64_PCREL21B 0x49 /* immediate21 form1 S + A - P */
+#define R_IA_64_PCREL21M 0x4a /* immediate21 form2 S + A - P */
+#define R_IA_64_PCREL21F 0x4b /* immediate21 form3 S + A - P */
+#define R_IA_64_PCREL32MSB 0x4c /* word32 MSB S + A - P */
+#define R_IA_64_PCREL32LSB 0x4d /* word32 LSB S + A - P */
+#define R_IA_64_PCREL64MSB 0x4e /* word64 MSB S + A - P */
+#define R_IA_64_PCREL64LSB 0x4f /* word64 LSB S + A - P */
+#define R_IA_64_LTOFF_FPTR22 0x52 /* immediate22 @ltoff(@fptr(S + A)) */
+#define R_IA_64_LTOFF_FPTR64I 0x53 /* immediate64 @ltoff(@fptr(S + A)) */
+#define R_IA_64_LTOFF_FPTR32MSB 0x54 /* word32 MSB @ltoff(@fptr(S + A)) */
+#define R_IA_64_LTOFF_FPTR32LSB 0x55 /* word32 LSB @ltoff(@fptr(S + A)) */
+#define R_IA_64_LTOFF_FPTR64MSB 0x56 /* word64 MSB @ltoff(@fptr(S + A)) */
+#define R_IA_64_LTOFF_FPTR64LSB 0x57 /* word64 LSB @ltoff(@fptr(S + A)) */
+#define R_IA_64_SEGREL32MSB 0x5c /* word32 MSB @segrel(S + A) */
+#define R_IA_64_SEGREL32LSB 0x5d /* word32 LSB @segrel(S + A) */
+#define R_IA_64_SEGREL64MSB 0x5e /* word64 MSB @segrel(S + A) */
+#define R_IA_64_SEGREL64LSB 0x5f /* word64 LSB @segrel(S + A) */
+#define R_IA_64_SECREL32MSB 0x64 /* word32 MSB @secrel(S + A) */
+#define R_IA_64_SECREL32LSB 0x65 /* word32 LSB @secrel(S + A) */
+#define R_IA_64_SECREL64MSB 0x66 /* word64 MSB @secrel(S + A) */
+#define R_IA_64_SECREL64LSB 0x67 /* word64 LSB @secrel(S + A) */
+#define R_IA_64_REL32MSB 0x6c /* word32 MSB BD + A */
+#define R_IA_64_REL32LSB 0x6d /* word32 LSB BD + A */
+#define R_IA_64_REL64MSB 0x6e /* word64 MSB BD + A */
+#define R_IA_64_REL64LSB 0x6f /* word64 LSB BD + A */
+#define R_IA_64_LTV32MSB 0x74 /* word32 MSB S + A */
+#define R_IA_64_LTV32LSB 0x75 /* word32 LSB S + A */
+#define R_IA_64_LTV64MSB 0x76 /* word64 MSB S + A */
+#define R_IA_64_LTV64LSB 0x77 /* word64 LSB S + A */
+#define R_IA_64_PCREL21BI 0x79 /* immediate21 form1 S + A - P */
+#define R_IA_64_PCREL22 0x7a /* immediate22 S + A - P */
+#define R_IA_64_PCREL64I 0x7b /* immediate64 S + A - P */
+#define R_IA_64_IPLTMSB 0x80 /* function descriptor MSB special */
+#define R_IA_64_IPLTLSB 0x81 /* function descriptor LSB speciaal */
+#define R_IA_64_SUB 0x85 /* immediate64 A - S */
+#define R_IA_64_LTOFF22X 0x86 /* immediate22 special */
+#define R_IA_64_LDXMOV 0x87 /* immediate22 special */
+#define R_IA_64_TPREL14 0x91 /* imm14 @tprel(S + A) */
+#define R_IA_64_TPREL22 0x92 /* imm22 @tprel(S + A) */
+#define R_IA_64_TPREL64I 0x93 /* imm64 @tprel(S + A) */
+#define R_IA_64_TPREL64MSB 0x96 /* word64 MSB @tprel(S + A) */
+#define R_IA_64_TPREL64LSB 0x97 /* word64 LSB @tprel(S + A) */
+#define R_IA_64_LTOFF_TPREL22 0x9a /* imm22 @ltoff(@tprel(S+A)) */
+#define R_IA_64_DTPMOD64MSB 0xa6 /* word64 MSB @dtpmod(S + A) */
+#define R_IA_64_DTPMOD64LSB 0xa7 /* word64 LSB @dtpmod(S + A) */
+#define R_IA_64_LTOFF_DTPMOD22 0xaa /* imm22 @ltoff(@dtpmod(S+A)) */
+#define R_IA_64_DTPREL14 0xb1 /* imm14 @dtprel(S + A) */
+#define R_IA_64_DTPREL22 0xb2 /* imm22 @dtprel(S + A) */
+#define R_IA_64_DTPREL64I 0xb3 /* imm64 @dtprel(S + A) */
+#define R_IA_64_DTPREL32MSB 0xb4 /* word32 MSB @dtprel(S + A) */
+#define R_IA_64_DTPREL32LSB 0xb5 /* word32 LSB @dtprel(S + A) */
+#define R_IA_64_DTPREL64MSB 0xb6 /* word64 MSB @dtprel(S + A) */
+#define R_IA_64_DTPREL64LSB 0xb7 /* word64 LSB @dtprel(S + A) */
+#define R_IA_64_LTOFF_DTPREL22 0xba /* imm22 @ltoff(@dtprel(S+A)) */
+
+#define R_MIPS_NONE 0 /* No reloc */
+#define R_MIPS_16 1 /* Direct 16 bit */
+#define R_MIPS_32 2 /* Direct 32 bit */
+#define R_MIPS_REL32 3 /* PC relative 32 bit */
+#define R_MIPS_26 4 /* Direct 26 bit shifted */
+#define R_MIPS_HI16 5 /* High 16 bit */
+#define R_MIPS_LO16 6 /* Low 16 bit */
+#define R_MIPS_GPREL16 7 /* GP relative 16 bit */
+#define R_MIPS_LITERAL 8 /* 16 bit literal entry */
+#define R_MIPS_GOT16 9 /* 16 bit GOT entry */
+#define R_MIPS_PC16 10 /* PC relative 16 bit */
+#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */
+#define R_MIPS_GPREL32 12 /* GP relative 32 bit */
+#define R_MIPS_GOTHI16 21 /* GOT HI 16 bit */
+#define R_MIPS_GOTLO16 22 /* GOT LO 16 bit */
+#define R_MIPS_CALLHI16 30 /* upper 16 bit GOT entry for function */
+#define R_MIPS_CALLLO16 31 /* lower 16 bit GOT entry for function */
+
+#define R_PPC_NONE 0 /* No relocation. */
+#define R_PPC_ADDR32 1
+#define R_PPC_ADDR24 2
+#define R_PPC_ADDR16 3
+#define R_PPC_ADDR16_LO 4
+#define R_PPC_ADDR16_HI 5
+#define R_PPC_ADDR16_HA 6
+#define R_PPC_ADDR14 7
+#define R_PPC_ADDR14_BRTAKEN 8
+#define R_PPC_ADDR14_BRNTAKEN 9
+#define R_PPC_REL24 10
+#define R_PPC_REL14 11
+#define R_PPC_REL14_BRTAKEN 12
+#define R_PPC_REL14_BRNTAKEN 13
+#define R_PPC_GOT16 14
+#define R_PPC_GOT16_LO 15
+#define R_PPC_GOT16_HI 16
+#define R_PPC_GOT16_HA 17
+#define R_PPC_PLTREL24 18
+#define R_PPC_COPY 19
+#define R_PPC_GLOB_DAT 20
+#define R_PPC_JMP_SLOT 21
+#define R_PPC_RELATIVE 22
+#define R_PPC_LOCAL24PC 23
+#define R_PPC_UADDR32 24
+#define R_PPC_UADDR16 25
+#define R_PPC_REL32 26
+#define R_PPC_PLT32 27
+#define R_PPC_PLTREL32 28
+#define R_PPC_PLT16_LO 29
+#define R_PPC_PLT16_HI 30
+#define R_PPC_PLT16_HA 31
+#define R_PPC_SDAREL16 32
+#define R_PPC_SECTOFF 33
+#define R_PPC_SECTOFF_LO 34
+#define R_PPC_SECTOFF_HI 35
+#define R_PPC_SECTOFF_HA 36
+
+/*
+ * 64-bit relocations
+ */
+#define R_PPC64_ADDR64 38
+#define R_PPC64_ADDR16_HIGHER 39
+#define R_PPC64_ADDR16_HIGHERA 40
+#define R_PPC64_ADDR16_HIGHEST 41
+#define R_PPC64_ADDR16_HIGHESTA 42
+#define R_PPC64_UADDR64 43
+#define R_PPC64_REL64 44
+#define R_PPC64_PLT64 45
+#define R_PPC64_PLTREL64 46
+#define R_PPC64_TOC16 47
+#define R_PPC64_TOC16_LO 48
+#define R_PPC64_TOC16_HI 49
+#define R_PPC64_TOC16_HA 50
+#define R_PPC64_TOC 51
+#define R_PPC64_DTPMOD64 68
+#define R_PPC64_TPREL64 73
+#define R_PPC64_DTPREL64 78
+
+/*
+ * TLS relocations
+ */
+#define R_PPC_TLS 67
+#define R_PPC_DTPMOD32 68
+#define R_PPC_TPREL16 69
+#define R_PPC_TPREL16_LO 70
+#define R_PPC_TPREL16_HI 71
+#define R_PPC_TPREL16_HA 72
+#define R_PPC_TPREL32 73
+#define R_PPC_DTPREL16 74
+#define R_PPC_DTPREL16_LO 75
+#define R_PPC_DTPREL16_HI 76
+#define R_PPC_DTPREL16_HA 77
+#define R_PPC_DTPREL32 78
+#define R_PPC_GOT_TLSGD16 79
+#define R_PPC_GOT_TLSGD16_LO 80
+#define R_PPC_GOT_TLSGD16_HI 81
+#define R_PPC_GOT_TLSGD16_HA 82
+#define R_PPC_GOT_TLSLD16 83
+#define R_PPC_GOT_TLSLD16_LO 84
+#define R_PPC_GOT_TLSLD16_HI 85
+#define R_PPC_GOT_TLSLD16_HA 86
+#define R_PPC_GOT_TPREL16 87
+#define R_PPC_GOT_TPREL16_LO 88
+#define R_PPC_GOT_TPREL16_HI 89
+#define R_PPC_GOT_TPREL16_HA 90
+
+/*
+ * The remaining relocs are from the Embedded ELF ABI, and are not in the
+ * SVR4 ELF ABI.
+ */
+
+#define R_PPC_EMB_NADDR32 101
+#define R_PPC_EMB_NADDR16 102
+#define R_PPC_EMB_NADDR16_LO 103
+#define R_PPC_EMB_NADDR16_HI 104
+#define R_PPC_EMB_NADDR16_HA 105
+#define R_PPC_EMB_SDAI16 106
+#define R_PPC_EMB_SDA2I16 107
+#define R_PPC_EMB_SDA2REL 108
+#define R_PPC_EMB_SDA21 109
+#define R_PPC_EMB_MRKREF 110
+#define R_PPC_EMB_RELSEC16 111
+#define R_PPC_EMB_RELST_LO 112
+#define R_PPC_EMB_RELST_HI 113
+#define R_PPC_EMB_RELST_HA 114
+#define R_PPC_EMB_BIT_FLD 115
+#define R_PPC_EMB_RELSDA 116
+
+#define R_SPARC_NONE 0
+#define R_SPARC_8 1
+#define R_SPARC_16 2
+#define R_SPARC_32 3
+#define R_SPARC_DISP8 4
+#define R_SPARC_DISP16 5
+#define R_SPARC_DISP32 6
+#define R_SPARC_WDISP30 7
+#define R_SPARC_WDISP22 8
+#define R_SPARC_HI22 9
+#define R_SPARC_22 10
+#define R_SPARC_13 11
+#define R_SPARC_LO10 12
+#define R_SPARC_GOT10 13
+#define R_SPARC_GOT13 14
+#define R_SPARC_GOT22 15
+#define R_SPARC_PC10 16
+#define R_SPARC_PC22 17
+#define R_SPARC_WPLT30 18
+#define R_SPARC_COPY 19
+#define R_SPARC_GLOB_DAT 20
+#define R_SPARC_JMP_SLOT 21
+#define R_SPARC_RELATIVE 22
+#define R_SPARC_UA32 23
+#define R_SPARC_PLT32 24
+#define R_SPARC_HIPLT22 25
+#define R_SPARC_LOPLT10 26
+#define R_SPARC_PCPLT32 27
+#define R_SPARC_PCPLT22 28
+#define R_SPARC_PCPLT10 29
+#define R_SPARC_10 30
+#define R_SPARC_11 31
+#define R_SPARC_64 32
+#define R_SPARC_OLO10 33
+#define R_SPARC_HH22 34
+#define R_SPARC_HM10 35
+#define R_SPARC_LM22 36
+#define R_SPARC_PC_HH22 37
+#define R_SPARC_PC_HM10 38
+#define R_SPARC_PC_LM22 39
+#define R_SPARC_WDISP16 40
+#define R_SPARC_WDISP19 41
+#define R_SPARC_GLOB_JMP 42
+#define R_SPARC_7 43
+#define R_SPARC_5 44
+#define R_SPARC_6 45
+#define R_SPARC_DISP64 46
+#define R_SPARC_PLT64 47
+#define R_SPARC_HIX22 48
+#define R_SPARC_LOX10 49
+#define R_SPARC_H44 50
+#define R_SPARC_M44 51
+#define R_SPARC_L44 52
+#define R_SPARC_REGISTER 53
+#define R_SPARC_UA64 54
+#define R_SPARC_UA16 55
+#define R_SPARC_TLS_GD_HI22 56
+#define R_SPARC_TLS_GD_LO10 57
+#define R_SPARC_TLS_GD_ADD 58
+#define R_SPARC_TLS_GD_CALL 59
+#define R_SPARC_TLS_LDM_HI22 60
+#define R_SPARC_TLS_LDM_LO10 61
+#define R_SPARC_TLS_LDM_ADD 62
+#define R_SPARC_TLS_LDM_CALL 63
+#define R_SPARC_TLS_LDO_HIX22 64
+#define R_SPARC_TLS_LDO_LOX10 65
+#define R_SPARC_TLS_LDO_ADD 66
+#define R_SPARC_TLS_IE_HI22 67
+#define R_SPARC_TLS_IE_LO10 68
+#define R_SPARC_TLS_IE_LD 69
+#define R_SPARC_TLS_IE_LDX 70
+#define R_SPARC_TLS_IE_ADD 71
+#define R_SPARC_TLS_LE_HIX22 72
+#define R_SPARC_TLS_LE_LOX10 73
+#define R_SPARC_TLS_DTPMOD32 74
+#define R_SPARC_TLS_DTPMOD64 75
+#define R_SPARC_TLS_DTPOFF32 76
+#define R_SPARC_TLS_DTPOFF64 77
+#define R_SPARC_TLS_TPOFF32 78
+#define R_SPARC_TLS_TPOFF64 79
+
+#define R_X86_64_NONE 0 /* No relocation. */
+#define R_X86_64_64 1 /* Add 64 bit symbol value. */
+#define R_X86_64_PC32 2 /* PC-relative 32 bit signed sym value. */
+#define R_X86_64_GOT32 3 /* PC-relative 32 bit GOT offset. */
+#define R_X86_64_PLT32 4 /* PC-relative 32 bit PLT offset. */
+#define R_X86_64_COPY 5 /* Copy data from shared object. */
+#define R_X86_64_GLOB_DAT 6 /* Set GOT entry to data address. */
+#define R_X86_64_JMP_SLOT 7 /* Set GOT entry to code address. */
+#define R_X86_64_RELATIVE 8 /* Add load address of shared object. */
+#define R_X86_64_GOTPCREL 9 /* Add 32 bit signed pcrel offset to GOT. */
+#define R_X86_64_32 10 /* Add 32 bit zero extended symbol value */
+#define R_X86_64_32S 11 /* Add 32 bit sign extended symbol value */
+#define R_X86_64_16 12 /* Add 16 bit zero extended symbol value */
+#define R_X86_64_PC16 13 /* Add 16 bit signed extended pc relative symbol value */
+#define R_X86_64_8 14 /* Add 8 bit zero extended symbol value */
+#define R_X86_64_PC8 15 /* Add 8 bit signed extended pc relative symbol value */
+#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */
+#define R_X86_64_DTPOFF64 17 /* Offset in TLS block */
+#define R_X86_64_TPOFF64 18 /* Offset in static TLS block */
+#define R_X86_64_TLSGD 19 /* PC relative offset to GD GOT entry */
+#define R_X86_64_TLSLD 20 /* PC relative offset to LD GOT entry */
+#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */
+#define R_X86_64_GOTTPOFF 22 /* PC relative offset to IE GOT entry */
+#define R_X86_64_TPOFF32 23 /* Offset in static TLS block */
+#define R_X86_64_IRELATIVE 37
+
+
+#endif /* !_SYS_ELF_COMMON_H_ */
#include "io.h"
#include "sdram.h"
#include "console.h"
+#include "elf64.h"
+
+#define FLASH_LOADER_USE_MAP
int _printf(const char *fmt, ...)
{
int count;
- char buffer[320];
+ char buffer[128];
va_list ap;
va_start(ap, fmt);
__asm__ volatile ("icbi 0,0; isync" : : : "memory");
}
-void main(void)
+#define SPI_CMD_RDID 0x9f
+#define SPI_CMD_READ 0x03
+#define SPI_CMD_DUAL_FREAD 0x3b
+#define SPI_CMD_QUAD_FREAD 0x6b
+#define SPI_CMD_RDCR 0x35
+#define SPI_CMD_WREN 0x06
+#define SPI_CMD_PP 0x02
+#define SPI_CMD_RDSR 0x05
+#define SPI_CMD_WWR 0x01
+
+static void fl_cs_on(void)
+{
+ writeb(SPI_REG_CTRL_MANUAL_CS, SPI_FCTRL_BASE + SPI_REG_CTRL);
+}
+
+static void fl_cs_off(void)
+{
+ writeb(0, SPI_FCTRL_BASE + SPI_REG_CTRL);
+ __asm__ volatile("nop");
+ __asm__ volatile("nop");
+ __asm__ volatile("nop");
+ __asm__ volatile("nop");
+ __asm__ volatile("nop");
+}
+
+static void wait_wip(void)
+{
+ for (;;) {
+ uint8_t sr;
+
+ fl_cs_on();
+ writeb(SPI_CMD_RDSR, SPI_FCTRL_BASE + SPI_REG_DATA);
+ sr = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
+ fl_cs_off();
+ if ((sr & 1) == 0)
+ break;
+ }
+}
+
+static void send_wren(void)
+{
+ fl_cs_on();
+ writeb(SPI_CMD_WREN, SPI_FCTRL_BASE + SPI_REG_DATA);
+ fl_cs_off();
+}
+
+static void check_spansion_quad_mode(void)
+{
+ uint8_t cf1;
+
+ writeb(SPI_CMD_RDCR, SPI_FCTRL_BASE + SPI_REG_DATA);
+ fl_cs_on();
+ writeb(SPI_CMD_RDCR, SPI_FCTRL_BASE + SPI_REG_DATA);
+ cf1 = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
+ fl_cs_off();
+ printf(" Cypress/Spansion (CF1=%02x)", cf1);
+ if (cf1 & 0x02)
+ return;
+ printf(" enabling QUAD");
+ send_wren();
+ fl_cs_on();
+ writeb(SPI_CMD_WWR, SPI_FCTRL_BASE + SPI_REG_DATA);
+ writeb(0x00, SPI_FCTRL_BASE + SPI_REG_DATA);
+ writeb(cf1 | 0x02, SPI_FCTRL_BASE + SPI_REG_DATA);
+ writeb(0, SPI_FCTRL_BASE + SPI_REG_CTRL);
+ fl_cs_off();
+ wait_wip();
+}
+
+static bool check_flash(void)
+{
+ bool quad = false;
+ uint8_t id[3];
+
+ fl_cs_on();
+ writeb(SPI_CMD_RDID, SPI_FCTRL_BASE + SPI_REG_DATA);
+ id[0] = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
+ id[1] = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
+ id[2] = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
+ fl_cs_off();
+ printf(" SPI FLASH ID: %02x%02x%02x", id[0], id[1], id[2]);
+
+ if ((id[0] | id[1] | id[2]) == 0 ||
+ (id[0] & id[1] & id[2]) == 0xff)
+ return false;
+
+ /* Supported flash types for quad mode */
+ if (id[0] == 0x01 &&
+ (id[1] == 0x02 || id[1] == 0x20) &&
+ (id[2] == 0x18 || id[2] == 0x19)) {
+ check_spansion_quad_mode();
+ quad = true;
+ }
+ if (id[0] == 0x20 && id[1] == 0xba && id[2] == 0x18) {
+ printf(" Micron");
+ quad = true;
+ }
+ if (quad) {
+ uint32_t cfg;
+ printf(" [quad IO mode]");
+
+ /* Preserve the default clock div for the board */
+ cfg = readl(SPI_FCTRL_BASE + SPI_REG_AUTO_CFG);
+ cfg &= SPI_REG_AUTO_CFG_CKDIV_MASK;
+
+ /* Enable quad mode, 8 dummy clocks, 32 cycles CS timeout */
+ cfg |= SPI_CMD_QUAD_FREAD |
+ (0x07 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT) |
+ SPI_REG_AUT_CFG_MODE_QUAD |
+ (0x20 << SPI_REG_AUTO_CFG_CSTOUT_SHIFT);
+ writel(cfg, SPI_FCTRL_BASE + SPI_REG_AUTO_CFG);
+ }
+ printf("\n");
+
+ return true;
+}
+
+static bool fl_read(void *dst, uint32_t offset, uint32_t size)
+{
+ uint8_t *d = dst;
+
+#ifdef FLASH_LOADER_USE_MAP
+ memcpy(d, (void *)(unsigned long)(SPI_FLASH_BASE + offset), size);
+#else
+ if (size < 1)
+ return false;
+ fl_cs_on();
+ writeb(SPI_CMD_QUAD_FREAD, SPI_FCTRL_BASE + SPI_REG_DATA);
+ writeb(offset >> 16, SPI_FCTRL_BASE + SPI_REG_DATA);
+ writeb(offset >> 8, SPI_FCTRL_BASE + SPI_REG_DATA);
+ writeb(offset, SPI_FCTRL_BASE + SPI_REG_DATA);
+ writeb(0x00, SPI_FCTRL_BASE + SPI_REG_DATA);
+ while(size--)
+ *(d++) = readb(SPI_FCTRL_BASE + SPI_REG_DATA_QUAD);
+ fl_cs_off();
+#endif
+
+ return true;
+}
+
+static unsigned long boot_flash(unsigned int offset)
+{
+ Elf64_Ehdr ehdr;
+ Elf64_Phdr ph;
+ unsigned int i, poff, size, off;
+ void *addr;
+
+ printf("Trying flash...\n");
+ if (!fl_read(&ehdr, offset, sizeof(ehdr)))
+ return -1ul;
+ if (!IS_ELF(ehdr) || ehdr.e_ident[EI_CLASS] != ELFCLASS64) {
+ printf("Doesn't look like an elf64\n");
+ goto dump;
+ }
+ if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB ||
+ ehdr.e_machine != EM_PPC64) {
+ printf("Not a ppc64le binary\n");
+ goto dump;
+ }
+
+ poff = offset + ehdr.e_phoff;
+ for (i = 0; i < ehdr.e_phnum; i++) {
+ if (!fl_read(&ph, poff, sizeof(ph)))
+ goto dump;
+ if (ph.p_type != PT_LOAD)
+ continue;
+
+ /* XXX Add bound checking ! */
+ size = ph.p_filesz;
+ addr = (void *)ph.p_vaddr;
+ off = offset + ph.p_offset;
+ printf("Copy segment %d (0x%x bytes) to %p\n", i, size, addr);
+ fl_read(addr, off, size);
+ poff += ehdr.e_phentsize;
+ }
+
+ printf("Booting from DRAM at %x\n", (unsigned int)ehdr.e_entry);
+ flush_cpu_icache();
+ return ehdr.e_entry;
+dump:
+ printf("HDR: %02x %02x %02x %02x %02x %02x %02x %02x\n",
+ ehdr.e_ident[0], ehdr.e_ident[1], ehdr.e_ident[2], ehdr.e_ident[3],
+ ehdr.e_ident[4], ehdr.e_ident[5], ehdr.e_ident[6], ehdr.e_ident[7]);
+ return -1ul;
+}
+
+static void boot_sdram(void)
+{
+ void *s = (void *)(DRAM_INIT_BASE + 0x4000);
+ void *d = (void *)DRAM_BASE;
+ int sz = (0x10000 - 0x4000);
+ printf("Copying payload to DRAM...\n");
+ memcpy(d, s, sz);
+ printf("Booting from DRAM...\n");
+ flush_cpu_icache();
+}
+
+uint64_t main(void)
{
- unsigned long long ftr, val;
+ unsigned long ftr, val;
+ unsigned int fl_off = 0;
+ bool try_flash = false;
/* Init the UART */
potato_uart_init();
printf("DRAM ");
if (ftr & SYS_REG_INFO_HAS_BRAM)
printf("BRAM ");
+ if (ftr & SYS_REG_INFO_HAS_SPI_FLASH)
+ printf("SPIFLASH ");
printf("\n");
if (ftr & SYS_REG_INFO_HAS_BRAM) {
val = readq(SYSCON_BASE + SYS_REG_BRAMINFO) & SYS_REG_BRAMINFO_SIZE_MASK;
- printf(" BRAM: %lld KB\n", val / 1024);
+ printf(" BRAM: %ld KB\n", val / 1024);
}
if (ftr & SYS_REG_INFO_HAS_DRAM) {
val = readq(SYSCON_BASE + SYS_REG_DRAMINFO) & SYS_REG_DRAMINFO_SIZE_MASK;
- printf(" DRAM: %lld MB\n", val / (1024 * 1024));
+ printf(" DRAM: %ld MB\n", val / (1024 * 1024));
val = readq(SYSCON_BASE + SYS_REG_DRAMINITINFO);
- printf(" DRAM INIT: %lld KB\n", val / 1024);
+ printf(" DRAM INIT: %ld KB\n", val / 1024);
}
val = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
- printf(" CLK: %lld MHz\n", val / 1000000);
-
+ printf(" CLK: %ld MHz\n", val / 1000000);
+ if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
+ val = readq(SYSCON_BASE + SYS_REG_SPI_INFO);
+ try_flash = check_flash();
+ fl_off = val & SYS_REG_SPI_INFO_FLASH_OFF_MASK;
+ printf(" SPI FLASH OFF: 0x%x bytes\n", fl_off);
+ try_flash = true;
+ }
printf("\n");
if (ftr & SYS_REG_INFO_HAS_DRAM) {
printf("LiteDRAM built from Migen %s and LiteX %s\n",
MIGEN_GIT_SHA1, LITEX_GIT_SHA1);
sdrinit();
}
- if (ftr & SYS_REG_INFO_HAS_BRAM)
+ if (ftr & SYS_REG_INFO_HAS_BRAM) {
printf("Booting from BRAM...\n");
- else {
- void *s = (void *)(DRAM_INIT_BASE + 0x4000);
- void *d = (void *)DRAM_BASE;
- int sz = (0x10000 - 0x4000);
- printf("Copying payload to DRAM...\n");
- memcpy(d, s, sz);
- printf("Booting from DRAM...\n");
- flush_cpu_icache();
+ return 0;
+ }
+ if (try_flash) {
+ val = boot_flash(fl_off);
+ if (val != (unsigned long)-1)
+ return val;
}
+ boot_sdram();
+ return 0;
}
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:51
+// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:02
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
output wire [127:0] user_port_native_0_rdata_data
);
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-wire [31:0] litedramcore_dat_w;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-wire [31:0] litedramcore_wishbone_dat_r;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
+reg [13:0] soc_litedramcore_adr = 14'd0;
+reg soc_litedramcore_we = 1'd0;
+wire [31:0] soc_litedramcore_dat_w;
+wire [31:0] soc_litedramcore_dat_r;
+wire [29:0] soc_litedramcore_wishbone_adr;
+wire [31:0] soc_litedramcore_wishbone_dat_w;
+wire [31:0] soc_litedramcore_wishbone_dat_r;
+wire [3:0] soc_litedramcore_wishbone_sel;
+wire soc_litedramcore_wishbone_cyc;
+wire soc_litedramcore_wishbone_stb;
+reg soc_litedramcore_wishbone_ack = 1'd0;
+wire soc_litedramcore_wishbone_we;
+wire [2:0] soc_litedramcore_wishbone_cti;
+wire [1:0] soc_litedramcore_wishbone_bte;
+reg soc_litedramcore_wishbone_err = 1'd0;
wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire sys4x_dqs_clk;
wire iodelay_clk;
wire iodelay_rst;
-wire sys_pll_reset;
-wire sys_pll_locked;
-wire s7pll0_clkin;
-wire s7pll0_clkout0;
-wire s7pll0_clkout_buf0;
-wire s7pll0_clkout1;
-wire s7pll0_clkout_buf1;
-wire s7pll0_clkout2;
-wire s7pll0_clkout_buf2;
-wire iodelay_pll_reset;
-wire iodelay_pll_locked;
-wire s7pll1_clkin;
-wire s7pll1_clkout;
-wire s7pll1_clkout_buf;
-reg [3:0] reset_counter = 4'd15;
-reg ic_reset = 1'd1;
-reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg a7ddrphy_wlevel_en_storage = 1'd0;
-reg a7ddrphy_wlevel_en_re = 1'd0;
-wire a7ddrphy_wlevel_strobe_re;
-wire a7ddrphy_wlevel_strobe_r;
-wire a7ddrphy_wlevel_strobe_we;
-reg a7ddrphy_wlevel_strobe_w = 1'd0;
-wire a7ddrphy_cdly_rst_re;
-wire a7ddrphy_cdly_rst_r;
-wire a7ddrphy_cdly_rst_we;
-reg a7ddrphy_cdly_rst_w = 1'd0;
-wire a7ddrphy_cdly_inc_re;
-wire a7ddrphy_cdly_inc_r;
-wire a7ddrphy_cdly_inc_we;
-reg a7ddrphy_cdly_inc_w = 1'd0;
-reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg a7ddrphy_dly_sel_re = 1'd0;
-wire a7ddrphy_rdly_dq_rst_re;
-wire a7ddrphy_rdly_dq_rst_r;
-wire a7ddrphy_rdly_dq_rst_we;
-reg a7ddrphy_rdly_dq_rst_w = 1'd0;
-wire a7ddrphy_rdly_dq_inc_re;
-wire a7ddrphy_rdly_dq_inc_r;
-wire a7ddrphy_rdly_dq_inc_we;
-reg a7ddrphy_rdly_dq_inc_w = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_rst_re;
-wire a7ddrphy_rdly_dq_bitslip_rst_r;
-wire a7ddrphy_rdly_dq_bitslip_rst_we;
-reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_re;
-wire a7ddrphy_rdly_dq_bitslip_r;
-wire a7ddrphy_rdly_dq_bitslip_we;
-reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-wire [13:0] a7ddrphy_dfi_p0_address;
-wire [2:0] a7ddrphy_dfi_p0_bank;
-wire a7ddrphy_dfi_p0_cas_n;
-wire a7ddrphy_dfi_p0_cs_n;
-wire a7ddrphy_dfi_p0_ras_n;
-wire a7ddrphy_dfi_p0_we_n;
-wire a7ddrphy_dfi_p0_cke;
-wire a7ddrphy_dfi_p0_odt;
-wire a7ddrphy_dfi_p0_reset_n;
-wire a7ddrphy_dfi_p0_act_n;
-wire [31:0] a7ddrphy_dfi_p0_wrdata;
-wire a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-reg a7ddrphy_dfi_p0_rddata_valid = 1'd0;
-wire [13:0] a7ddrphy_dfi_p1_address;
-wire [2:0] a7ddrphy_dfi_p1_bank;
-wire a7ddrphy_dfi_p1_cas_n;
-wire a7ddrphy_dfi_p1_cs_n;
-wire a7ddrphy_dfi_p1_ras_n;
-wire a7ddrphy_dfi_p1_we_n;
-wire a7ddrphy_dfi_p1_cke;
-wire a7ddrphy_dfi_p1_odt;
-wire a7ddrphy_dfi_p1_reset_n;
-wire a7ddrphy_dfi_p1_act_n;
-wire [31:0] a7ddrphy_dfi_p1_wrdata;
-wire a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-reg a7ddrphy_dfi_p1_rddata_valid = 1'd0;
-wire [13:0] a7ddrphy_dfi_p2_address;
-wire [2:0] a7ddrphy_dfi_p2_bank;
-wire a7ddrphy_dfi_p2_cas_n;
-wire a7ddrphy_dfi_p2_cs_n;
-wire a7ddrphy_dfi_p2_ras_n;
-wire a7ddrphy_dfi_p2_we_n;
-wire a7ddrphy_dfi_p2_cke;
-wire a7ddrphy_dfi_p2_odt;
-wire a7ddrphy_dfi_p2_reset_n;
-wire a7ddrphy_dfi_p2_act_n;
-wire [31:0] a7ddrphy_dfi_p2_wrdata;
-wire a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-reg a7ddrphy_dfi_p2_rddata_valid = 1'd0;
-wire [13:0] a7ddrphy_dfi_p3_address;
-wire [2:0] a7ddrphy_dfi_p3_bank;
-wire a7ddrphy_dfi_p3_cas_n;
-wire a7ddrphy_dfi_p3_cs_n;
-wire a7ddrphy_dfi_p3_ras_n;
-wire a7ddrphy_dfi_p3_we_n;
-wire a7ddrphy_dfi_p3_cke;
-wire a7ddrphy_dfi_p3_odt;
-wire a7ddrphy_dfi_p3_reset_n;
-wire a7ddrphy_dfi_p3_act_n;
-wire [31:0] a7ddrphy_dfi_p3_wrdata;
-wire a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-reg a7ddrphy_dfi_p3_rddata_valid = 1'd0;
-wire a7ddrphy_sd_clk_se_nodelay;
-reg a7ddrphy_dqs_oe = 1'd0;
-reg a7ddrphy_dqs_oe_delayed = 1'd0;
-wire a7ddrphy_dqspattern0;
-wire a7ddrphy_dqspattern1;
-reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire [1:0] a7ddrphy_dqs_i;
-wire [1:0] a7ddrphy_dqs_i_delayed;
-wire a7ddrphy_dqs_o_no_delay0;
-wire a7ddrphy_dqs_t0;
-wire a7ddrphy0;
-wire a7ddrphy_dqs_o_no_delay1;
-wire a7ddrphy_dqs_t1;
-wire a7ddrphy1;
-wire a7ddrphy_dq_oe;
-reg a7ddrphy_dq_oe_delayed = 1'd0;
-wire a7ddrphy_dq_o_nodelay0;
-wire a7ddrphy_dq_i_nodelay0;
-wire a7ddrphy_dq_i_delayed0;
-wire a7ddrphy_dq_t0;
-wire [7:0] a7ddrphy_dq_i_data0;
-wire [7:0] a7ddrphy_bitslip0_i;
-reg [7:0] a7ddrphy_bitslip0_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip0_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip0_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay1;
-wire a7ddrphy_dq_i_nodelay1;
-wire a7ddrphy_dq_i_delayed1;
-wire a7ddrphy_dq_t1;
-wire [7:0] a7ddrphy_dq_i_data1;
-wire [7:0] a7ddrphy_bitslip1_i;
-reg [7:0] a7ddrphy_bitslip1_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip1_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip1_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay2;
-wire a7ddrphy_dq_i_nodelay2;
-wire a7ddrphy_dq_i_delayed2;
-wire a7ddrphy_dq_t2;
-wire [7:0] a7ddrphy_dq_i_data2;
-wire [7:0] a7ddrphy_bitslip2_i;
-reg [7:0] a7ddrphy_bitslip2_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip2_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip2_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay3;
-wire a7ddrphy_dq_i_nodelay3;
-wire a7ddrphy_dq_i_delayed3;
-wire a7ddrphy_dq_t3;
-wire [7:0] a7ddrphy_dq_i_data3;
-wire [7:0] a7ddrphy_bitslip3_i;
-reg [7:0] a7ddrphy_bitslip3_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip3_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip3_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay4;
-wire a7ddrphy_dq_i_nodelay4;
-wire a7ddrphy_dq_i_delayed4;
-wire a7ddrphy_dq_t4;
-wire [7:0] a7ddrphy_dq_i_data4;
-wire [7:0] a7ddrphy_bitslip4_i;
-reg [7:0] a7ddrphy_bitslip4_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip4_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip4_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay5;
-wire a7ddrphy_dq_i_nodelay5;
-wire a7ddrphy_dq_i_delayed5;
-wire a7ddrphy_dq_t5;
-wire [7:0] a7ddrphy_dq_i_data5;
-wire [7:0] a7ddrphy_bitslip5_i;
-reg [7:0] a7ddrphy_bitslip5_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip5_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip5_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay6;
-wire a7ddrphy_dq_i_nodelay6;
-wire a7ddrphy_dq_i_delayed6;
-wire a7ddrphy_dq_t6;
-wire [7:0] a7ddrphy_dq_i_data6;
-wire [7:0] a7ddrphy_bitslip6_i;
-reg [7:0] a7ddrphy_bitslip6_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip6_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip6_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay7;
-wire a7ddrphy_dq_i_nodelay7;
-wire a7ddrphy_dq_i_delayed7;
-wire a7ddrphy_dq_t7;
-wire [7:0] a7ddrphy_dq_i_data7;
-wire [7:0] a7ddrphy_bitslip7_i;
-reg [7:0] a7ddrphy_bitslip7_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip7_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip7_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay8;
-wire a7ddrphy_dq_i_nodelay8;
-wire a7ddrphy_dq_i_delayed8;
-wire a7ddrphy_dq_t8;
-wire [7:0] a7ddrphy_dq_i_data8;
-wire [7:0] a7ddrphy_bitslip8_i;
-reg [7:0] a7ddrphy_bitslip8_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip8_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip8_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay9;
-wire a7ddrphy_dq_i_nodelay9;
-wire a7ddrphy_dq_i_delayed9;
-wire a7ddrphy_dq_t9;
-wire [7:0] a7ddrphy_dq_i_data9;
-wire [7:0] a7ddrphy_bitslip9_i;
-reg [7:0] a7ddrphy_bitslip9_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip9_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip9_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay10;
-wire a7ddrphy_dq_i_nodelay10;
-wire a7ddrphy_dq_i_delayed10;
-wire a7ddrphy_dq_t10;
-wire [7:0] a7ddrphy_dq_i_data10;
-wire [7:0] a7ddrphy_bitslip10_i;
-reg [7:0] a7ddrphy_bitslip10_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip10_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip10_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay11;
-wire a7ddrphy_dq_i_nodelay11;
-wire a7ddrphy_dq_i_delayed11;
-wire a7ddrphy_dq_t11;
-wire [7:0] a7ddrphy_dq_i_data11;
-wire [7:0] a7ddrphy_bitslip11_i;
-reg [7:0] a7ddrphy_bitslip11_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip11_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip11_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay12;
-wire a7ddrphy_dq_i_nodelay12;
-wire a7ddrphy_dq_i_delayed12;
-wire a7ddrphy_dq_t12;
-wire [7:0] a7ddrphy_dq_i_data12;
-wire [7:0] a7ddrphy_bitslip12_i;
-reg [7:0] a7ddrphy_bitslip12_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip12_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip12_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay13;
-wire a7ddrphy_dq_i_nodelay13;
-wire a7ddrphy_dq_i_delayed13;
-wire a7ddrphy_dq_t13;
-wire [7:0] a7ddrphy_dq_i_data13;
-wire [7:0] a7ddrphy_bitslip13_i;
-reg [7:0] a7ddrphy_bitslip13_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip13_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip13_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay14;
-wire a7ddrphy_dq_i_nodelay14;
-wire a7ddrphy_dq_i_delayed14;
-wire a7ddrphy_dq_t14;
-wire [7:0] a7ddrphy_dq_i_data14;
-wire [7:0] a7ddrphy_bitslip14_i;
-reg [7:0] a7ddrphy_bitslip14_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip14_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip14_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay15;
-wire a7ddrphy_dq_i_nodelay15;
-wire a7ddrphy_dq_i_delayed15;
-wire a7ddrphy_dq_t15;
-wire [7:0] a7ddrphy_dq_i_data15;
-wire [7:0] a7ddrphy_bitslip15_i;
-reg [7:0] a7ddrphy_bitslip15_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip15_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip15_r = 24'd0;
-wire [7:0] a7ddrphy_rddata_en;
-reg [7:0] a7ddrphy_rddata_en_last = 8'd0;
-wire [3:0] a7ddrphy_wrdata_en;
-reg [3:0] a7ddrphy_wrdata_en_last = 4'd0;
-wire [13:0] litedramcore_inti_p0_address;
-wire [2:0] litedramcore_inti_p0_bank;
-reg litedramcore_inti_p0_cas_n = 1'd1;
-reg litedramcore_inti_p0_cs_n = 1'd1;
-reg litedramcore_inti_p0_ras_n = 1'd1;
-reg litedramcore_inti_p0_we_n = 1'd1;
-wire litedramcore_inti_p0_cke;
-wire litedramcore_inti_p0_odt;
-wire litedramcore_inti_p0_reset_n;
-reg litedramcore_inti_p0_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p0_wrdata;
-wire litedramcore_inti_p0_wrdata_en;
-wire [3:0] litedramcore_inti_p0_wrdata_mask;
-wire litedramcore_inti_p0_rddata_en;
-reg [31:0] litedramcore_inti_p0_rddata = 32'd0;
-reg litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [13:0] litedramcore_inti_p1_address;
-wire [2:0] litedramcore_inti_p1_bank;
-reg litedramcore_inti_p1_cas_n = 1'd1;
-reg litedramcore_inti_p1_cs_n = 1'd1;
-reg litedramcore_inti_p1_ras_n = 1'd1;
-reg litedramcore_inti_p1_we_n = 1'd1;
-wire litedramcore_inti_p1_cke;
-wire litedramcore_inti_p1_odt;
-wire litedramcore_inti_p1_reset_n;
-reg litedramcore_inti_p1_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p1_wrdata;
-wire litedramcore_inti_p1_wrdata_en;
-wire [3:0] litedramcore_inti_p1_wrdata_mask;
-wire litedramcore_inti_p1_rddata_en;
-reg [31:0] litedramcore_inti_p1_rddata = 32'd0;
-reg litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [13:0] litedramcore_inti_p2_address;
-wire [2:0] litedramcore_inti_p2_bank;
-reg litedramcore_inti_p2_cas_n = 1'd1;
-reg litedramcore_inti_p2_cs_n = 1'd1;
-reg litedramcore_inti_p2_ras_n = 1'd1;
-reg litedramcore_inti_p2_we_n = 1'd1;
-wire litedramcore_inti_p2_cke;
-wire litedramcore_inti_p2_odt;
-wire litedramcore_inti_p2_reset_n;
-reg litedramcore_inti_p2_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p2_wrdata;
-wire litedramcore_inti_p2_wrdata_en;
-wire [3:0] litedramcore_inti_p2_wrdata_mask;
-wire litedramcore_inti_p2_rddata_en;
-reg [31:0] litedramcore_inti_p2_rddata = 32'd0;
-reg litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [13:0] litedramcore_inti_p3_address;
-wire [2:0] litedramcore_inti_p3_bank;
-reg litedramcore_inti_p3_cas_n = 1'd1;
-reg litedramcore_inti_p3_cs_n = 1'd1;
-reg litedramcore_inti_p3_ras_n = 1'd1;
-reg litedramcore_inti_p3_we_n = 1'd1;
-wire litedramcore_inti_p3_cke;
-wire litedramcore_inti_p3_odt;
-wire litedramcore_inti_p3_reset_n;
-reg litedramcore_inti_p3_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p3_wrdata;
-wire litedramcore_inti_p3_wrdata_en;
-wire [3:0] litedramcore_inti_p3_wrdata_mask;
-wire litedramcore_inti_p3_rddata_en;
-reg [31:0] litedramcore_inti_p3_rddata = 32'd0;
-reg litedramcore_inti_p3_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [31:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [3:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [31:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [3:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p2_address;
-wire [2:0] litedramcore_slave_p2_bank;
-wire litedramcore_slave_p2_cas_n;
-wire litedramcore_slave_p2_cs_n;
-wire litedramcore_slave_p2_ras_n;
-wire litedramcore_slave_p2_we_n;
-wire litedramcore_slave_p2_cke;
-wire litedramcore_slave_p2_odt;
-wire litedramcore_slave_p2_reset_n;
-wire litedramcore_slave_p2_act_n;
-wire [31:0] litedramcore_slave_p2_wrdata;
-wire litedramcore_slave_p2_wrdata_en;
-wire [3:0] litedramcore_slave_p2_wrdata_mask;
-wire litedramcore_slave_p2_rddata_en;
-reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p3_address;
-wire [2:0] litedramcore_slave_p3_bank;
-wire litedramcore_slave_p3_cas_n;
-wire litedramcore_slave_p3_cs_n;
-wire litedramcore_slave_p3_ras_n;
-wire litedramcore_slave_p3_we_n;
-wire litedramcore_slave_p3_cke;
-wire litedramcore_slave_p3_odt;
-wire litedramcore_slave_p3_reset_n;
-wire litedramcore_slave_p3_act_n;
-wire [31:0] litedramcore_slave_p3_wrdata;
-wire litedramcore_slave_p3_wrdata_en;
-wire [3:0] litedramcore_slave_p3_wrdata_mask;
-wire litedramcore_slave_p3_rddata_en;
-reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [13:0] litedramcore_master_p0_address = 14'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [13:0] litedramcore_master_p1_address = 14'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-reg [13:0] litedramcore_master_p2_address = 14'd0;
-reg [2:0] litedramcore_master_p2_bank = 3'd0;
-reg litedramcore_master_p2_cas_n = 1'd1;
-reg litedramcore_master_p2_cs_n = 1'd1;
-reg litedramcore_master_p2_ras_n = 1'd1;
-reg litedramcore_master_p2_we_n = 1'd1;
-reg litedramcore_master_p2_cke = 1'd0;
-reg litedramcore_master_p2_odt = 1'd0;
-reg litedramcore_master_p2_reset_n = 1'd0;
-reg litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p2_rddata;
-wire litedramcore_master_p2_rddata_valid;
-reg [13:0] litedramcore_master_p3_address = 14'd0;
-reg [2:0] litedramcore_master_p3_bank = 3'd0;
-reg litedramcore_master_p3_cas_n = 1'd1;
-reg litedramcore_master_p3_cs_n = 1'd1;
-reg litedramcore_master_p3_ras_n = 1'd1;
-reg litedramcore_master_p3_we_n = 1'd1;
-reg litedramcore_master_p3_cke = 1'd0;
-reg litedramcore_master_p3_odt = 1'd0;
-reg litedramcore_master_p3_reset_n = 1'd0;
-reg litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p3_rddata;
-wire litedramcore_master_p3_rddata_valid;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_re;
-wire litedramcore_phaseinjector0_command_issue_r;
-wire litedramcore_phaseinjector0_command_issue_we;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_status = 32'd0;
-wire litedramcore_phaseinjector0_we;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_re;
-wire litedramcore_phaseinjector1_command_issue_r;
-wire litedramcore_phaseinjector1_command_issue_we;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_status = 32'd0;
-wire litedramcore_phaseinjector1_we;
-reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg litedramcore_phaseinjector2_command_re = 1'd0;
-wire litedramcore_phaseinjector2_command_issue_re;
-wire litedramcore_phaseinjector2_command_issue_r;
-wire litedramcore_phaseinjector2_command_issue_we;
-reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
-reg litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_status = 32'd0;
-wire litedramcore_phaseinjector2_we;
-reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg litedramcore_phaseinjector3_command_re = 1'd0;
-wire litedramcore_phaseinjector3_command_issue_re;
-wire litedramcore_phaseinjector3_command_issue_r;
-wire litedramcore_phaseinjector3_command_issue_we;
-reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
-reg litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_status = 32'd0;
-wire litedramcore_phaseinjector3_we;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [20:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [20:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [20:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [20:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [20:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [20:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [20:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [20:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [127:0] litedramcore_interface_wdata = 128'd0;
-reg [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] litedramcore_interface_rdata;
-reg [13:0] litedramcore_dfi_p0_address = 14'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [13:0] litedramcore_dfi_p1_address = 14'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg [13:0] litedramcore_dfi_p2_address = 14'd0;
-reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg litedramcore_dfi_p2_cas_n = 1'd1;
-reg litedramcore_dfi_p2_cs_n = 1'd1;
-reg litedramcore_dfi_p2_ras_n = 1'd1;
-reg litedramcore_dfi_p2_we_n = 1'd1;
-wire litedramcore_dfi_p2_cke;
-wire litedramcore_dfi_p2_odt;
-wire litedramcore_dfi_p2_reset_n;
-reg litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p2_wrdata;
-reg litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p2_rddata;
-wire litedramcore_dfi_p2_rddata_valid;
-reg [13:0] litedramcore_dfi_p3_address = 14'd0;
-reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg litedramcore_dfi_p3_cas_n = 1'd1;
-reg litedramcore_dfi_p3_cs_n = 1'd1;
-reg litedramcore_dfi_p3_ras_n = 1'd1;
-reg litedramcore_dfi_p3_we_n = 1'd1;
-wire litedramcore_dfi_p3_cke;
-wire litedramcore_dfi_p3_odt;
-wire litedramcore_dfi_p3_reset_n;
-reg litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p3_wrdata;
-reg litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p3_rddata;
-wire litedramcore_dfi_p3_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [13:0] litedramcore_cmd_payload_a = 14'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [9:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [9:0] litedramcore_timer_count1 = 10'd781;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] litedramcore_sequencer_counter = 6'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [26:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [20:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine0_row = 14'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [20:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine1_row = 14'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [20:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine2_row = 14'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [20:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine3_row = 14'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [20:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine4_row = 14'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [20:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine5_row = 14'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [20:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine6_row = 14'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [20:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine7_row = 14'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [13:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [13:0] litedramcore_nop_a = 14'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-reg litedramcore_steerer4 = 1'd1;
-reg litedramcore_steerer5 = 1'd1;
-reg litedramcore_steerer6 = 1'd1;
-reg litedramcore_steerer7 = 1'd1;
-wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] litedramcore_tfawcon_count;
-reg [4:0] litedramcore_tfawcon_window = 5'd0;
-wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [23:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [127:0] user_port_wdata_payload_data;
-wire [15:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [127:0] user_port_rdata_payload_data;
-reg state = 1'd0;
-reg next_state = 1'd0;
-wire pll_fb0;
-wire pll_fb1;
-reg [1:0] refresher_state = 2'd0;
-reg [1:0] refresher_next_state = 2'd0;
-reg [3:0] bankmachine0_state = 4'd0;
-reg [3:0] bankmachine0_next_state = 4'd0;
-reg [3:0] bankmachine1_state = 4'd0;
-reg [3:0] bankmachine1_next_state = 4'd0;
-reg [3:0] bankmachine2_state = 4'd0;
-reg [3:0] bankmachine2_next_state = 4'd0;
-reg [3:0] bankmachine3_state = 4'd0;
-reg [3:0] bankmachine3_next_state = 4'd0;
-reg [3:0] bankmachine4_state = 4'd0;
-reg [3:0] bankmachine4_next_state = 4'd0;
-reg [3:0] bankmachine5_state = 4'd0;
-reg [3:0] bankmachine5_next_state = 4'd0;
-reg [3:0] bankmachine6_state = 4'd0;
-reg [3:0] bankmachine6_next_state = 4'd0;
-reg [3:0] bankmachine7_state = 4'd0;
-reg [3:0] bankmachine7_next_state = 4'd0;
-reg [3:0] multiplexer_state = 4'd0;
-reg [3:0] multiplexer_next_state = 4'd0;
-wire roundrobin0_request;
-wire roundrobin0_grant;
-wire roundrobin0_ce;
-wire roundrobin1_request;
-wire roundrobin1_grant;
-wire roundrobin1_ce;
-wire roundrobin2_request;
-wire roundrobin2_grant;
-wire roundrobin2_ce;
-wire roundrobin3_request;
-wire roundrobin3_grant;
-wire roundrobin3_ce;
-wire roundrobin4_request;
-wire roundrobin4_grant;
-wire roundrobin4_ce;
-wire roundrobin5_request;
-wire roundrobin5_grant;
-wire roundrobin5_ce;
-wire roundrobin6_request;
-wire roundrobin6_grant;
-wire roundrobin6_ce;
-wire roundrobin7_request;
-wire roundrobin7_grant;
-wire roundrobin7_ce;
-reg locked0 = 1'd0;
-reg locked1 = 1'd0;
-reg locked2 = 1'd0;
-reg locked3 = 1'd0;
-reg locked4 = 1'd0;
-reg locked5 = 1'd0;
-reg locked6 = 1'd0;
-reg locked7 = 1'd0;
-reg new_master_wdata_ready0 = 1'd0;
-reg new_master_wdata_ready1 = 1'd0;
-reg new_master_wdata_ready2 = 1'd0;
-reg new_master_rdata_valid0 = 1'd0;
-reg new_master_rdata_valid1 = 1'd0;
-reg new_master_rdata_valid2 = 1'd0;
-reg new_master_rdata_valid3 = 1'd0;
-reg new_master_rdata_valid4 = 1'd0;
-reg new_master_rdata_valid5 = 1'd0;
-reg new_master_rdata_valid6 = 1'd0;
-reg new_master_rdata_valid7 = 1'd0;
-reg new_master_rdata_valid8 = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-wire csrbank0_init_done0_re;
-wire csrbank0_init_done0_r;
-wire csrbank0_init_done0_we;
-wire csrbank0_init_done0_w;
-wire csrbank0_init_error0_re;
-wire csrbank0_init_error0_r;
-wire csrbank0_init_error0_we;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-wire csrbank1_half_sys8x_taps0_re;
-wire [4:0] csrbank1_half_sys8x_taps0_r;
-wire csrbank1_half_sys8x_taps0_we;
-wire [4:0] csrbank1_half_sys8x_taps0_w;
-wire csrbank1_wlevel_en0_re;
-wire csrbank1_wlevel_en0_r;
-wire csrbank1_wlevel_en0_we;
-wire csrbank1_wlevel_en0_w;
-wire csrbank1_dly_sel0_re;
-wire [1:0] csrbank1_dly_sel0_r;
-wire csrbank1_dly_sel0_we;
-wire [1:0] csrbank1_dly_sel0_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-wire csrbank2_dfii_control0_re;
-wire [3:0] csrbank2_dfii_control0_r;
-wire csrbank2_dfii_control0_we;
-wire [3:0] csrbank2_dfii_control0_w;
-wire csrbank2_dfii_pi0_command0_re;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-wire csrbank2_dfii_pi0_command0_we;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-wire csrbank2_dfii_pi0_address0_re;
-wire [13:0] csrbank2_dfii_pi0_address0_r;
-wire csrbank2_dfii_pi0_address0_we;
-wire [13:0] csrbank2_dfii_pi0_address0_w;
-wire csrbank2_dfii_pi0_baddress0_re;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-wire csrbank2_dfii_pi0_baddress0_we;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-wire csrbank2_dfii_pi0_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-wire csrbank2_dfii_pi0_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-wire csrbank2_dfii_pi0_rddata_re;
-wire [31:0] csrbank2_dfii_pi0_rddata_r;
-wire csrbank2_dfii_pi0_rddata_we;
-wire [31:0] csrbank2_dfii_pi0_rddata_w;
-wire csrbank2_dfii_pi1_command0_re;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-wire csrbank2_dfii_pi1_command0_we;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-wire csrbank2_dfii_pi1_address0_re;
-wire [13:0] csrbank2_dfii_pi1_address0_r;
-wire csrbank2_dfii_pi1_address0_we;
-wire [13:0] csrbank2_dfii_pi1_address0_w;
-wire csrbank2_dfii_pi1_baddress0_re;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-wire csrbank2_dfii_pi1_baddress0_we;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-wire csrbank2_dfii_pi1_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-wire csrbank2_dfii_pi1_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-wire csrbank2_dfii_pi1_rddata_re;
-wire [31:0] csrbank2_dfii_pi1_rddata_r;
-wire csrbank2_dfii_pi1_rddata_we;
-wire [31:0] csrbank2_dfii_pi1_rddata_w;
-wire csrbank2_dfii_pi2_command0_re;
-wire [5:0] csrbank2_dfii_pi2_command0_r;
-wire csrbank2_dfii_pi2_command0_we;
-wire [5:0] csrbank2_dfii_pi2_command0_w;
-wire csrbank2_dfii_pi2_address0_re;
-wire [13:0] csrbank2_dfii_pi2_address0_r;
-wire csrbank2_dfii_pi2_address0_we;
-wire [13:0] csrbank2_dfii_pi2_address0_w;
-wire csrbank2_dfii_pi2_baddress0_re;
-wire [2:0] csrbank2_dfii_pi2_baddress0_r;
-wire csrbank2_dfii_pi2_baddress0_we;
-wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-wire csrbank2_dfii_pi2_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
-wire csrbank2_dfii_pi2_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
-wire csrbank2_dfii_pi2_rddata_re;
-wire [31:0] csrbank2_dfii_pi2_rddata_r;
-wire csrbank2_dfii_pi2_rddata_we;
-wire [31:0] csrbank2_dfii_pi2_rddata_w;
-wire csrbank2_dfii_pi3_command0_re;
-wire [5:0] csrbank2_dfii_pi3_command0_r;
-wire csrbank2_dfii_pi3_command0_we;
-wire [5:0] csrbank2_dfii_pi3_command0_w;
-wire csrbank2_dfii_pi3_address0_re;
-wire [13:0] csrbank2_dfii_pi3_address0_r;
-wire csrbank2_dfii_pi3_address0_we;
-wire [13:0] csrbank2_dfii_pi3_address0_w;
-wire csrbank2_dfii_pi3_baddress0_re;
-wire [2:0] csrbank2_dfii_pi3_baddress0_r;
-wire csrbank2_dfii_pi3_baddress0_we;
-wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-wire csrbank2_dfii_pi3_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
-wire csrbank2_dfii_pi3_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
-wire csrbank2_dfii_pi3_rddata_re;
-wire [31:0] csrbank2_dfii_pi3_rddata_r;
-wire csrbank2_dfii_pi3_rddata_we;
-wire [31:0] csrbank2_dfii_pi3_rddata_w;
-wire csrbank2_sel;
-wire [13:0] adr;
-wire we;
-wire [31:0] dat_w;
-wire [31:0] dat_r;
-reg rhs_array_muxed0 = 1'd0;
-reg [13:0] rhs_array_muxed1 = 14'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [13:0] rhs_array_muxed7 = 14'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [20:0] rhs_array_muxed12 = 21'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [20:0] rhs_array_muxed15 = 21'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [20:0] rhs_array_muxed18 = 21'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [20:0] rhs_array_muxed21 = 21'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [20:0] rhs_array_muxed24 = 21'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [20:0] rhs_array_muxed27 = 21'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [20:0] rhs_array_muxed30 = 21'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [20:0] rhs_array_muxed33 = 21'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [13:0] array_muxed1 = 14'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [13:0] array_muxed8 = 14'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [13:0] array_muxed15 = 14'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [13:0] array_muxed22 = 14'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
-wire xilinxasyncresetsynchronizerimpl0;
-wire xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1;
-wire xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1_expr;
-wire xilinxasyncresetsynchronizerimpl2;
-wire xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2_expr;
-wire xilinxasyncresetsynchronizerimpl3;
-wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire soc_reset;
+wire soc_locked;
+wire soc_clkin;
+wire soc_clkout0;
+wire soc_clkout_buf0;
+wire soc_clkout1;
+wire soc_clkout_buf1;
+wire soc_clkout2;
+wire soc_clkout_buf2;
+wire soc_clkout3;
+wire soc_clkout_buf3;
+reg [3:0] soc_reset_counter = 4'd15;
+reg soc_ic_reset = 1'd1;
+reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg soc_a7ddrphy_wlevel_en_storage = 1'd0;
+reg soc_a7ddrphy_wlevel_en_re = 1'd0;
+wire soc_a7ddrphy_wlevel_strobe_re;
+wire soc_a7ddrphy_wlevel_strobe_r;
+wire soc_a7ddrphy_wlevel_strobe_we;
+reg soc_a7ddrphy_wlevel_strobe_w = 1'd0;
+wire soc_a7ddrphy_cdly_rst_re;
+wire soc_a7ddrphy_cdly_rst_r;
+wire soc_a7ddrphy_cdly_rst_we;
+reg soc_a7ddrphy_cdly_rst_w = 1'd0;
+wire soc_a7ddrphy_cdly_inc_re;
+wire soc_a7ddrphy_cdly_inc_r;
+wire soc_a7ddrphy_cdly_inc_we;
+reg soc_a7ddrphy_cdly_inc_w = 1'd0;
+reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
+reg soc_a7ddrphy_dly_sel_re = 1'd0;
+wire soc_a7ddrphy_rdly_dq_rst_re;
+wire soc_a7ddrphy_rdly_dq_rst_r;
+wire soc_a7ddrphy_rdly_dq_rst_we;
+reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_inc_re;
+wire soc_a7ddrphy_rdly_dq_inc_r;
+wire soc_a7ddrphy_rdly_dq_inc_we;
+reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p0_address;
+wire [2:0] soc_a7ddrphy_dfi_p0_bank;
+wire soc_a7ddrphy_dfi_p0_cas_n;
+wire soc_a7ddrphy_dfi_p0_cs_n;
+wire soc_a7ddrphy_dfi_p0_ras_n;
+wire soc_a7ddrphy_dfi_p0_we_n;
+wire soc_a7ddrphy_dfi_p0_cke;
+wire soc_a7ddrphy_dfi_p0_odt;
+wire soc_a7ddrphy_dfi_p0_reset_n;
+wire soc_a7ddrphy_dfi_p0_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
+wire soc_a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
+wire soc_a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p1_address;
+wire [2:0] soc_a7ddrphy_dfi_p1_bank;
+wire soc_a7ddrphy_dfi_p1_cas_n;
+wire soc_a7ddrphy_dfi_p1_cs_n;
+wire soc_a7ddrphy_dfi_p1_ras_n;
+wire soc_a7ddrphy_dfi_p1_we_n;
+wire soc_a7ddrphy_dfi_p1_cke;
+wire soc_a7ddrphy_dfi_p1_odt;
+wire soc_a7ddrphy_dfi_p1_reset_n;
+wire soc_a7ddrphy_dfi_p1_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
+wire soc_a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
+wire soc_a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p2_address;
+wire [2:0] soc_a7ddrphy_dfi_p2_bank;
+wire soc_a7ddrphy_dfi_p2_cas_n;
+wire soc_a7ddrphy_dfi_p2_cs_n;
+wire soc_a7ddrphy_dfi_p2_ras_n;
+wire soc_a7ddrphy_dfi_p2_we_n;
+wire soc_a7ddrphy_dfi_p2_cke;
+wire soc_a7ddrphy_dfi_p2_odt;
+wire soc_a7ddrphy_dfi_p2_reset_n;
+wire soc_a7ddrphy_dfi_p2_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
+wire soc_a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
+wire soc_a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p3_address;
+wire [2:0] soc_a7ddrphy_dfi_p3_bank;
+wire soc_a7ddrphy_dfi_p3_cas_n;
+wire soc_a7ddrphy_dfi_p3_cs_n;
+wire soc_a7ddrphy_dfi_p3_ras_n;
+wire soc_a7ddrphy_dfi_p3_we_n;
+wire soc_a7ddrphy_dfi_p3_cke;
+wire soc_a7ddrphy_dfi_p3_odt;
+wire soc_a7ddrphy_dfi_p3_reset_n;
+wire soc_a7ddrphy_dfi_p3_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
+wire soc_a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
+wire soc_a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
+wire soc_a7ddrphy_sd_clk_se_nodelay;
+reg soc_a7ddrphy_dqs_oe = 1'd0;
+reg soc_a7ddrphy_dqs_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dqspattern0;
+wire soc_a7ddrphy_dqspattern1;
+reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0;
+wire [1:0] soc_a7ddrphy_dqs_i;
+wire [1:0] soc_a7ddrphy_dqs_i_delayed;
+wire soc_a7ddrphy_dqs_o_no_delay0;
+wire soc_a7ddrphy_dqs_t0;
+wire soc_a7ddrphy0;
+wire soc_a7ddrphy_dqs_o_no_delay1;
+wire soc_a7ddrphy_dqs_t1;
+wire soc_a7ddrphy1;
+wire soc_a7ddrphy_dq_oe;
+reg soc_a7ddrphy_dq_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dq_o_nodelay0;
+wire soc_a7ddrphy_dq_i_nodelay0;
+wire soc_a7ddrphy_dq_i_delayed0;
+wire soc_a7ddrphy_dq_t0;
+wire [7:0] soc_a7ddrphy_dq_i_data0;
+wire [7:0] soc_a7ddrphy_bitslip0_i;
+reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip0_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip0_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay1;
+wire soc_a7ddrphy_dq_i_nodelay1;
+wire soc_a7ddrphy_dq_i_delayed1;
+wire soc_a7ddrphy_dq_t1;
+wire [7:0] soc_a7ddrphy_dq_i_data1;
+wire [7:0] soc_a7ddrphy_bitslip1_i;
+reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip1_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip1_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay2;
+wire soc_a7ddrphy_dq_i_nodelay2;
+wire soc_a7ddrphy_dq_i_delayed2;
+wire soc_a7ddrphy_dq_t2;
+wire [7:0] soc_a7ddrphy_dq_i_data2;
+wire [7:0] soc_a7ddrphy_bitslip2_i;
+reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip2_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip2_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay3;
+wire soc_a7ddrphy_dq_i_nodelay3;
+wire soc_a7ddrphy_dq_i_delayed3;
+wire soc_a7ddrphy_dq_t3;
+wire [7:0] soc_a7ddrphy_dq_i_data3;
+wire [7:0] soc_a7ddrphy_bitslip3_i;
+reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip3_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip3_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay4;
+wire soc_a7ddrphy_dq_i_nodelay4;
+wire soc_a7ddrphy_dq_i_delayed4;
+wire soc_a7ddrphy_dq_t4;
+wire [7:0] soc_a7ddrphy_dq_i_data4;
+wire [7:0] soc_a7ddrphy_bitslip4_i;
+reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip4_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip4_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay5;
+wire soc_a7ddrphy_dq_i_nodelay5;
+wire soc_a7ddrphy_dq_i_delayed5;
+wire soc_a7ddrphy_dq_t5;
+wire [7:0] soc_a7ddrphy_dq_i_data5;
+wire [7:0] soc_a7ddrphy_bitslip5_i;
+reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip5_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip5_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay6;
+wire soc_a7ddrphy_dq_i_nodelay6;
+wire soc_a7ddrphy_dq_i_delayed6;
+wire soc_a7ddrphy_dq_t6;
+wire [7:0] soc_a7ddrphy_dq_i_data6;
+wire [7:0] soc_a7ddrphy_bitslip6_i;
+reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip6_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip6_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay7;
+wire soc_a7ddrphy_dq_i_nodelay7;
+wire soc_a7ddrphy_dq_i_delayed7;
+wire soc_a7ddrphy_dq_t7;
+wire [7:0] soc_a7ddrphy_dq_i_data7;
+wire [7:0] soc_a7ddrphy_bitslip7_i;
+reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip7_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip7_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay8;
+wire soc_a7ddrphy_dq_i_nodelay8;
+wire soc_a7ddrphy_dq_i_delayed8;
+wire soc_a7ddrphy_dq_t8;
+wire [7:0] soc_a7ddrphy_dq_i_data8;
+wire [7:0] soc_a7ddrphy_bitslip8_i;
+reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip8_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip8_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay9;
+wire soc_a7ddrphy_dq_i_nodelay9;
+wire soc_a7ddrphy_dq_i_delayed9;
+wire soc_a7ddrphy_dq_t9;
+wire [7:0] soc_a7ddrphy_dq_i_data9;
+wire [7:0] soc_a7ddrphy_bitslip9_i;
+reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip9_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip9_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay10;
+wire soc_a7ddrphy_dq_i_nodelay10;
+wire soc_a7ddrphy_dq_i_delayed10;
+wire soc_a7ddrphy_dq_t10;
+wire [7:0] soc_a7ddrphy_dq_i_data10;
+wire [7:0] soc_a7ddrphy_bitslip10_i;
+reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip10_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip10_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay11;
+wire soc_a7ddrphy_dq_i_nodelay11;
+wire soc_a7ddrphy_dq_i_delayed11;
+wire soc_a7ddrphy_dq_t11;
+wire [7:0] soc_a7ddrphy_dq_i_data11;
+wire [7:0] soc_a7ddrphy_bitslip11_i;
+reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip11_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip11_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay12;
+wire soc_a7ddrphy_dq_i_nodelay12;
+wire soc_a7ddrphy_dq_i_delayed12;
+wire soc_a7ddrphy_dq_t12;
+wire [7:0] soc_a7ddrphy_dq_i_data12;
+wire [7:0] soc_a7ddrphy_bitslip12_i;
+reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip12_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip12_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay13;
+wire soc_a7ddrphy_dq_i_nodelay13;
+wire soc_a7ddrphy_dq_i_delayed13;
+wire soc_a7ddrphy_dq_t13;
+wire [7:0] soc_a7ddrphy_dq_i_data13;
+wire [7:0] soc_a7ddrphy_bitslip13_i;
+reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip13_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip13_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay14;
+wire soc_a7ddrphy_dq_i_nodelay14;
+wire soc_a7ddrphy_dq_i_delayed14;
+wire soc_a7ddrphy_dq_t14;
+wire [7:0] soc_a7ddrphy_dq_i_data14;
+wire [7:0] soc_a7ddrphy_bitslip14_i;
+reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip14_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip14_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay15;
+wire soc_a7ddrphy_dq_i_nodelay15;
+wire soc_a7ddrphy_dq_i_delayed15;
+wire soc_a7ddrphy_dq_t15;
+wire [7:0] soc_a7ddrphy_dq_i_data15;
+wire [7:0] soc_a7ddrphy_bitslip15_i;
+reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip15_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip15_r = 24'd0;
+wire [7:0] soc_a7ddrphy_rddata_en;
+reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0;
+wire [3:0] soc_a7ddrphy_wrdata_en;
+reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0;
+wire [13:0] soc_litedramcore_inti_p0_address;
+wire [2:0] soc_litedramcore_inti_p0_bank;
+reg soc_litedramcore_inti_p0_cas_n = 1'd1;
+reg soc_litedramcore_inti_p0_cs_n = 1'd1;
+reg soc_litedramcore_inti_p0_ras_n = 1'd1;
+reg soc_litedramcore_inti_p0_we_n = 1'd1;
+wire soc_litedramcore_inti_p0_cke;
+wire soc_litedramcore_inti_p0_odt;
+wire soc_litedramcore_inti_p0_reset_n;
+reg soc_litedramcore_inti_p0_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p0_wrdata;
+wire soc_litedramcore_inti_p0_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p0_wrdata_mask;
+wire soc_litedramcore_inti_p0_rddata_en;
+reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0;
+reg soc_litedramcore_inti_p0_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_inti_p1_address;
+wire [2:0] soc_litedramcore_inti_p1_bank;
+reg soc_litedramcore_inti_p1_cas_n = 1'd1;
+reg soc_litedramcore_inti_p1_cs_n = 1'd1;
+reg soc_litedramcore_inti_p1_ras_n = 1'd1;
+reg soc_litedramcore_inti_p1_we_n = 1'd1;
+wire soc_litedramcore_inti_p1_cke;
+wire soc_litedramcore_inti_p1_odt;
+wire soc_litedramcore_inti_p1_reset_n;
+reg soc_litedramcore_inti_p1_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p1_wrdata;
+wire soc_litedramcore_inti_p1_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p1_wrdata_mask;
+wire soc_litedramcore_inti_p1_rddata_en;
+reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0;
+reg soc_litedramcore_inti_p1_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_inti_p2_address;
+wire [2:0] soc_litedramcore_inti_p2_bank;
+reg soc_litedramcore_inti_p2_cas_n = 1'd1;
+reg soc_litedramcore_inti_p2_cs_n = 1'd1;
+reg soc_litedramcore_inti_p2_ras_n = 1'd1;
+reg soc_litedramcore_inti_p2_we_n = 1'd1;
+wire soc_litedramcore_inti_p2_cke;
+wire soc_litedramcore_inti_p2_odt;
+wire soc_litedramcore_inti_p2_reset_n;
+reg soc_litedramcore_inti_p2_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p2_wrdata;
+wire soc_litedramcore_inti_p2_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p2_wrdata_mask;
+wire soc_litedramcore_inti_p2_rddata_en;
+reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0;
+reg soc_litedramcore_inti_p2_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_inti_p3_address;
+wire [2:0] soc_litedramcore_inti_p3_bank;
+reg soc_litedramcore_inti_p3_cas_n = 1'd1;
+reg soc_litedramcore_inti_p3_cs_n = 1'd1;
+reg soc_litedramcore_inti_p3_ras_n = 1'd1;
+reg soc_litedramcore_inti_p3_we_n = 1'd1;
+wire soc_litedramcore_inti_p3_cke;
+wire soc_litedramcore_inti_p3_odt;
+wire soc_litedramcore_inti_p3_reset_n;
+reg soc_litedramcore_inti_p3_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p3_wrdata;
+wire soc_litedramcore_inti_p3_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p3_wrdata_mask;
+wire soc_litedramcore_inti_p3_rddata_en;
+reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0;
+reg soc_litedramcore_inti_p3_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_slave_p0_address;
+wire [2:0] soc_litedramcore_slave_p0_bank;
+wire soc_litedramcore_slave_p0_cas_n;
+wire soc_litedramcore_slave_p0_cs_n;
+wire soc_litedramcore_slave_p0_ras_n;
+wire soc_litedramcore_slave_p0_we_n;
+wire soc_litedramcore_slave_p0_cke;
+wire soc_litedramcore_slave_p0_odt;
+wire soc_litedramcore_slave_p0_reset_n;
+wire soc_litedramcore_slave_p0_act_n;
+wire [31:0] soc_litedramcore_slave_p0_wrdata;
+wire soc_litedramcore_slave_p0_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p0_wrdata_mask;
+wire soc_litedramcore_slave_p0_rddata_en;
+reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
+reg soc_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_slave_p1_address;
+wire [2:0] soc_litedramcore_slave_p1_bank;
+wire soc_litedramcore_slave_p1_cas_n;
+wire soc_litedramcore_slave_p1_cs_n;
+wire soc_litedramcore_slave_p1_ras_n;
+wire soc_litedramcore_slave_p1_we_n;
+wire soc_litedramcore_slave_p1_cke;
+wire soc_litedramcore_slave_p1_odt;
+wire soc_litedramcore_slave_p1_reset_n;
+wire soc_litedramcore_slave_p1_act_n;
+wire [31:0] soc_litedramcore_slave_p1_wrdata;
+wire soc_litedramcore_slave_p1_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p1_wrdata_mask;
+wire soc_litedramcore_slave_p1_rddata_en;
+reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
+reg soc_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_slave_p2_address;
+wire [2:0] soc_litedramcore_slave_p2_bank;
+wire soc_litedramcore_slave_p2_cas_n;
+wire soc_litedramcore_slave_p2_cs_n;
+wire soc_litedramcore_slave_p2_ras_n;
+wire soc_litedramcore_slave_p2_we_n;
+wire soc_litedramcore_slave_p2_cke;
+wire soc_litedramcore_slave_p2_odt;
+wire soc_litedramcore_slave_p2_reset_n;
+wire soc_litedramcore_slave_p2_act_n;
+wire [31:0] soc_litedramcore_slave_p2_wrdata;
+wire soc_litedramcore_slave_p2_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p2_wrdata_mask;
+wire soc_litedramcore_slave_p2_rddata_en;
+reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
+reg soc_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_slave_p3_address;
+wire [2:0] soc_litedramcore_slave_p3_bank;
+wire soc_litedramcore_slave_p3_cas_n;
+wire soc_litedramcore_slave_p3_cs_n;
+wire soc_litedramcore_slave_p3_ras_n;
+wire soc_litedramcore_slave_p3_we_n;
+wire soc_litedramcore_slave_p3_cke;
+wire soc_litedramcore_slave_p3_odt;
+wire soc_litedramcore_slave_p3_reset_n;
+wire soc_litedramcore_slave_p3_act_n;
+wire [31:0] soc_litedramcore_slave_p3_wrdata;
+wire soc_litedramcore_slave_p3_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p3_wrdata_mask;
+wire soc_litedramcore_slave_p3_rddata_en;
+reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
+reg soc_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [13:0] soc_litedramcore_master_p0_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p0_bank = 3'd0;
+reg soc_litedramcore_master_p0_cas_n = 1'd1;
+reg soc_litedramcore_master_p0_cs_n = 1'd1;
+reg soc_litedramcore_master_p0_ras_n = 1'd1;
+reg soc_litedramcore_master_p0_we_n = 1'd1;
+reg soc_litedramcore_master_p0_cke = 1'd0;
+reg soc_litedramcore_master_p0_odt = 1'd0;
+reg soc_litedramcore_master_p0_reset_n = 1'd0;
+reg soc_litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
+reg soc_litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p0_rddata;
+wire soc_litedramcore_master_p0_rddata_valid;
+reg [13:0] soc_litedramcore_master_p1_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p1_bank = 3'd0;
+reg soc_litedramcore_master_p1_cas_n = 1'd1;
+reg soc_litedramcore_master_p1_cs_n = 1'd1;
+reg soc_litedramcore_master_p1_ras_n = 1'd1;
+reg soc_litedramcore_master_p1_we_n = 1'd1;
+reg soc_litedramcore_master_p1_cke = 1'd0;
+reg soc_litedramcore_master_p1_odt = 1'd0;
+reg soc_litedramcore_master_p1_reset_n = 1'd0;
+reg soc_litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
+reg soc_litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p1_rddata;
+wire soc_litedramcore_master_p1_rddata_valid;
+reg [13:0] soc_litedramcore_master_p2_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p2_bank = 3'd0;
+reg soc_litedramcore_master_p2_cas_n = 1'd1;
+reg soc_litedramcore_master_p2_cs_n = 1'd1;
+reg soc_litedramcore_master_p2_ras_n = 1'd1;
+reg soc_litedramcore_master_p2_we_n = 1'd1;
+reg soc_litedramcore_master_p2_cke = 1'd0;
+reg soc_litedramcore_master_p2_odt = 1'd0;
+reg soc_litedramcore_master_p2_reset_n = 1'd0;
+reg soc_litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
+reg soc_litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p2_rddata;
+wire soc_litedramcore_master_p2_rddata_valid;
+reg [13:0] soc_litedramcore_master_p3_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p3_bank = 3'd0;
+reg soc_litedramcore_master_p3_cas_n = 1'd1;
+reg soc_litedramcore_master_p3_cs_n = 1'd1;
+reg soc_litedramcore_master_p3_ras_n = 1'd1;
+reg soc_litedramcore_master_p3_we_n = 1'd1;
+reg soc_litedramcore_master_p3_cke = 1'd0;
+reg soc_litedramcore_master_p3_odt = 1'd0;
+reg soc_litedramcore_master_p3_reset_n = 1'd0;
+reg soc_litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
+reg soc_litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p3_rddata;
+wire soc_litedramcore_master_p3_rddata_valid;
+wire soc_litedramcore_sel;
+wire soc_litedramcore_cke;
+wire soc_litedramcore_odt;
+wire soc_litedramcore_reset_n;
+reg [3:0] soc_litedramcore_storage = 4'd1;
+reg soc_litedramcore_re = 1'd0;
+reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector0_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector0_command_issue_re;
+wire soc_litedramcore_phaseinjector0_command_issue_r;
+wire soc_litedramcore_phaseinjector0_command_issue_we;
+reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector0_status = 32'd0;
+wire soc_litedramcore_phaseinjector0_we;
+reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector1_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector1_command_issue_re;
+wire soc_litedramcore_phaseinjector1_command_issue_r;
+wire soc_litedramcore_phaseinjector1_command_issue_we;
+reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector1_status = 32'd0;
+wire soc_litedramcore_phaseinjector1_we;
+reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector2_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector2_command_issue_re;
+wire soc_litedramcore_phaseinjector2_command_issue_r;
+wire soc_litedramcore_phaseinjector2_command_issue_we;
+reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector2_status = 32'd0;
+wire soc_litedramcore_phaseinjector2_we;
+reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector3_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector3_command_issue_re;
+wire soc_litedramcore_phaseinjector3_command_issue_r;
+wire soc_litedramcore_phaseinjector3_command_issue_we;
+reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector3_status = 32'd0;
+wire soc_litedramcore_phaseinjector3_we;
+wire soc_litedramcore_interface_bank0_valid;
+wire soc_litedramcore_interface_bank0_ready;
+wire soc_litedramcore_interface_bank0_we;
+wire [20:0] soc_litedramcore_interface_bank0_addr;
+wire soc_litedramcore_interface_bank0_lock;
+wire soc_litedramcore_interface_bank0_wdata_ready;
+wire soc_litedramcore_interface_bank0_rdata_valid;
+wire soc_litedramcore_interface_bank1_valid;
+wire soc_litedramcore_interface_bank1_ready;
+wire soc_litedramcore_interface_bank1_we;
+wire [20:0] soc_litedramcore_interface_bank1_addr;
+wire soc_litedramcore_interface_bank1_lock;
+wire soc_litedramcore_interface_bank1_wdata_ready;
+wire soc_litedramcore_interface_bank1_rdata_valid;
+wire soc_litedramcore_interface_bank2_valid;
+wire soc_litedramcore_interface_bank2_ready;
+wire soc_litedramcore_interface_bank2_we;
+wire [20:0] soc_litedramcore_interface_bank2_addr;
+wire soc_litedramcore_interface_bank2_lock;
+wire soc_litedramcore_interface_bank2_wdata_ready;
+wire soc_litedramcore_interface_bank2_rdata_valid;
+wire soc_litedramcore_interface_bank3_valid;
+wire soc_litedramcore_interface_bank3_ready;
+wire soc_litedramcore_interface_bank3_we;
+wire [20:0] soc_litedramcore_interface_bank3_addr;
+wire soc_litedramcore_interface_bank3_lock;
+wire soc_litedramcore_interface_bank3_wdata_ready;
+wire soc_litedramcore_interface_bank3_rdata_valid;
+wire soc_litedramcore_interface_bank4_valid;
+wire soc_litedramcore_interface_bank4_ready;
+wire soc_litedramcore_interface_bank4_we;
+wire [20:0] soc_litedramcore_interface_bank4_addr;
+wire soc_litedramcore_interface_bank4_lock;
+wire soc_litedramcore_interface_bank4_wdata_ready;
+wire soc_litedramcore_interface_bank4_rdata_valid;
+wire soc_litedramcore_interface_bank5_valid;
+wire soc_litedramcore_interface_bank5_ready;
+wire soc_litedramcore_interface_bank5_we;
+wire [20:0] soc_litedramcore_interface_bank5_addr;
+wire soc_litedramcore_interface_bank5_lock;
+wire soc_litedramcore_interface_bank5_wdata_ready;
+wire soc_litedramcore_interface_bank5_rdata_valid;
+wire soc_litedramcore_interface_bank6_valid;
+wire soc_litedramcore_interface_bank6_ready;
+wire soc_litedramcore_interface_bank6_we;
+wire [20:0] soc_litedramcore_interface_bank6_addr;
+wire soc_litedramcore_interface_bank6_lock;
+wire soc_litedramcore_interface_bank6_wdata_ready;
+wire soc_litedramcore_interface_bank6_rdata_valid;
+wire soc_litedramcore_interface_bank7_valid;
+wire soc_litedramcore_interface_bank7_ready;
+wire soc_litedramcore_interface_bank7_we;
+wire [20:0] soc_litedramcore_interface_bank7_addr;
+wire soc_litedramcore_interface_bank7_lock;
+wire soc_litedramcore_interface_bank7_wdata_ready;
+wire soc_litedramcore_interface_bank7_rdata_valid;
+reg [127:0] soc_litedramcore_interface_wdata = 128'd0;
+reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] soc_litedramcore_interface_rdata;
+reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
+reg soc_litedramcore_dfi_p0_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p0_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p0_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p0_we_n = 1'd1;
+wire soc_litedramcore_dfi_p0_cke;
+wire soc_litedramcore_dfi_p0_odt;
+wire soc_litedramcore_dfi_p0_reset_n;
+reg soc_litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p0_wrdata;
+reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
+reg soc_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p0_rddata;
+wire soc_litedramcore_dfi_p0_rddata_valid;
+reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
+reg soc_litedramcore_dfi_p1_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p1_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p1_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p1_we_n = 1'd1;
+wire soc_litedramcore_dfi_p1_cke;
+wire soc_litedramcore_dfi_p1_odt;
+wire soc_litedramcore_dfi_p1_reset_n;
+reg soc_litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p1_wrdata;
+reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
+reg soc_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p1_rddata;
+wire soc_litedramcore_dfi_p1_rddata_valid;
+reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
+reg soc_litedramcore_dfi_p2_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p2_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p2_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p2_we_n = 1'd1;
+wire soc_litedramcore_dfi_p2_cke;
+wire soc_litedramcore_dfi_p2_odt;
+wire soc_litedramcore_dfi_p2_reset_n;
+reg soc_litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p2_wrdata;
+reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
+reg soc_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p2_rddata;
+wire soc_litedramcore_dfi_p2_rddata_valid;
+reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
+reg soc_litedramcore_dfi_p3_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p3_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p3_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p3_we_n = 1'd1;
+wire soc_litedramcore_dfi_p3_cke;
+wire soc_litedramcore_dfi_p3_odt;
+wire soc_litedramcore_dfi_p3_reset_n;
+reg soc_litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p3_wrdata;
+reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
+reg soc_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p3_rddata;
+wire soc_litedramcore_dfi_p3_rddata_valid;
+reg soc_litedramcore_cmd_valid = 1'd0;
+reg soc_litedramcore_cmd_ready = 1'd0;
+reg soc_litedramcore_cmd_last = 1'd0;
+reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
+reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
+reg soc_litedramcore_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_cmd_payload_we = 1'd0;
+reg soc_litedramcore_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_cmd_payload_is_write = 1'd0;
+wire soc_litedramcore_wants_refresh;
+wire soc_litedramcore_wants_zqcs;
+wire soc_litedramcore_timer_wait;
+wire soc_litedramcore_timer_done0;
+wire [9:0] soc_litedramcore_timer_count0;
+wire soc_litedramcore_timer_done1;
+reg [9:0] soc_litedramcore_timer_count1 = 10'd781;
+wire soc_litedramcore_postponer_req_i;
+reg soc_litedramcore_postponer_req_o = 1'd0;
+reg soc_litedramcore_postponer_count = 1'd0;
+reg soc_litedramcore_sequencer_start0 = 1'd0;
+wire soc_litedramcore_sequencer_done0;
+wire soc_litedramcore_sequencer_start1;
+reg soc_litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] soc_litedramcore_sequencer_counter = 6'd0;
+reg soc_litedramcore_sequencer_count = 1'd0;
+wire soc_litedramcore_zqcs_timer_wait;
+wire soc_litedramcore_zqcs_timer_done0;
+wire [26:0] soc_litedramcore_zqcs_timer_count0;
+wire soc_litedramcore_zqcs_timer_done1;
+reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg soc_litedramcore_zqcs_executer_start = 1'd0;
+reg soc_litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
+wire soc_litedramcore_bankmachine0_req_valid;
+wire soc_litedramcore_bankmachine0_req_ready;
+wire soc_litedramcore_bankmachine0_req_we;
+wire [20:0] soc_litedramcore_bankmachine0_req_addr;
+wire soc_litedramcore_bankmachine0_req_lock;
+reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine0_refresh_req;
+reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
+reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
+reg soc_litedramcore_bankmachine0_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine0_row_hit;
+reg soc_litedramcore_bankmachine0_row_open = 1'd0;
+reg soc_litedramcore_bankmachine0_row_close = 1'd0;
+reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_req_valid;
+wire soc_litedramcore_bankmachine1_req_ready;
+wire soc_litedramcore_bankmachine1_req_we;
+wire [20:0] soc_litedramcore_bankmachine1_req_addr;
+wire soc_litedramcore_bankmachine1_req_lock;
+reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine1_refresh_req;
+reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
+reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
+reg soc_litedramcore_bankmachine1_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine1_row_hit;
+reg soc_litedramcore_bankmachine1_row_open = 1'd0;
+reg soc_litedramcore_bankmachine1_row_close = 1'd0;
+reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_req_valid;
+wire soc_litedramcore_bankmachine2_req_ready;
+wire soc_litedramcore_bankmachine2_req_we;
+wire [20:0] soc_litedramcore_bankmachine2_req_addr;
+wire soc_litedramcore_bankmachine2_req_lock;
+reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine2_refresh_req;
+reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
+reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
+reg soc_litedramcore_bankmachine2_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine2_row_hit;
+reg soc_litedramcore_bankmachine2_row_open = 1'd0;
+reg soc_litedramcore_bankmachine2_row_close = 1'd0;
+reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_req_valid;
+wire soc_litedramcore_bankmachine3_req_ready;
+wire soc_litedramcore_bankmachine3_req_we;
+wire [20:0] soc_litedramcore_bankmachine3_req_addr;
+wire soc_litedramcore_bankmachine3_req_lock;
+reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine3_refresh_req;
+reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
+reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
+reg soc_litedramcore_bankmachine3_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine3_row_hit;
+reg soc_litedramcore_bankmachine3_row_open = 1'd0;
+reg soc_litedramcore_bankmachine3_row_close = 1'd0;
+reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_req_valid;
+wire soc_litedramcore_bankmachine4_req_ready;
+wire soc_litedramcore_bankmachine4_req_we;
+wire [20:0] soc_litedramcore_bankmachine4_req_addr;
+wire soc_litedramcore_bankmachine4_req_lock;
+reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine4_refresh_req;
+reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
+reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
+reg soc_litedramcore_bankmachine4_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine4_row_hit;
+reg soc_litedramcore_bankmachine4_row_open = 1'd0;
+reg soc_litedramcore_bankmachine4_row_close = 1'd0;
+reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_req_valid;
+wire soc_litedramcore_bankmachine5_req_ready;
+wire soc_litedramcore_bankmachine5_req_we;
+wire [20:0] soc_litedramcore_bankmachine5_req_addr;
+wire soc_litedramcore_bankmachine5_req_lock;
+reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine5_refresh_req;
+reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
+reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
+reg soc_litedramcore_bankmachine5_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine5_row_hit;
+reg soc_litedramcore_bankmachine5_row_open = 1'd0;
+reg soc_litedramcore_bankmachine5_row_close = 1'd0;
+reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_req_valid;
+wire soc_litedramcore_bankmachine6_req_ready;
+wire soc_litedramcore_bankmachine6_req_we;
+wire [20:0] soc_litedramcore_bankmachine6_req_addr;
+wire soc_litedramcore_bankmachine6_req_lock;
+reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine6_refresh_req;
+reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
+reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
+reg soc_litedramcore_bankmachine6_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine6_row_hit;
+reg soc_litedramcore_bankmachine6_row_open = 1'd0;
+reg soc_litedramcore_bankmachine6_row_close = 1'd0;
+reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_req_valid;
+wire soc_litedramcore_bankmachine7_req_ready;
+wire soc_litedramcore_bankmachine7_req_we;
+wire [20:0] soc_litedramcore_bankmachine7_req_addr;
+wire soc_litedramcore_bankmachine7_req_lock;
+reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine7_refresh_req;
+reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
+reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
+reg soc_litedramcore_bankmachine7_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine7_row_hit;
+reg soc_litedramcore_bankmachine7_row_open = 1'd0;
+reg soc_litedramcore_bankmachine7_row_close = 1'd0;
+reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
+wire soc_litedramcore_ras_allowed;
+wire soc_litedramcore_cas_allowed;
+reg soc_litedramcore_choose_cmd_want_reads = 1'd0;
+reg soc_litedramcore_choose_cmd_want_writes = 1'd0;
+reg soc_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg soc_litedramcore_choose_cmd_want_activates = 1'd0;
+wire soc_litedramcore_choose_cmd_cmd_valid;
+reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
+reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_read;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] soc_litedramcore_choose_cmd_request;
+reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
+wire soc_litedramcore_choose_cmd_ce;
+reg soc_litedramcore_choose_req_want_reads = 1'd0;
+reg soc_litedramcore_choose_req_want_writes = 1'd0;
+reg soc_litedramcore_choose_req_want_cmds = 1'd0;
+reg soc_litedramcore_choose_req_want_activates = 1'd0;
+wire soc_litedramcore_choose_req_cmd_valid;
+reg soc_litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] soc_litedramcore_choose_req_cmd_payload_a;
+wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
+reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire soc_litedramcore_choose_req_cmd_payload_is_cmd;
+wire soc_litedramcore_choose_req_cmd_payload_is_read;
+wire soc_litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] soc_litedramcore_choose_req_valids = 8'd0;
+wire [7:0] soc_litedramcore_choose_req_request;
+reg [2:0] soc_litedramcore_choose_req_grant = 3'd0;
+wire soc_litedramcore_choose_req_ce;
+reg [13:0] soc_litedramcore_nop_a = 14'd0;
+reg [2:0] soc_litedramcore_nop_ba = 3'd0;
+reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
+reg soc_litedramcore_steerer0 = 1'd1;
+reg soc_litedramcore_steerer1 = 1'd1;
+reg soc_litedramcore_steerer2 = 1'd1;
+reg soc_litedramcore_steerer3 = 1'd1;
+reg soc_litedramcore_steerer4 = 1'd1;
+reg soc_litedramcore_steerer5 = 1'd1;
+reg soc_litedramcore_steerer6 = 1'd1;
+reg soc_litedramcore_steerer7 = 1'd1;
+wire soc_litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0;
+reg soc_litedramcore_trrdcon_count = 1'd0;
+wire soc_litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] soc_litedramcore_tfawcon_count;
+reg [4:0] soc_litedramcore_tfawcon_window = 5'd0;
+wire soc_litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0;
+reg soc_litedramcore_tccdcon_count = 1'd0;
+wire soc_litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_twtrcon_count = 3'd0;
+wire soc_litedramcore_read_available;
+wire soc_litedramcore_write_available;
+reg soc_litedramcore_en0 = 1'd0;
+wire soc_litedramcore_max_time0;
+reg [4:0] soc_litedramcore_time0 = 5'd0;
+reg soc_litedramcore_en1 = 1'd0;
+wire soc_litedramcore_max_time1;
+reg [3:0] soc_litedramcore_time1 = 4'd0;
+wire soc_litedramcore_go_to_refresh;
+reg soc_init_done_storage = 1'd0;
+reg soc_init_done_re = 1'd0;
+reg soc_init_error_storage = 1'd0;
+reg soc_init_error_re = 1'd0;
+wire [29:0] soc_wb_bus_adr;
+wire [31:0] soc_wb_bus_dat_w;
+wire [31:0] soc_wb_bus_dat_r;
+wire [3:0] soc_wb_bus_sel;
+wire soc_wb_bus_cyc;
+wire soc_wb_bus_stb;
+wire soc_wb_bus_ack;
+wire soc_wb_bus_we;
+wire [2:0] soc_wb_bus_cti;
+wire [1:0] soc_wb_bus_bte;
+wire soc_wb_bus_err;
+wire soc_user_port_cmd_valid;
+wire soc_user_port_cmd_ready;
+wire soc_user_port_cmd_payload_we;
+wire [23:0] soc_user_port_cmd_payload_addr;
+wire soc_user_port_wdata_valid;
+wire soc_user_port_wdata_ready;
+wire [127:0] soc_user_port_wdata_payload_data;
+wire [15:0] soc_user_port_wdata_payload_we;
+wire soc_user_port_rdata_valid;
+wire soc_user_port_rdata_ready;
+wire [127:0] soc_user_port_rdata_payload_data;
+reg vns_state = 1'd0;
+reg vns_next_state = 1'd0;
+wire vns_pll_fb;
+reg [1:0] vns_refresher_state = 2'd0;
+reg [1:0] vns_refresher_next_state = 2'd0;
+reg [3:0] vns_bankmachine0_state = 4'd0;
+reg [3:0] vns_bankmachine0_next_state = 4'd0;
+reg [3:0] vns_bankmachine1_state = 4'd0;
+reg [3:0] vns_bankmachine1_next_state = 4'd0;
+reg [3:0] vns_bankmachine2_state = 4'd0;
+reg [3:0] vns_bankmachine2_next_state = 4'd0;
+reg [3:0] vns_bankmachine3_state = 4'd0;
+reg [3:0] vns_bankmachine3_next_state = 4'd0;
+reg [3:0] vns_bankmachine4_state = 4'd0;
+reg [3:0] vns_bankmachine4_next_state = 4'd0;
+reg [3:0] vns_bankmachine5_state = 4'd0;
+reg [3:0] vns_bankmachine5_next_state = 4'd0;
+reg [3:0] vns_bankmachine6_state = 4'd0;
+reg [3:0] vns_bankmachine6_next_state = 4'd0;
+reg [3:0] vns_bankmachine7_state = 4'd0;
+reg [3:0] vns_bankmachine7_next_state = 4'd0;
+reg [3:0] vns_multiplexer_state = 4'd0;
+reg [3:0] vns_multiplexer_next_state = 4'd0;
+wire vns_roundrobin0_request;
+wire vns_roundrobin0_grant;
+wire vns_roundrobin0_ce;
+wire vns_roundrobin1_request;
+wire vns_roundrobin1_grant;
+wire vns_roundrobin1_ce;
+wire vns_roundrobin2_request;
+wire vns_roundrobin2_grant;
+wire vns_roundrobin2_ce;
+wire vns_roundrobin3_request;
+wire vns_roundrobin3_grant;
+wire vns_roundrobin3_ce;
+wire vns_roundrobin4_request;
+wire vns_roundrobin4_grant;
+wire vns_roundrobin4_ce;
+wire vns_roundrobin5_request;
+wire vns_roundrobin5_grant;
+wire vns_roundrobin5_ce;
+wire vns_roundrobin6_request;
+wire vns_roundrobin6_grant;
+wire vns_roundrobin6_ce;
+wire vns_roundrobin7_request;
+wire vns_roundrobin7_grant;
+wire vns_roundrobin7_ce;
+reg vns_locked0 = 1'd0;
+reg vns_locked1 = 1'd0;
+reg vns_locked2 = 1'd0;
+reg vns_locked3 = 1'd0;
+reg vns_locked4 = 1'd0;
+reg vns_locked5 = 1'd0;
+reg vns_locked6 = 1'd0;
+reg vns_locked7 = 1'd0;
+reg vns_new_master_wdata_ready0 = 1'd0;
+reg vns_new_master_wdata_ready1 = 1'd0;
+reg vns_new_master_wdata_ready2 = 1'd0;
+reg vns_new_master_rdata_valid0 = 1'd0;
+reg vns_new_master_rdata_valid1 = 1'd0;
+reg vns_new_master_rdata_valid2 = 1'd0;
+reg vns_new_master_rdata_valid3 = 1'd0;
+reg vns_new_master_rdata_valid4 = 1'd0;
+reg vns_new_master_rdata_valid5 = 1'd0;
+reg vns_new_master_rdata_valid6 = 1'd0;
+reg vns_new_master_rdata_valid7 = 1'd0;
+reg vns_new_master_rdata_valid8 = 1'd0;
+wire [13:0] vns_interface0_bank_bus_adr;
+wire vns_interface0_bank_bus_we;
+wire [31:0] vns_interface0_bank_bus_dat_w;
+reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0;
+wire vns_csrbank0_init_done0_re;
+wire vns_csrbank0_init_done0_r;
+wire vns_csrbank0_init_done0_we;
+wire vns_csrbank0_init_done0_w;
+wire vns_csrbank0_init_error0_re;
+wire vns_csrbank0_init_error0_r;
+wire vns_csrbank0_init_error0_we;
+wire vns_csrbank0_init_error0_w;
+wire vns_csrbank0_sel;
+wire [13:0] vns_interface1_bank_bus_adr;
+wire vns_interface1_bank_bus_we;
+wire [31:0] vns_interface1_bank_bus_dat_w;
+reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0;
+wire vns_csrbank1_half_sys8x_taps0_re;
+wire [4:0] vns_csrbank1_half_sys8x_taps0_r;
+wire vns_csrbank1_half_sys8x_taps0_we;
+wire [4:0] vns_csrbank1_half_sys8x_taps0_w;
+wire vns_csrbank1_wlevel_en0_re;
+wire vns_csrbank1_wlevel_en0_r;
+wire vns_csrbank1_wlevel_en0_we;
+wire vns_csrbank1_wlevel_en0_w;
+wire vns_csrbank1_dly_sel0_re;
+wire [1:0] vns_csrbank1_dly_sel0_r;
+wire vns_csrbank1_dly_sel0_we;
+wire [1:0] vns_csrbank1_dly_sel0_w;
+wire vns_csrbank1_sel;
+wire [13:0] vns_interface2_bank_bus_adr;
+wire vns_interface2_bank_bus_we;
+wire [31:0] vns_interface2_bank_bus_dat_w;
+reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0;
+wire vns_csrbank2_dfii_control0_re;
+wire [3:0] vns_csrbank2_dfii_control0_r;
+wire vns_csrbank2_dfii_control0_we;
+wire [3:0] vns_csrbank2_dfii_control0_w;
+wire vns_csrbank2_dfii_pi0_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi0_command0_r;
+wire vns_csrbank2_dfii_pi0_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi0_command0_w;
+wire vns_csrbank2_dfii_pi0_address0_re;
+wire [13:0] vns_csrbank2_dfii_pi0_address0_r;
+wire vns_csrbank2_dfii_pi0_address0_we;
+wire [13:0] vns_csrbank2_dfii_pi0_address0_w;
+wire vns_csrbank2_dfii_pi0_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r;
+wire vns_csrbank2_dfii_pi0_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w;
+wire vns_csrbank2_dfii_pi0_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r;
+wire vns_csrbank2_dfii_pi0_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w;
+wire vns_csrbank2_dfii_pi0_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi0_rddata_r;
+wire vns_csrbank2_dfii_pi0_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi0_rddata_w;
+wire vns_csrbank2_dfii_pi1_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi1_command0_r;
+wire vns_csrbank2_dfii_pi1_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi1_command0_w;
+wire vns_csrbank2_dfii_pi1_address0_re;
+wire [13:0] vns_csrbank2_dfii_pi1_address0_r;
+wire vns_csrbank2_dfii_pi1_address0_we;
+wire [13:0] vns_csrbank2_dfii_pi1_address0_w;
+wire vns_csrbank2_dfii_pi1_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r;
+wire vns_csrbank2_dfii_pi1_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w;
+wire vns_csrbank2_dfii_pi1_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r;
+wire vns_csrbank2_dfii_pi1_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w;
+wire vns_csrbank2_dfii_pi1_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi1_rddata_r;
+wire vns_csrbank2_dfii_pi1_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi1_rddata_w;
+wire vns_csrbank2_dfii_pi2_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi2_command0_r;
+wire vns_csrbank2_dfii_pi2_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi2_command0_w;
+wire vns_csrbank2_dfii_pi2_address0_re;
+wire [13:0] vns_csrbank2_dfii_pi2_address0_r;
+wire vns_csrbank2_dfii_pi2_address0_we;
+wire [13:0] vns_csrbank2_dfii_pi2_address0_w;
+wire vns_csrbank2_dfii_pi2_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r;
+wire vns_csrbank2_dfii_pi2_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w;
+wire vns_csrbank2_dfii_pi2_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r;
+wire vns_csrbank2_dfii_pi2_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w;
+wire vns_csrbank2_dfii_pi2_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi2_rddata_r;
+wire vns_csrbank2_dfii_pi2_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi2_rddata_w;
+wire vns_csrbank2_dfii_pi3_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi3_command0_r;
+wire vns_csrbank2_dfii_pi3_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi3_command0_w;
+wire vns_csrbank2_dfii_pi3_address0_re;
+wire [13:0] vns_csrbank2_dfii_pi3_address0_r;
+wire vns_csrbank2_dfii_pi3_address0_we;
+wire [13:0] vns_csrbank2_dfii_pi3_address0_w;
+wire vns_csrbank2_dfii_pi3_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r;
+wire vns_csrbank2_dfii_pi3_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w;
+wire vns_csrbank2_dfii_pi3_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r;
+wire vns_csrbank2_dfii_pi3_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w;
+wire vns_csrbank2_dfii_pi3_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi3_rddata_r;
+wire vns_csrbank2_dfii_pi3_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi3_rddata_w;
+wire vns_csrbank2_sel;
+wire [13:0] vns_adr;
+wire vns_we;
+wire [31:0] vns_dat_w;
+wire [31:0] vns_dat_r;
+reg vns_rhs_array_muxed0 = 1'd0;
+reg [13:0] vns_rhs_array_muxed1 = 14'd0;
+reg [2:0] vns_rhs_array_muxed2 = 3'd0;
+reg vns_rhs_array_muxed3 = 1'd0;
+reg vns_rhs_array_muxed4 = 1'd0;
+reg vns_rhs_array_muxed5 = 1'd0;
+reg vns_t_array_muxed0 = 1'd0;
+reg vns_t_array_muxed1 = 1'd0;
+reg vns_t_array_muxed2 = 1'd0;
+reg vns_rhs_array_muxed6 = 1'd0;
+reg [13:0] vns_rhs_array_muxed7 = 14'd0;
+reg [2:0] vns_rhs_array_muxed8 = 3'd0;
+reg vns_rhs_array_muxed9 = 1'd0;
+reg vns_rhs_array_muxed10 = 1'd0;
+reg vns_rhs_array_muxed11 = 1'd0;
+reg vns_t_array_muxed3 = 1'd0;
+reg vns_t_array_muxed4 = 1'd0;
+reg vns_t_array_muxed5 = 1'd0;
+reg [20:0] vns_rhs_array_muxed12 = 21'd0;
+reg vns_rhs_array_muxed13 = 1'd0;
+reg vns_rhs_array_muxed14 = 1'd0;
+reg [20:0] vns_rhs_array_muxed15 = 21'd0;
+reg vns_rhs_array_muxed16 = 1'd0;
+reg vns_rhs_array_muxed17 = 1'd0;
+reg [20:0] vns_rhs_array_muxed18 = 21'd0;
+reg vns_rhs_array_muxed19 = 1'd0;
+reg vns_rhs_array_muxed20 = 1'd0;
+reg [20:0] vns_rhs_array_muxed21 = 21'd0;
+reg vns_rhs_array_muxed22 = 1'd0;
+reg vns_rhs_array_muxed23 = 1'd0;
+reg [20:0] vns_rhs_array_muxed24 = 21'd0;
+reg vns_rhs_array_muxed25 = 1'd0;
+reg vns_rhs_array_muxed26 = 1'd0;
+reg [20:0] vns_rhs_array_muxed27 = 21'd0;
+reg vns_rhs_array_muxed28 = 1'd0;
+reg vns_rhs_array_muxed29 = 1'd0;
+reg [20:0] vns_rhs_array_muxed30 = 21'd0;
+reg vns_rhs_array_muxed31 = 1'd0;
+reg vns_rhs_array_muxed32 = 1'd0;
+reg [20:0] vns_rhs_array_muxed33 = 21'd0;
+reg vns_rhs_array_muxed34 = 1'd0;
+reg vns_rhs_array_muxed35 = 1'd0;
+reg [2:0] vns_array_muxed0 = 3'd0;
+reg [13:0] vns_array_muxed1 = 14'd0;
+reg vns_array_muxed2 = 1'd0;
+reg vns_array_muxed3 = 1'd0;
+reg vns_array_muxed4 = 1'd0;
+reg vns_array_muxed5 = 1'd0;
+reg vns_array_muxed6 = 1'd0;
+reg [2:0] vns_array_muxed7 = 3'd0;
+reg [13:0] vns_array_muxed8 = 14'd0;
+reg vns_array_muxed9 = 1'd0;
+reg vns_array_muxed10 = 1'd0;
+reg vns_array_muxed11 = 1'd0;
+reg vns_array_muxed12 = 1'd0;
+reg vns_array_muxed13 = 1'd0;
+reg [2:0] vns_array_muxed14 = 3'd0;
+reg [13:0] vns_array_muxed15 = 14'd0;
+reg vns_array_muxed16 = 1'd0;
+reg vns_array_muxed17 = 1'd0;
+reg vns_array_muxed18 = 1'd0;
+reg vns_array_muxed19 = 1'd0;
+reg vns_array_muxed20 = 1'd0;
+reg [2:0] vns_array_muxed21 = 3'd0;
+reg [13:0] vns_array_muxed22 = 14'd0;
+reg vns_array_muxed23 = 1'd0;
+reg vns_array_muxed24 = 1'd0;
+reg vns_array_muxed25 = 1'd0;
+reg vns_array_muxed26 = 1'd0;
+reg vns_array_muxed27 = 1'd0;
+wire vns_xilinxasyncresetsynchronizerimpl0;
+wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl1;
+wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl2;
+wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl2_expr;
+wire vns_xilinxasyncresetsynchronizerimpl3;
+wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl3_expr;
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
-assign init_done = init_done_storage;
-assign init_error = init_error_storage;
-assign wb_bus_adr = wb_ctrl_adr;
-assign wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = wb_bus_dat_r;
-assign wb_bus_sel = wb_ctrl_sel;
-assign wb_bus_cyc = wb_ctrl_cyc;
-assign wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = wb_bus_ack;
-assign wb_bus_we = wb_ctrl_we;
-assign wb_bus_cti = wb_ctrl_cti;
-assign wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = wb_bus_err;
+assign init_done = soc_init_done_storage;
+assign init_error = soc_init_error_storage;
+assign soc_wb_bus_adr = wb_ctrl_adr;
+assign soc_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = soc_wb_bus_dat_r;
+assign soc_wb_bus_sel = wb_ctrl_sel;
+assign soc_wb_bus_cyc = wb_ctrl_cyc;
+assign soc_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = soc_wb_bus_ack;
+assign soc_wb_bus_we = wb_ctrl_we;
+assign soc_wb_bus_cti = wb_ctrl_cti;
+assign soc_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = soc_wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
-assign user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = user_port_cmd_ready;
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = user_port_wdata_ready;
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = user_port_rdata_valid;
-assign user_port_rdata_ready = user_port_native_0_rdata_ready;
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
-assign litedramcore_dat_w = litedramcore_wishbone_dat_w;
-assign litedramcore_wishbone_dat_r = litedramcore_dat_r;
+assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready;
+assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready;
+assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid;
+assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data;
+assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w;
+assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r;
// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
- next_state <= 1'd0;
- next_state <= state;
- case (state)
+ vns_next_state <= 1'd0;
+ vns_next_state <= vns_state;
+ case (vns_state)
1'd1: begin
- next_state <= 1'd0;
+ vns_next_state <= 1'd0;
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- next_state <= 1'd1;
+ if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
+ vns_next_state <= 1'd1;
end
end
endcase
reg dummy_d_1;
// synthesis translate_on
always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (state)
+ soc_litedramcore_wishbone_ack <= 1'd0;
+ case (vns_state)
1'd1: begin
- litedramcore_wishbone_ack <= 1'd1;
+ soc_litedramcore_wishbone_ack <= 1'd1;
end
default: begin
end
reg dummy_d_2;
// synthesis translate_on
always @(*) begin
- litedramcore_adr <= 14'd0;
- case (state)
+ soc_litedramcore_adr <= 14'd0;
+ case (vns_state)
1'd1: begin
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr <= litedramcore_wishbone_adr;
+ if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
+ soc_litedramcore_adr <= soc_litedramcore_wishbone_adr;
end
end
endcase
reg dummy_d_3;
// synthesis translate_on
always @(*) begin
- litedramcore_we <= 1'd0;
- case (state)
+ soc_litedramcore_we <= 1'd0;
+ case (vns_state)
1'd1: begin
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
+ soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0));
end
end
endcase
dummy_d_3 = dummy_s;
// synthesis translate_on
end
-assign sys_pll_reset = rst;
-assign pll_locked = sys_pll_locked;
-assign iodelay_pll_reset = rst;
-assign s7pll0_clkin = clk;
-assign sys_clk = s7pll0_clkout_buf0;
-assign sys4x_clk = s7pll0_clkout_buf1;
-assign sys4x_dqs_clk = s7pll0_clkout_buf2;
-assign s7pll1_clkin = clk;
-assign iodelay_clk = s7pll1_clkout_buf;
-assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0;
+assign soc_reset = rst;
+assign pll_locked = soc_locked;
+assign soc_clkin = clk;
+assign iodelay_clk = soc_clkout_buf0;
+assign sys_clk = soc_clkout_buf1;
+assign sys4x_clk = soc_clkout_buf2;
+assign sys4x_dqs_clk = soc_clkout_buf3;
+assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
// synthesis translate_off
reg dummy_d_4;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p0_rddata <= 32'd0;
- a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip0_o[0];
- a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip0_o[1];
- a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip1_o[0];
- a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip1_o[1];
- a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip2_o[0];
- a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip2_o[1];
- a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip3_o[0];
- a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip3_o[1];
- a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip4_o[0];
- a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip4_o[1];
- a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip5_o[0];
- a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip5_o[1];
- a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip6_o[0];
- a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip6_o[1];
- a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip7_o[0];
- a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip7_o[1];
- a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip8_o[0];
- a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip8_o[1];
- a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip9_o[0];
- a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip9_o[1];
- a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip10_o[0];
- a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip10_o[1];
- a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip11_o[0];
- a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip11_o[1];
- a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip12_o[0];
- a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip12_o[1];
- a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip13_o[0];
- a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip13_o[1];
- a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip14_o[0];
- a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip14_o[1];
- a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0];
- a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1];
+ soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
// synthesis translate_off
dummy_d_4 = dummy_s;
// synthesis translate_on
reg dummy_d_5;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p1_rddata <= 32'd0;
- a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip0_o[2];
- a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip0_o[3];
- a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip1_o[2];
- a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip1_o[3];
- a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip2_o[2];
- a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip2_o[3];
- a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip3_o[2];
- a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip3_o[3];
- a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip4_o[2];
- a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip4_o[3];
- a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip5_o[2];
- a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip5_o[3];
- a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip6_o[2];
- a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip6_o[3];
- a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip7_o[2];
- a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip7_o[3];
- a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip8_o[2];
- a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip8_o[3];
- a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip9_o[2];
- a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip9_o[3];
- a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip10_o[2];
- a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip10_o[3];
- a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip11_o[2];
- a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip11_o[3];
- a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip12_o[2];
- a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip12_o[3];
- a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip13_o[2];
- a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip13_o[3];
- a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip14_o[2];
- a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip14_o[3];
- a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2];
- a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3];
+ soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
// synthesis translate_off
dummy_d_5 = dummy_s;
// synthesis translate_on
reg dummy_d_6;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p2_rddata <= 32'd0;
- a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip0_o[4];
- a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip0_o[5];
- a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip1_o[4];
- a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip1_o[5];
- a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip2_o[4];
- a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip2_o[5];
- a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip3_o[4];
- a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip3_o[5];
- a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip4_o[4];
- a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip4_o[5];
- a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip5_o[4];
- a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip5_o[5];
- a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip6_o[4];
- a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip6_o[5];
- a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip7_o[4];
- a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip7_o[5];
- a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip8_o[4];
- a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip8_o[5];
- a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip9_o[4];
- a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip9_o[5];
- a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip10_o[4];
- a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip10_o[5];
- a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip11_o[4];
- a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip11_o[5];
- a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip12_o[4];
- a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip12_o[5];
- a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip13_o[4];
- a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip13_o[5];
- a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip14_o[4];
- a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip14_o[5];
- a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4];
- a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5];
+ soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
// synthesis translate_off
dummy_d_6 = dummy_s;
// synthesis translate_on
reg dummy_d_7;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p3_rddata <= 32'd0;
- a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip0_o[6];
- a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip0_o[7];
- a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip1_o[6];
- a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip1_o[7];
- a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip2_o[6];
- a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip2_o[7];
- a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip3_o[6];
- a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip3_o[7];
- a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip4_o[6];
- a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip4_o[7];
- a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip5_o[6];
- a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip5_o[7];
- a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip6_o[6];
- a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip6_o[7];
- a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip7_o[6];
- a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip7_o[7];
- a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip8_o[6];
- a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip8_o[7];
- a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip9_o[6];
- a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip9_o[7];
- a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip10_o[6];
- a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip10_o[7];
- a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip11_o[6];
- a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip11_o[7];
- a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip12_o[6];
- a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip12_o[7];
- a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip13_o[6];
- a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip13_o[7];
- a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip14_o[6];
- a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip14_o[7];
- a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6];
- a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7];
+ soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
// synthesis translate_off
dummy_d_7 = dummy_s;
// synthesis translate_on
end
-assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1;
-assign a7ddrphy_bitslip2_i = a7ddrphy_dq_i_data2;
-assign a7ddrphy_bitslip3_i = a7ddrphy_dq_i_data3;
-assign a7ddrphy_bitslip4_i = a7ddrphy_dq_i_data4;
-assign a7ddrphy_bitslip5_i = a7ddrphy_dq_i_data5;
-assign a7ddrphy_bitslip6_i = a7ddrphy_dq_i_data6;
-assign a7ddrphy_bitslip7_i = a7ddrphy_dq_i_data7;
-assign a7ddrphy_bitslip8_i = a7ddrphy_dq_i_data8;
-assign a7ddrphy_bitslip9_i = a7ddrphy_dq_i_data9;
-assign a7ddrphy_bitslip10_i = a7ddrphy_dq_i_data10;
-assign a7ddrphy_bitslip11_i = a7ddrphy_dq_i_data11;
-assign a7ddrphy_bitslip12_i = a7ddrphy_dq_i_data12;
-assign a7ddrphy_bitslip13_i = a7ddrphy_dq_i_data13;
-assign a7ddrphy_bitslip14_i = a7ddrphy_dq_i_data14;
-assign a7ddrphy_bitslip15_i = a7ddrphy_dq_i_data15;
-assign a7ddrphy_rddata_en = {a7ddrphy_rddata_en_last, a7ddrphy_dfi_p2_rddata_en};
-assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en};
-assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2];
+assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
+assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
+assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
+assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
+assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
+assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
+assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
+assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
+assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
+assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
+assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
+assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
+assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
+assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
+assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
+assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en};
+assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en};
+assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2];
// synthesis translate_off
reg dummy_d_8;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dqs_oe <= 1'd0;
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqs_oe <= 1'd1;
+ soc_a7ddrphy_dqs_oe <= 1'd0;
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqs_oe <= 1'd1;
end else begin
- a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+ soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe;
end
// synthesis translate_off
dummy_d_8 = dummy_s;
// synthesis translate_on
end
-assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2]));
-assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2]));
+assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2]));
+assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2]));
// synthesis translate_off
reg dummy_d_9;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dqspattern_o0 <= 8'd0;
- a7ddrphy_dqspattern_o0 <= 7'd85;
- if (a7ddrphy_dqspattern0) begin
- a7ddrphy_dqspattern_o0 <= 5'd21;
+ soc_a7ddrphy_dqspattern_o0 <= 8'd0;
+ soc_a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (soc_a7ddrphy_dqspattern0) begin
+ soc_a7ddrphy_dqspattern_o0 <= 5'd21;
end
- if (a7ddrphy_dqspattern1) begin
- a7ddrphy_dqspattern_o0 <= 7'd84;
+ if (soc_a7ddrphy_dqspattern1) begin
+ soc_a7ddrphy_dqspattern_o0 <= 7'd84;
end
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqspattern_o0 <= 1'd0;
- if (a7ddrphy_wlevel_strobe_re) begin
- a7ddrphy_dqspattern_o0 <= 1'd1;
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (soc_a7ddrphy_wlevel_strobe_re) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd1;
end
end
// synthesis translate_off
reg dummy_d_10;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip0_o <= 8'd0;
- case (a7ddrphy_bitslip0_value)
+ soc_a7ddrphy_bitslip0_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip0_value)
1'd0: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[7:0];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[8:1];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[9:2];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[10:3];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[11:4];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[12:5];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[13:6];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_11;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip1_o <= 8'd0;
- case (a7ddrphy_bitslip1_value)
+ soc_a7ddrphy_bitslip1_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip1_value)
1'd0: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[7:0];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[8:1];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[9:2];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[10:3];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[11:4];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[12:5];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[13:6];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_12;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip2_o <= 8'd0;
- case (a7ddrphy_bitslip2_value)
+ soc_a7ddrphy_bitslip2_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip2_value)
1'd0: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[7:0];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[8:1];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[9:2];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[10:3];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[11:4];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[12:5];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[13:6];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_13;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip3_o <= 8'd0;
- case (a7ddrphy_bitslip3_value)
+ soc_a7ddrphy_bitslip3_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip3_value)
1'd0: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[7:0];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[8:1];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[9:2];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[10:3];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[11:4];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[12:5];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[13:6];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_14;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip4_o <= 8'd0;
- case (a7ddrphy_bitslip4_value)
+ soc_a7ddrphy_bitslip4_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip4_value)
1'd0: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[7:0];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[8:1];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[9:2];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[10:3];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[11:4];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[12:5];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[13:6];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_15;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip5_o <= 8'd0;
- case (a7ddrphy_bitslip5_value)
+ soc_a7ddrphy_bitslip5_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip5_value)
1'd0: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[7:0];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[8:1];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[9:2];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[10:3];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[11:4];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[12:5];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[13:6];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_16;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip6_o <= 8'd0;
- case (a7ddrphy_bitslip6_value)
+ soc_a7ddrphy_bitslip6_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip6_value)
1'd0: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[7:0];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[8:1];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[9:2];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[10:3];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[11:4];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[12:5];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[13:6];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_17;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip7_o <= 8'd0;
- case (a7ddrphy_bitslip7_value)
+ soc_a7ddrphy_bitslip7_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip7_value)
1'd0: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[7:0];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[8:1];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[9:2];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[10:3];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[11:4];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[12:5];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[13:6];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_18;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip8_o <= 8'd0;
- case (a7ddrphy_bitslip8_value)
+ soc_a7ddrphy_bitslip8_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip8_value)
1'd0: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[7:0];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[8:1];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[9:2];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[10:3];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[11:4];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[12:5];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[13:6];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_19;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip9_o <= 8'd0;
- case (a7ddrphy_bitslip9_value)
+ soc_a7ddrphy_bitslip9_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip9_value)
1'd0: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[7:0];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[8:1];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[9:2];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[10:3];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[11:4];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[12:5];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[13:6];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_20;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip10_o <= 8'd0;
- case (a7ddrphy_bitslip10_value)
+ soc_a7ddrphy_bitslip10_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip10_value)
1'd0: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[7:0];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[8:1];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[9:2];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[10:3];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[11:4];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[12:5];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[13:6];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_21;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip11_o <= 8'd0;
- case (a7ddrphy_bitslip11_value)
+ soc_a7ddrphy_bitslip11_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip11_value)
1'd0: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[7:0];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[8:1];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[9:2];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[10:3];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[11:4];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[12:5];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[13:6];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_22;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip12_o <= 8'd0;
- case (a7ddrphy_bitslip12_value)
+ soc_a7ddrphy_bitslip12_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip12_value)
1'd0: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[7:0];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[8:1];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[9:2];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[10:3];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[11:4];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[12:5];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[13:6];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_23;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip13_o <= 8'd0;
- case (a7ddrphy_bitslip13_value)
+ soc_a7ddrphy_bitslip13_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip13_value)
1'd0: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[7:0];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[8:1];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[9:2];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[10:3];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[11:4];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[12:5];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[13:6];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_24;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip14_o <= 8'd0;
- case (a7ddrphy_bitslip14_value)
+ soc_a7ddrphy_bitslip14_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip14_value)
1'd0: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[7:0];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[8:1];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[9:2];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[10:3];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[11:4];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[12:5];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[13:6];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_25;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip15_o <= 8'd0;
- case (a7ddrphy_bitslip15_value)
+ soc_a7ddrphy_bitslip15_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip15_value)
1'd0: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[7:0];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[8:1];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[9:2];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[10:3];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[11:4];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[12:5];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[13:6];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[22:15];
end
endcase
// synthesis translate_off
dummy_d_25 = dummy_s;
// synthesis translate_on
end
-assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
-assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
-assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
-assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
-assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
-assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
-assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
-assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
-assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
-assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
-assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
-assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
-assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
-assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
-assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
-assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
-assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
-assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
-assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
-assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
-assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
-assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
-assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
-assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
-assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
-assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
-assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
-assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
-assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
-assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
-assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
-assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
-assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
-assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
-assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
-assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
-assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
-assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
-assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
-assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
-assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
-assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
-assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
-assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
-assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
-assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
-assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
-assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
-assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
-assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
-assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
-assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
-assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
-assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
-assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
-assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
-assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
-assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
-assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
-assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
-assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
-assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
-assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
-assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
-assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
-assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
-assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
-assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
-assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
-assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
-assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
-assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
-assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
-assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
-assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
-assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
-assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
-assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
-assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
-assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
-assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
-assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
-assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
-assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
-assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
-assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
-assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
-assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
-assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
-assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
-assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
-assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
-assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
-assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
-assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
-assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
-assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
-assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
-assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
-assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
-assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
-assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
-assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
-assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
-assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
-assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
-assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
-assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
-assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
-assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
-assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
-assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
-assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
-assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
-assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
-assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
-assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
-assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
-assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
-assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
-assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
-assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
-assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
-assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
-assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
-assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
-assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+assign soc_a7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address;
+assign soc_a7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank;
+assign soc_a7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n;
+assign soc_a7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n;
+assign soc_a7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n;
+assign soc_a7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n;
+assign soc_a7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke;
+assign soc_a7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt;
+assign soc_a7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n;
+assign soc_a7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n;
+assign soc_a7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata;
+assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en;
+assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask;
+assign soc_a7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en;
+assign soc_litedramcore_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
+assign soc_litedramcore_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
+assign soc_a7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address;
+assign soc_a7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank;
+assign soc_a7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n;
+assign soc_a7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n;
+assign soc_a7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n;
+assign soc_a7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n;
+assign soc_a7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke;
+assign soc_a7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt;
+assign soc_a7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n;
+assign soc_a7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n;
+assign soc_a7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata;
+assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en;
+assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask;
+assign soc_a7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en;
+assign soc_litedramcore_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
+assign soc_litedramcore_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
+assign soc_a7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address;
+assign soc_a7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank;
+assign soc_a7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n;
+assign soc_a7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n;
+assign soc_a7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n;
+assign soc_a7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n;
+assign soc_a7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke;
+assign soc_a7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt;
+assign soc_a7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n;
+assign soc_a7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n;
+assign soc_a7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata;
+assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en;
+assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask;
+assign soc_a7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en;
+assign soc_litedramcore_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
+assign soc_litedramcore_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
+assign soc_a7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address;
+assign soc_a7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank;
+assign soc_a7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n;
+assign soc_a7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n;
+assign soc_a7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n;
+assign soc_a7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n;
+assign soc_a7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke;
+assign soc_a7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt;
+assign soc_a7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n;
+assign soc_a7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n;
+assign soc_a7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata;
+assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en;
+assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask;
+assign soc_a7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en;
+assign soc_litedramcore_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
+assign soc_litedramcore_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
+assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address;
+assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank;
+assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n;
+assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n;
+assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n;
+assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n;
+assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke;
+assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt;
+assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n;
+assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n;
+assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata;
+assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en;
+assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask;
+assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en;
+assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata;
+assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid;
+assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address;
+assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank;
+assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n;
+assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n;
+assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n;
+assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n;
+assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke;
+assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt;
+assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n;
+assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n;
+assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata;
+assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en;
+assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask;
+assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en;
+assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata;
+assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid;
+assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address;
+assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank;
+assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n;
+assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n;
+assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n;
+assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n;
+assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke;
+assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt;
+assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n;
+assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n;
+assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata;
+assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en;
+assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask;
+assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en;
+assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata;
+assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid;
+assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address;
+assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank;
+assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n;
+assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n;
+assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n;
+assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n;
+assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke;
+assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt;
+assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n;
+assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n;
+assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata;
+assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en;
+assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask;
+assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en;
+assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata;
+assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid;
// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ soc_litedramcore_master_p2_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
end else begin
- litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
+ soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
dummy_d_26 = dummy_s;
reg dummy_d_27;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ soc_litedramcore_master_p2_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
end else begin
+ soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n;
end
// synthesis translate_off
dummy_d_27 = dummy_s;
reg dummy_d_28;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ soc_litedramcore_master_p2_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
end else begin
- litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
+ soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata;
end
// synthesis translate_off
dummy_d_28 = dummy_s;
reg dummy_d_29;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ soc_litedramcore_inti_p3_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
+ soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_29 = dummy_s;
reg dummy_d_30;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ soc_litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
end else begin
- litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
+ soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en;
end
// synthesis translate_off
dummy_d_30 = dummy_s;
reg dummy_d_31;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ soc_litedramcore_inti_p3_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
+ soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
dummy_d_31 = dummy_s;
reg dummy_d_32;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
end else begin
- litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
+ soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask;
end
// synthesis translate_off
dummy_d_32 = dummy_s;
reg dummy_d_33;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p2_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
end else begin
- litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
+ soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
dummy_d_33 = dummy_s;
reg dummy_d_34;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ soc_litedramcore_master_p3_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
+ soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address;
end
// synthesis translate_off
dummy_d_34 = dummy_s;
reg dummy_d_35;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p3_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
end else begin
- litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank;
end
// synthesis translate_off
dummy_d_35 = dummy_s;
reg dummy_d_36;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ soc_litedramcore_master_p3_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
+ soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
dummy_d_36 = dummy_s;
reg dummy_d_37;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ soc_litedramcore_master_p3_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
+ soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
dummy_d_37 = dummy_s;
reg dummy_d_38;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_address <= 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ soc_litedramcore_master_p3_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
end else begin
- litedramcore_master_p3_address <= litedramcore_inti_p3_address;
+ soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n;
end
// synthesis translate_off
dummy_d_38 = dummy_s;
reg dummy_d_39;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ soc_litedramcore_slave_p3_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
end else begin
- litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
end
// synthesis translate_off
dummy_d_39 = dummy_s;
reg dummy_d_40;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ soc_litedramcore_master_p3_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
end else begin
- litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
+ soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n;
end
// synthesis translate_off
dummy_d_40 = dummy_s;
reg dummy_d_41;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
end else begin
- litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
dummy_d_41 = dummy_s;
reg dummy_d_42;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ soc_litedramcore_master_p3_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
end else begin
- litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
+ soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke;
end
// synthesis translate_off
dummy_d_42 = dummy_s;
reg dummy_d_43;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ soc_litedramcore_master_p3_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
end else begin
+ soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt;
end
// synthesis translate_off
dummy_d_43 = dummy_s;
reg dummy_d_44;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ soc_litedramcore_master_p3_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
end else begin
- litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
+ soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n;
end
// synthesis translate_off
dummy_d_44 = dummy_s;
reg dummy_d_45;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ soc_litedramcore_master_p3_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
end else begin
+ soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n;
end
// synthesis translate_off
dummy_d_45 = dummy_s;
reg dummy_d_46;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ soc_litedramcore_master_p3_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
end else begin
- litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
+ soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata;
end
// synthesis translate_off
dummy_d_46 = dummy_s;
reg dummy_d_47;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ soc_litedramcore_inti_p0_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
+ soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata;
end
// synthesis translate_off
dummy_d_47 = dummy_s;
reg dummy_d_48;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ soc_litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
end else begin
- litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
+ soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en;
end
// synthesis translate_off
dummy_d_48 = dummy_s;
reg dummy_d_49;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ soc_litedramcore_inti_p0_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
+ soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
end
// synthesis translate_off
dummy_d_49 = dummy_s;
reg dummy_d_50;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
end else begin
- litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
+ soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask;
end
// synthesis translate_off
dummy_d_50 = dummy_s;
reg dummy_d_51;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p3_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
end else begin
- litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
+ soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en;
end
// synthesis translate_off
dummy_d_51 = dummy_s;
reg dummy_d_52;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ soc_litedramcore_master_p0_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
+ soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_52 = dummy_s;
reg dummy_d_53;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p0_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
end else begin
- litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank;
end
// synthesis translate_off
dummy_d_53 = dummy_s;
reg dummy_d_54;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ soc_litedramcore_master_p0_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
+ soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_54 = dummy_s;
reg dummy_d_55;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ soc_litedramcore_master_p0_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
+ soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n;
end
// synthesis translate_off
dummy_d_55 = dummy_s;
reg dummy_d_56;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_address <= 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ soc_litedramcore_slave_p0_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
end else begin
- litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_56 = dummy_s;
reg dummy_d_57;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ soc_litedramcore_master_p0_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
end else begin
- litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+ soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n;
end
// synthesis translate_off
dummy_d_57 = dummy_s;
reg dummy_d_58;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
end else begin
- litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_58 = dummy_s;
reg dummy_d_59;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ soc_litedramcore_master_p0_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
end else begin
- litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+ soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n;
end
// synthesis translate_off
dummy_d_59 = dummy_s;
reg dummy_d_60;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ soc_litedramcore_master_p0_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
end else begin
+ soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke;
end
// synthesis translate_off
dummy_d_60 = dummy_s;
reg dummy_d_61;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ soc_litedramcore_master_p0_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
end else begin
- litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+ soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt;
end
// synthesis translate_off
dummy_d_61 = dummy_s;
reg dummy_d_62;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ soc_litedramcore_master_p0_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
end else begin
- litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+ soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n;
end
// synthesis translate_off
dummy_d_62 = dummy_s;
reg dummy_d_63;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ soc_litedramcore_master_p0_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
end else begin
+ soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n;
end
// synthesis translate_off
dummy_d_63 = dummy_s;
reg dummy_d_64;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ soc_litedramcore_master_p0_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
end else begin
- litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+ soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata;
end
// synthesis translate_off
dummy_d_64 = dummy_s;
reg dummy_d_65;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ soc_litedramcore_inti_p1_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
+ soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata;
end
// synthesis translate_off
dummy_d_65 = dummy_s;
reg dummy_d_66;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ soc_litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
end else begin
- litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+ soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en;
end
// synthesis translate_off
dummy_d_66 = dummy_s;
reg dummy_d_67;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ soc_litedramcore_inti_p1_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
+ soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
end
// synthesis translate_off
dummy_d_67 = dummy_s;
reg dummy_d_68;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
end else begin
- litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+ soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask;
end
// synthesis translate_off
dummy_d_68 = dummy_s;
reg dummy_d_69;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_slave_p2_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
end else begin
- litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
end
// synthesis translate_off
dummy_d_69 = dummy_s;
reg dummy_d_70;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ soc_litedramcore_master_p0_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
+ soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
dummy_d_70 = dummy_s;
reg dummy_d_71;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p1_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
end else begin
- litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address;
end
// synthesis translate_off
dummy_d_71 = dummy_s;
reg dummy_d_72;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ soc_litedramcore_master_p1_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
+ soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank;
end
// synthesis translate_off
dummy_d_72 = dummy_s;
reg dummy_d_73;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
dummy_d_73 = dummy_s;
reg dummy_d_74;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_address <= 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ soc_litedramcore_master_p1_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
end else begin
- litedramcore_master_p1_address <= litedramcore_inti_p1_address;
+ soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
dummy_d_74 = dummy_s;
reg dummy_d_75;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ soc_litedramcore_master_p1_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
end else begin
- litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
+ soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
dummy_d_75 = dummy_s;
reg dummy_d_76;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ soc_litedramcore_master_p1_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
end else begin
- litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
+ soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n;
end
// synthesis translate_off
dummy_d_76 = dummy_s;
reg dummy_d_77;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ soc_litedramcore_slave_p1_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
end else begin
- litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
dummy_d_77 = dummy_s;
reg dummy_d_78;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ soc_litedramcore_master_p1_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
end else begin
- litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
+ soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n;
end
// synthesis translate_off
dummy_d_78 = dummy_s;
reg dummy_d_79;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
end else begin
end
// synthesis translate_off
reg dummy_d_80;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ soc_litedramcore_master_p1_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
end else begin
- litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
+ soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke;
end
// synthesis translate_off
dummy_d_80 = dummy_s;
reg dummy_d_81;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ soc_litedramcore_master_p1_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
end else begin
+ soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt;
end
// synthesis translate_off
dummy_d_81 = dummy_s;
reg dummy_d_82;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ soc_litedramcore_master_p1_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
end else begin
- litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
+ soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
dummy_d_82 = dummy_s;
reg dummy_d_83;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ soc_litedramcore_master_p1_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
end else begin
- litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
+ soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n;
end
// synthesis translate_off
dummy_d_83 = dummy_s;
reg dummy_d_84;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ soc_litedramcore_master_p1_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
end else begin
- litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
+ soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata;
end
// synthesis translate_off
dummy_d_84 = dummy_s;
reg dummy_d_85;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ soc_litedramcore_inti_p2_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
+ soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata;
end
// synthesis translate_off
dummy_d_85 = dummy_s;
reg dummy_d_86;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ soc_litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
end else begin
- litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
+ soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en;
end
// synthesis translate_off
dummy_d_86 = dummy_s;
reg dummy_d_87;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ soc_litedramcore_inti_p2_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
+ soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
end
// synthesis translate_off
dummy_d_87 = dummy_s;
reg dummy_d_88;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
end else begin
- litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
+ soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask;
end
// synthesis translate_off
dummy_d_88 = dummy_s;
reg dummy_d_89;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ soc_litedramcore_master_p1_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+ soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en;
end
// synthesis translate_off
dummy_d_89 = dummy_s;
reg dummy_d_90;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p2_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
end else begin
- litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address;
end
// synthesis translate_off
dummy_d_90 = dummy_s;
reg dummy_d_91;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ soc_litedramcore_master_p2_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+ soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank;
end
// synthesis translate_off
dummy_d_91 = dummy_s;
reg dummy_d_92;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ soc_litedramcore_master_p2_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
+ soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n;
end
// synthesis translate_off
dummy_d_92 = dummy_s;
reg dummy_d_93;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_address <= 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ soc_litedramcore_master_p2_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
end else begin
- litedramcore_master_p2_address <= litedramcore_inti_p2_address;
+ soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n;
end
// synthesis translate_off
dummy_d_93 = dummy_s;
reg dummy_d_94;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ soc_litedramcore_master_p2_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
end else begin
- litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
+ soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n;
end
// synthesis translate_off
dummy_d_94 = dummy_s;
reg dummy_d_95;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ soc_litedramcore_master_p2_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
end else begin
- litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
+ soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n;
end
// synthesis translate_off
dummy_d_95 = dummy_s;
reg dummy_d_96;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ soc_litedramcore_master_p2_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
end else begin
- litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
+ soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke;
end
// synthesis translate_off
dummy_d_96 = dummy_s;
reg dummy_d_97;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ soc_litedramcore_master_p2_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
end else begin
- litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
+ soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt;
end
// synthesis translate_off
dummy_d_97 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p0_cke = litedramcore_storage[1];
-assign litedramcore_inti_p1_cke = litedramcore_storage[1];
-assign litedramcore_inti_p2_cke = litedramcore_storage[1];
-assign litedramcore_inti_p3_cke = litedramcore_storage[1];
-assign litedramcore_inti_p0_odt = litedramcore_storage[2];
-assign litedramcore_inti_p1_odt = litedramcore_storage[2];
-assign litedramcore_inti_p2_odt = litedramcore_storage[2];
-assign litedramcore_inti_p3_odt = litedramcore_storage[2];
-assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
+assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n;
// synthesis translate_off
reg dummy_d_98;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
+ soc_litedramcore_inti_p0_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]);
end else begin
- litedramcore_inti_p0_we_n <= 1'd1;
+ soc_litedramcore_inti_p0_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_98 = dummy_s;
reg dummy_d_99;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
+ soc_litedramcore_inti_p0_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]);
end else begin
- litedramcore_inti_p0_cas_n <= 1'd1;
+ soc_litedramcore_inti_p0_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_99 = dummy_s;
reg dummy_d_100;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+ soc_litedramcore_inti_p0_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]);
end else begin
- litedramcore_inti_p0_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p0_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_100 = dummy_s;
reg dummy_d_101;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
+ soc_litedramcore_inti_p0_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
end else begin
- litedramcore_inti_p0_ras_n <= 1'd1;
+ soc_litedramcore_inti_p0_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_101 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
-assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
-assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage;
+assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
+assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]);
+assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]);
+assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
+assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0;
// synthesis translate_off
reg dummy_d_102;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
+ soc_litedramcore_inti_p1_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]);
end else begin
- litedramcore_inti_p1_we_n <= 1'd1;
+ soc_litedramcore_inti_p1_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_102 = dummy_s;
reg dummy_d_103;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
+ soc_litedramcore_inti_p1_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]);
end else begin
- litedramcore_inti_p1_cas_n <= 1'd1;
+ soc_litedramcore_inti_p1_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_103 = dummy_s;
reg dummy_d_104;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+ soc_litedramcore_inti_p1_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]);
end else begin
- litedramcore_inti_p1_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p1_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_104 = dummy_s;
reg dummy_d_105;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
+ soc_litedramcore_inti_p1_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
end else begin
- litedramcore_inti_p1_ras_n <= 1'd1;
+ soc_litedramcore_inti_p1_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_105 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
-assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
-assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage;
+assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
+assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]);
+assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]);
+assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
+assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0;
// synthesis translate_off
reg dummy_d_106;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_we_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
+ soc_litedramcore_inti_p2_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]);
end else begin
- litedramcore_inti_p2_we_n <= 1'd1;
+ soc_litedramcore_inti_p2_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_106 = dummy_s;
reg dummy_d_107;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cas_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
+ soc_litedramcore_inti_p2_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]);
end else begin
- litedramcore_inti_p2_cas_n <= 1'd1;
+ soc_litedramcore_inti_p2_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_107 = dummy_s;
reg dummy_d_108;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
+ soc_litedramcore_inti_p2_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]);
end else begin
- litedramcore_inti_p2_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p2_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_108 = dummy_s;
reg dummy_d_109;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_ras_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
+ soc_litedramcore_inti_p2_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
end else begin
- litedramcore_inti_p2_ras_n <= 1'd1;
+ soc_litedramcore_inti_p2_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_109 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
-assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
-assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage;
+assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
+assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]);
+assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]);
+assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
+assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0;
// synthesis translate_off
reg dummy_d_110;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_we_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
+ soc_litedramcore_inti_p3_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]);
end else begin
- litedramcore_inti_p3_we_n <= 1'd1;
+ soc_litedramcore_inti_p3_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_110 = dummy_s;
reg dummy_d_111;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cas_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
+ soc_litedramcore_inti_p3_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]);
end else begin
- litedramcore_inti_p3_cas_n <= 1'd1;
+ soc_litedramcore_inti_p3_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_111 = dummy_s;
reg dummy_d_112;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
+ soc_litedramcore_inti_p3_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]);
end else begin
- litedramcore_inti_p3_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p3_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_112 = dummy_s;
reg dummy_d_113;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_ras_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
+ soc_litedramcore_inti_p3_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
end else begin
- litedramcore_inti_p3_ras_n <= 1'd1;
+ soc_litedramcore_inti_p3_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_113 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
-assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
-assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
-assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]);
-assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
-assign litedramcore_inti_p3_wrdata_mask = 1'd0;
-assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
-assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
-assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
-assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
-assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
-assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
-assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
-assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
-assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
-assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
-assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
-assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
-assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
-assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
-assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
-assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
-assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
-assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
-assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
-assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
-assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
-assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
-assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
-assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
-assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
-assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
-assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
-assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
-assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
-assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
-assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
-assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
-assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
-assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
-assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
-assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
-assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
-assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
-assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
-assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
-assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
-assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
-assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
-assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
-assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
-assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
-assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
-assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
-assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
-assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
-assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
-assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
-assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
-assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
-assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
-assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
-assign litedramcore_timer_wait = (~litedramcore_timer_done0);
-assign litedramcore_postponer_req_i = litedramcore_timer_done0;
-assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
-assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
-assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
-assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
-assign litedramcore_timer_done0 = litedramcore_timer_done1;
-assign litedramcore_timer_count0 = litedramcore_timer_count1;
-assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
-assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
-assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
-assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
-assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage;
+assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
+assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]);
+assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]);
+assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage;
+assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0;
+assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid;
+assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready;
+assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we;
+assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr;
+assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock;
+assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready;
+assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid;
+assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid;
+assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready;
+assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we;
+assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr;
+assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock;
+assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready;
+assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid;
+assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid;
+assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready;
+assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we;
+assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr;
+assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock;
+assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready;
+assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid;
+assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid;
+assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready;
+assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we;
+assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr;
+assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock;
+assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready;
+assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid;
+assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid;
+assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready;
+assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we;
+assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr;
+assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock;
+assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready;
+assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid;
+assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid;
+assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready;
+assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we;
+assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr;
+assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock;
+assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready;
+assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid;
+assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid;
+assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready;
+assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we;
+assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr;
+assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock;
+assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready;
+assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid;
+assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid;
+assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready;
+assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we;
+assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr;
+assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock;
+assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready;
+assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid;
+assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0);
+assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0;
+assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o;
+assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0;
+assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done);
+assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0);
+assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1;
+assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1;
+assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0));
+assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0));
+assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0);
+assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
+assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
// synthesis translate_off
reg dummy_d_114;
// synthesis translate_on
always @(*) begin
- refresher_next_state <= 2'd0;
- refresher_next_state <= refresher_state;
- case (refresher_state)
+ vns_refresher_next_state <= 2'd0;
+ vns_refresher_next_state <= vns_refresher_state;
+ case (vns_refresher_state)
1'd1: begin
- if (litedramcore_cmd_ready) begin
- refresher_next_state <= 2'd2;
+ if (soc_litedramcore_cmd_ready) begin
+ vns_refresher_next_state <= 2'd2;
end
end
2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- refresher_next_state <= 2'd3;
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ vns_refresher_next_state <= 2'd3;
end else begin
- refresher_next_state <= 1'd0;
+ vns_refresher_next_state <= 1'd0;
end
end
end
2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- refresher_next_state <= 1'd0;
+ if (soc_litedramcore_zqcs_executer_done) begin
+ vns_refresher_next_state <= 1'd0;
end
end
default: begin
if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- refresher_next_state <= 1'd1;
+ if (soc_litedramcore_wants_refresh) begin
+ vns_refresher_next_state <= 1'd1;
end
end
end
reg dummy_d_115;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_zqcs_executer_start <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
end
2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ soc_litedramcore_zqcs_executer_start <= 1'd1;
end else begin
- litedramcore_cmd_valid <= 1'd0;
end
end
end
2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
end
default: begin
end
reg dummy_d_116;
// synthesis translate_on
always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_cmd_last <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
end
2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
end else begin
+ soc_litedramcore_cmd_last <= 1'd1;
end
end
end
2'd3: begin
+ if (soc_litedramcore_zqcs_executer_done) begin
+ soc_litedramcore_cmd_last <= 1'd1;
+ end
end
default: begin
end
reg dummy_d_117;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_sequencer_start0 <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
+ if (soc_litedramcore_cmd_ready) begin
+ soc_litedramcore_sequencer_start0 <= 1'd1;
+ end
end
2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
end
2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
end
default: begin
end
reg dummy_d_118;
// synthesis translate_on
always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_cmd_valid <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
+ soc_litedramcore_cmd_valid <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_cmd_valid <= 1'd1;
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ end else begin
+ soc_litedramcore_cmd_valid <= 1'd0;
+ end
+ end
end
2'd3: begin
+ soc_litedramcore_cmd_valid <= 1'd1;
+ if (soc_litedramcore_zqcs_executer_done) begin
+ soc_litedramcore_cmd_valid <= 1'd0;
+ end
end
default: begin
end
dummy_d_118 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid;
+assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid);
+assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
// synthesis translate_off
reg dummy_d_119;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_119 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
-assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
+assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
// synthesis translate_off
reg dummy_d_120;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ soc_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_120 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_121;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_121 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_122;
// synthesis translate_on
always @(*) begin
- bankmachine0_next_state <= 4'd0;
- bankmachine0_next_state <= bankmachine0_state;
- case (bankmachine0_state)
+ vns_bankmachine0_next_state <= 4'd0;
+ vns_bankmachine0_next_state <= vns_bankmachine0_state;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- bankmachine0_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- bankmachine0_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ vns_bankmachine0_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- bankmachine0_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ if (soc_litedramcore_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- bankmachine0_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
+ vns_bankmachine0_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine0_next_state <= 3'd6;
+ vns_bankmachine0_next_state <= 3'd6;
end
3'd6: begin
- bankmachine0_next_state <= 2'd3;
+ vns_bankmachine0_next_state <= 2'd3;
end
3'd7: begin
- bankmachine0_next_state <= 4'd8;
+ vns_bankmachine0_next_state <= 4'd8;
end
4'd8: begin
- bankmachine0_next_state <= 1'd0;
+ vns_bankmachine0_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- bankmachine0_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ vns_bankmachine0_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- bankmachine0_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
+ vns_bankmachine0_next_state <= 2'd2;
end
end else begin
- bankmachine0_next_state <= 1'd1;
+ vns_bankmachine0_next_state <= 1'd1;
end
end else begin
- bankmachine0_next_state <= 2'd3;
+ vns_bankmachine0_next_state <= 2'd3;
end
end
end
reg dummy_d_123;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
+ soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_124;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_125;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_row_open <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_126;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_row_close <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_127;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_128;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
reg dummy_d_129;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_130;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_131;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_132;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_133;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
end else begin
end
end else begin
reg dummy_d_134;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_135;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
end
end else begin
end
dummy_d_135 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid;
+assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid);
+assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
// synthesis translate_off
reg dummy_d_136;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_136 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
-assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
+assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
// synthesis translate_off
reg dummy_d_137;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ soc_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_137 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_138;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_138 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_139;
// synthesis translate_on
always @(*) begin
- bankmachine1_next_state <= 4'd0;
- bankmachine1_next_state <= bankmachine1_state;
- case (bankmachine1_state)
+ vns_bankmachine1_next_state <= 4'd0;
+ vns_bankmachine1_next_state <= vns_bankmachine1_state;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- bankmachine1_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- bankmachine1_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ vns_bankmachine1_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- bankmachine1_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ if (soc_litedramcore_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- bankmachine1_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
+ vns_bankmachine1_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine1_next_state <= 3'd6;
+ vns_bankmachine1_next_state <= 3'd6;
end
3'd6: begin
- bankmachine1_next_state <= 2'd3;
+ vns_bankmachine1_next_state <= 2'd3;
end
3'd7: begin
- bankmachine1_next_state <= 4'd8;
+ vns_bankmachine1_next_state <= 4'd8;
end
4'd8: begin
- bankmachine1_next_state <= 1'd0;
+ vns_bankmachine1_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- bankmachine1_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ vns_bankmachine1_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- bankmachine1_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
+ vns_bankmachine1_next_state <= 2'd2;
end
end else begin
- bankmachine1_next_state <= 1'd1;
+ vns_bankmachine1_next_state <= 1'd1;
end
end else begin
- bankmachine1_next_state <= 2'd3;
+ vns_bankmachine1_next_state <= 2'd3;
end
end
end
reg dummy_d_140;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
+ soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_141;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_142;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_row_open <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_143;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_row_close <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_144;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_145;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
reg dummy_d_146;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_147;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_148;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_149;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_150;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
end else begin
end
end else begin
reg dummy_d_151;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_152;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
end
end else begin
end
dummy_d_152 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid;
+assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
+assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
// synthesis translate_off
reg dummy_d_153;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_153 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
-assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
+assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
// synthesis translate_off
reg dummy_d_154;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ soc_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_154 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_155;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_155 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_156;
// synthesis translate_on
always @(*) begin
- bankmachine2_next_state <= 4'd0;
- bankmachine2_next_state <= bankmachine2_state;
- case (bankmachine2_state)
+ vns_bankmachine2_next_state <= 4'd0;
+ vns_bankmachine2_next_state <= vns_bankmachine2_state;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- bankmachine2_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- bankmachine2_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ vns_bankmachine2_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- bankmachine2_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ if (soc_litedramcore_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- bankmachine2_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
+ vns_bankmachine2_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine2_next_state <= 3'd6;
+ vns_bankmachine2_next_state <= 3'd6;
end
3'd6: begin
- bankmachine2_next_state <= 2'd3;
+ vns_bankmachine2_next_state <= 2'd3;
end
3'd7: begin
- bankmachine2_next_state <= 4'd8;
+ vns_bankmachine2_next_state <= 4'd8;
end
4'd8: begin
- bankmachine2_next_state <= 1'd0;
+ vns_bankmachine2_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- bankmachine2_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ vns_bankmachine2_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- bankmachine2_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
+ vns_bankmachine2_next_state <= 2'd2;
end
end else begin
- bankmachine2_next_state <= 1'd1;
+ vns_bankmachine2_next_state <= 1'd1;
end
end else begin
- bankmachine2_next_state <= 2'd3;
+ vns_bankmachine2_next_state <= 2'd3;
end
end
end
reg dummy_d_157;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
+ soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_158;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_159;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_row_open <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_160;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_row_close <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_161;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_162;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_163;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_164;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_165;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_166;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_167;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
end else begin
end
end else begin
reg dummy_d_168;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_169;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
end
end else begin
end
dummy_d_169 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid;
+assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid);
+assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
// synthesis translate_off
reg dummy_d_170;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_170 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
-assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
+assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
// synthesis translate_off
reg dummy_d_171;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ soc_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_171 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_172;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_172 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_173;
// synthesis translate_on
always @(*) begin
- bankmachine3_next_state <= 4'd0;
- bankmachine3_next_state <= bankmachine3_state;
- case (bankmachine3_state)
+ vns_bankmachine3_next_state <= 4'd0;
+ vns_bankmachine3_next_state <= vns_bankmachine3_state;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- bankmachine3_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- bankmachine3_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ vns_bankmachine3_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- bankmachine3_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ if (soc_litedramcore_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- bankmachine3_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
+ vns_bankmachine3_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine3_next_state <= 3'd6;
+ vns_bankmachine3_next_state <= 3'd6;
end
3'd6: begin
- bankmachine3_next_state <= 2'd3;
+ vns_bankmachine3_next_state <= 2'd3;
end
3'd7: begin
- bankmachine3_next_state <= 4'd8;
+ vns_bankmachine3_next_state <= 4'd8;
end
4'd8: begin
- bankmachine3_next_state <= 1'd0;
+ vns_bankmachine3_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- bankmachine3_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ vns_bankmachine3_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- bankmachine3_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
+ vns_bankmachine3_next_state <= 2'd2;
end
end else begin
- bankmachine3_next_state <= 1'd1;
+ vns_bankmachine3_next_state <= 1'd1;
end
end else begin
- bankmachine3_next_state <= 2'd3;
+ vns_bankmachine3_next_state <= 2'd3;
end
end
end
reg dummy_d_174;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
+ soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_175;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_176;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_row_open <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_177;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_row_close <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_178;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_179;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
reg dummy_d_180;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_181;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_182;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_183;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_184;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
end else begin
end
end else begin
reg dummy_d_185;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_186;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
end
end else begin
end
dummy_d_186 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid;
+assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
+assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
// synthesis translate_off
reg dummy_d_187;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_187 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
-assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
+assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
// synthesis translate_off
reg dummy_d_188;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ soc_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_188 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_189;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_189 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_190;
// synthesis translate_on
always @(*) begin
- bankmachine4_next_state <= 4'd0;
- bankmachine4_next_state <= bankmachine4_state;
- case (bankmachine4_state)
+ vns_bankmachine4_next_state <= 4'd0;
+ vns_bankmachine4_next_state <= vns_bankmachine4_state;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- bankmachine4_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- bankmachine4_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ vns_bankmachine4_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- bankmachine4_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ if (soc_litedramcore_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- bankmachine4_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
+ vns_bankmachine4_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine4_next_state <= 3'd6;
+ vns_bankmachine4_next_state <= 3'd6;
end
3'd6: begin
- bankmachine4_next_state <= 2'd3;
+ vns_bankmachine4_next_state <= 2'd3;
end
3'd7: begin
- bankmachine4_next_state <= 4'd8;
+ vns_bankmachine4_next_state <= 4'd8;
end
4'd8: begin
- bankmachine4_next_state <= 1'd0;
+ vns_bankmachine4_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- bankmachine4_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ vns_bankmachine4_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- bankmachine4_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
+ vns_bankmachine4_next_state <= 2'd2;
end
end else begin
- bankmachine4_next_state <= 1'd1;
+ vns_bankmachine4_next_state <= 1'd1;
end
end else begin
- bankmachine4_next_state <= 2'd3;
+ vns_bankmachine4_next_state <= 2'd3;
end
end
end
reg dummy_d_191;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
+ soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_192;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_193;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_row_open <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_194;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_row_close <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_195;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_196;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
reg dummy_d_197;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_198;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
reg dummy_d_199;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_200;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_201;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
end else begin
end
end else begin
reg dummy_d_202;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_203;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
end
end else begin
end
dummy_d_203 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid;
+assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid);
+assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
// synthesis translate_off
reg dummy_d_204;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_204 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
-assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
+assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
// synthesis translate_off
reg dummy_d_205;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ soc_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_205 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_206;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_206 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_207;
// synthesis translate_on
always @(*) begin
- bankmachine5_next_state <= 4'd0;
- bankmachine5_next_state <= bankmachine5_state;
- case (bankmachine5_state)
+ vns_bankmachine5_next_state <= 4'd0;
+ vns_bankmachine5_next_state <= vns_bankmachine5_state;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- bankmachine5_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- bankmachine5_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ vns_bankmachine5_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- bankmachine5_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ if (soc_litedramcore_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- bankmachine5_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
+ vns_bankmachine5_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine5_next_state <= 3'd6;
+ vns_bankmachine5_next_state <= 3'd6;
end
3'd6: begin
- bankmachine5_next_state <= 2'd3;
+ vns_bankmachine5_next_state <= 2'd3;
end
3'd7: begin
- bankmachine5_next_state <= 4'd8;
+ vns_bankmachine5_next_state <= 4'd8;
end
4'd8: begin
- bankmachine5_next_state <= 1'd0;
+ vns_bankmachine5_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- bankmachine5_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ vns_bankmachine5_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- bankmachine5_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
+ vns_bankmachine5_next_state <= 2'd2;
end
end else begin
- bankmachine5_next_state <= 1'd1;
+ vns_bankmachine5_next_state <= 1'd1;
end
end else begin
- bankmachine5_next_state <= 2'd3;
+ vns_bankmachine5_next_state <= 2'd3;
end
end
end
reg dummy_d_208;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
+ soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_209;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_210;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_row_open <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_row_open <= 1'd1;
+ end
end
3'd4: begin
end
end
4'd8: begin
end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
+ default: begin
end
endcase
// synthesis translate_off
reg dummy_d_211;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_row_close <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_212;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_213;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
reg dummy_d_214;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_215;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_216;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_217;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
end else begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_218;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_219;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_220;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
end
end else begin
end
dummy_d_220 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid;
+assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
+assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
// synthesis translate_off
reg dummy_d_221;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_221 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
-assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
+assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
// synthesis translate_off
reg dummy_d_222;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ soc_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_222 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_223;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_223 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_224;
// synthesis translate_on
always @(*) begin
- bankmachine6_next_state <= 4'd0;
- bankmachine6_next_state <= bankmachine6_state;
- case (bankmachine6_state)
+ vns_bankmachine6_next_state <= 4'd0;
+ vns_bankmachine6_next_state <= vns_bankmachine6_state;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- bankmachine6_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- bankmachine6_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ vns_bankmachine6_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- bankmachine6_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ if (soc_litedramcore_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- bankmachine6_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
+ vns_bankmachine6_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine6_next_state <= 3'd6;
+ vns_bankmachine6_next_state <= 3'd6;
end
3'd6: begin
- bankmachine6_next_state <= 2'd3;
+ vns_bankmachine6_next_state <= 2'd3;
end
3'd7: begin
- bankmachine6_next_state <= 4'd8;
+ vns_bankmachine6_next_state <= 4'd8;
end
4'd8: begin
- bankmachine6_next_state <= 1'd0;
+ vns_bankmachine6_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- bankmachine6_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ vns_bankmachine6_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- bankmachine6_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
+ vns_bankmachine6_next_state <= 2'd2;
end
end else begin
- bankmachine6_next_state <= 1'd1;
+ vns_bankmachine6_next_state <= 1'd1;
end
end else begin
- bankmachine6_next_state <= 2'd3;
+ vns_bankmachine6_next_state <= 2'd3;
end
end
end
reg dummy_d_225;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
+ soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_226;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_227;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_row_open <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_228;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_row_close <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_229;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_230;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_231;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_232;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_233;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_234;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_235;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
end else begin
end
end else begin
reg dummy_d_236;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_237;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
end
end else begin
end
dummy_d_237 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
-assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid;
+assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid);
+assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
// synthesis translate_off
reg dummy_d_238;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+ soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_238 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
-assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
+assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
// synthesis translate_off
reg dummy_d_239;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ soc_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_239 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_240;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_240 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_241;
// synthesis translate_on
always @(*) begin
- bankmachine7_next_state <= 4'd0;
- bankmachine7_next_state <= bankmachine7_state;
- case (bankmachine7_state)
+ vns_bankmachine7_next_state <= 4'd0;
+ vns_bankmachine7_next_state <= vns_bankmachine7_state;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- bankmachine7_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- bankmachine7_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ vns_bankmachine7_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- bankmachine7_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ if (soc_litedramcore_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- bankmachine7_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
+ vns_bankmachine7_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine7_next_state <= 3'd6;
+ vns_bankmachine7_next_state <= 3'd6;
end
3'd6: begin
- bankmachine7_next_state <= 2'd3;
+ vns_bankmachine7_next_state <= 2'd3;
end
3'd7: begin
- bankmachine7_next_state <= 4'd8;
+ vns_bankmachine7_next_state <= 4'd8;
end
4'd8: begin
- bankmachine7_next_state <= 1'd0;
+ vns_bankmachine7_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- bankmachine7_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ vns_bankmachine7_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- bankmachine7_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
+ vns_bankmachine7_next_state <= 2'd2;
end
end else begin
- bankmachine7_next_state <= 1'd1;
+ vns_bankmachine7_next_state <= 1'd1;
end
end else begin
- bankmachine7_next_state <= 2'd3;
+ vns_bankmachine7_next_state <= 2'd3;
end
end
end
reg dummy_d_242;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
+ soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_243;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_244;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_row_open <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_245;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_row_close <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_246;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_247;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
reg dummy_d_248;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_249;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_250;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_251;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_252;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
end else begin
end
end else begin
reg dummy_d_253;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_254;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
end
end else begin
end
dummy_d_254 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
-assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
-assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
-assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
-assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
-assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
-assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
-assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
-assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
-assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
+assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
+assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready);
+assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read));
+assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready;
+assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read));
+assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write));
+assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0);
+assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0);
+assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt);
+assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata};
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
// synthesis translate_off
reg dummy_d_255;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids <= 8'd0;
+ soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
// synthesis translate_off
dummy_d_255 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids;
+assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
+assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
+assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
// synthesis translate_off
reg dummy_d_256;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
end
// synthesis translate_off
dummy_d_256 = dummy_s;
reg dummy_d_257;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
end
// synthesis translate_off
dummy_d_257 = dummy_s;
reg dummy_d_258;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
end
// synthesis translate_off
dummy_d_258 = dummy_s;
reg dummy_d_259;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_259 = dummy_s;
reg dummy_d_260;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_260 = dummy_s;
reg dummy_d_261;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_261 = dummy_s;
reg dummy_d_262;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_262 = dummy_s;
reg dummy_d_263;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_263 = dummy_s;
reg dummy_d_264;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_264 = dummy_s;
reg dummy_d_265;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_265 = dummy_s;
reg dummy_d_266;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_266 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid));
// synthesis translate_off
reg dummy_d_267;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids <= 8'd0;
+ soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
// synthesis translate_off
dummy_d_267 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids;
+assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6;
+assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
+assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
+assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
+assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
+assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
// synthesis translate_off
reg dummy_d_268;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
end
// synthesis translate_off
dummy_d_268 = dummy_s;
reg dummy_d_269;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
end
// synthesis translate_off
dummy_d_269 = dummy_s;
reg dummy_d_270;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ soc_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5;
end
// synthesis translate_off
dummy_d_270 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
-assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
-assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
-assign litedramcore_dfi_p2_reset_n = 1'd1;
-assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
-assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
-assign litedramcore_dfi_p3_reset_n = 1'd1;
-assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
-assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
-assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid));
+assign soc_litedramcore_dfi_p0_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}};
+assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}};
+assign soc_litedramcore_dfi_p1_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}};
+assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}};
+assign soc_litedramcore_dfi_p2_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}};
+assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}};
+assign soc_litedramcore_dfi_p3_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}};
+assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}};
+assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
// synthesis translate_off
reg dummy_d_271;
// synthesis translate_on
always @(*) begin
- multiplexer_next_state <= 4'd0;
- multiplexer_next_state <= multiplexer_state;
- case (multiplexer_state)
+ vns_multiplexer_next_state <= 4'd0;
+ vns_multiplexer_next_state <= vns_multiplexer_state;
+ case (vns_multiplexer_state)
1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- multiplexer_next_state <= 2'd3;
+ if (soc_litedramcore_read_available) begin
+ if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
+ vns_multiplexer_next_state <= 2'd3;
end
end
- if (litedramcore_go_to_refresh) begin
- multiplexer_next_state <= 2'd2;
+ if (soc_litedramcore_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
end
end
2'd2: begin
- if (litedramcore_cmd_last) begin
- multiplexer_next_state <= 1'd0;
+ if (soc_litedramcore_cmd_last) begin
+ vns_multiplexer_next_state <= 1'd0;
end
end
2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- multiplexer_next_state <= 1'd0;
+ if (soc_litedramcore_twtrcon_ready) begin
+ vns_multiplexer_next_state <= 1'd0;
end
end
3'd4: begin
- multiplexer_next_state <= 3'd5;
+ vns_multiplexer_next_state <= 3'd5;
end
3'd5: begin
- multiplexer_next_state <= 3'd6;
+ vns_multiplexer_next_state <= 3'd6;
end
3'd6: begin
- multiplexer_next_state <= 3'd7;
+ vns_multiplexer_next_state <= 3'd7;
end
3'd7: begin
- multiplexer_next_state <= 4'd8;
+ vns_multiplexer_next_state <= 4'd8;
end
4'd8: begin
- multiplexer_next_state <= 4'd9;
+ vns_multiplexer_next_state <= 4'd9;
end
4'd9: begin
- multiplexer_next_state <= 4'd10;
+ vns_multiplexer_next_state <= 4'd10;
end
4'd10: begin
- multiplexer_next_state <= 1'd1;
+ vns_multiplexer_next_state <= 1'd1;
end
default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- multiplexer_next_state <= 3'd4;
+ if (soc_litedramcore_write_available) begin
+ if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
+ vns_multiplexer_next_state <= 3'd4;
end
end
- if (litedramcore_go_to_refresh) begin
- multiplexer_next_state <= 2'd2;
+ if (soc_litedramcore_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
end
end
endcase
reg dummy_d_272;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_req_want_reads <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel2 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel2 <= 2'd2;
+ soc_litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_273;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_req_want_writes <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
+ soc_litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
end
endcase
// synthesis translate_off
reg dummy_d_274;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel3 <= 2'd2;
+ if (1'd0) begin
+ soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+ end else begin
+ soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel3 <= 1'd0;
+ if (1'd0) begin
+ soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+ end else begin
+ soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+ end
end
endcase
// synthesis translate_off
reg dummy_d_275;
// synthesis translate_on
always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_en1 <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
+ soc_litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_en0 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_276;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel3 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
+ soc_litedramcore_steerer_sel3 <= 2'd2;
end
2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
+ soc_litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_277;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel0 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
+ soc_litedramcore_steerer_sel0 <= 1'd0;
end
2'd2: begin
+ soc_litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
+ soc_litedramcore_steerer_sel0 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_278;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel1 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
+ soc_litedramcore_steerer_sel1 <= 1'd0;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
+ soc_litedramcore_steerer_sel1 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_279;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel2 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
+ soc_litedramcore_steerer_sel2 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ soc_litedramcore_steerer_sel2 <= 2'd2;
end
endcase
// synthesis translate_off
reg dummy_d_280;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
end
end
2'd2: begin
end
default: begin
if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
end
end
endcase
reg dummy_d_281;
// synthesis translate_on
always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_en0 <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ soc_litedramcore_en0 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_282;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
end
2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
+ soc_litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel0 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_283;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel1 <= 1'd1;
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+ end
end
endcase
// synthesis translate_off
dummy_d_283 = dummy_s;
// synthesis translate_on
end
-assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = new_master_wdata_ready2;
-assign user_port_rdata_valid = new_master_rdata_valid8;
+assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
+assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12;
+assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13;
+assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14;
+assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
+assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15;
+assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16;
+assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17;
+assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
+assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18;
+assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19;
+assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20;
+assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
+assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21;
+assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22;
+assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23;
+assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
+assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24;
+assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25;
+assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26;
+assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
+assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27;
+assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28;
+assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29;
+assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
+assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30;
+assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31;
+assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32;
+assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
+assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33;
+assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34;
+assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35;
+assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
+assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2;
+assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8;
// synthesis translate_off
reg dummy_d_284;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
- case ({new_master_wdata_ready2})
+ soc_litedramcore_interface_wdata <= 128'd0;
+ case ({vns_new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
end
default: begin
- litedramcore_interface_wdata <= 1'd0;
+ soc_litedramcore_interface_wdata <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_285;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
- case ({new_master_wdata_ready2})
+ soc_litedramcore_interface_wdata_we <= 16'd0;
+ case ({vns_new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
end
default: begin
- litedramcore_interface_wdata_we <= 1'd0;
+ soc_litedramcore_interface_wdata_we <= 1'd0;
end
endcase
// synthesis translate_off
dummy_d_285 = dummy_s;
// synthesis translate_on
end
-assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign roundrobin0_grant = 1'd0;
-assign roundrobin1_grant = 1'd0;
-assign roundrobin2_grant = 1'd0;
-assign roundrobin3_grant = 1'd0;
-assign roundrobin4_grant = 1'd0;
-assign roundrobin5_grant = 1'd0;
-assign roundrobin6_grant = 1'd0;
-assign roundrobin7_grant = 1'd0;
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0));
-assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0));
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1));
-assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1));
-assign csrbank0_init_done0_w = init_done_storage;
-assign csrbank0_init_error0_w = init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
-assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
-assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0));
-assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0));
-assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
-assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1));
-assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1));
-assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2));
-assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2));
-assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3));
-assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3));
-assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4));
-assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4));
-assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
-assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5));
-assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5));
-assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6));
-assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6));
-assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7));
-assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7));
-assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9));
-assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9));
-assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
-assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
-assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1);
-assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
-assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0));
-assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0));
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1));
-assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1));
-assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2));
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3));
-assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3));
-assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4));
-assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4));
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5));
-assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5));
-assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6));
-assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6));
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7));
-assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7));
-assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8));
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9));
-assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9));
-assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10));
-assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10));
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11));
-assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11));
-assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12));
-assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12));
-assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13));
-assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13));
-assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14));
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15));
-assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15));
-assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16));
-assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16));
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17));
-assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17));
-assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18));
-assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18));
-assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19));
-assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19));
-assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20));
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21));
-assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21));
-assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22));
-assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22));
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23));
-assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23));
-assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24));
-assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24));
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
-assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we;
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
-assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we;
-assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
-assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
-assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we;
-assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
-assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
-assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
-assign adr = litedramcore_adr;
-assign we = litedramcore_we;
-assign dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = dat_r;
-assign interface0_bank_bus_adr = adr;
-assign interface1_bank_bus_adr = adr;
-assign interface2_bank_bus_adr = adr;
-assign interface0_bank_bus_we = we;
-assign interface1_bank_bus_we = we;
-assign interface2_bank_bus_we = we;
-assign interface0_bank_bus_dat_w = dat_w;
-assign interface1_bank_bus_dat_w = dat_w;
-assign interface2_bank_bus_dat_w = dat_w;
-assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata;
+assign vns_roundrobin0_grant = 1'd0;
+assign vns_roundrobin1_grant = 1'd0;
+assign vns_roundrobin2_grant = 1'd0;
+assign vns_roundrobin3_grant = 1'd0;
+assign vns_roundrobin4_grant = 1'd0;
+assign vns_roundrobin5_grant = 1'd0;
+assign vns_roundrobin6_grant = 1'd0;
+assign vns_roundrobin7_grant = 1'd0;
+assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr;
+assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
+assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r;
+assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel;
+assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc;
+assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb;
+assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack;
+assign soc_litedramcore_wishbone_we = soc_wb_bus_we;
+assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti;
+assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte;
+assign soc_wb_bus_err = soc_litedramcore_wishbone_err;
+assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2);
+assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0];
+assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0];
+assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank0_init_done0_w = soc_init_done_storage;
+assign vns_csrbank0_init_error0_w = soc_init_error_storage;
+assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0);
+assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0];
+assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0];
+assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1));
+assign soc_a7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4));
+assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[1:0];
+assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5));
+assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9));
+assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9));
+assign vns_csrbank1_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign vns_csrbank1_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage;
+assign vns_csrbank1_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
+assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1);
+assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0];
+assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd1));
+assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd1));
+assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd2));
+assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd2));
+assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[13:0];
+assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank2_dfii_pi0_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi0_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank2_dfii_pi0_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd7));
+assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd7));
+assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd8));
+assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd8));
+assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[13:0];
+assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank2_dfii_pi1_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi1_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank2_dfii_pi1_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd13));
+assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd13));
+assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd14));
+assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd14));
+assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[13:0];
+assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd15));
+assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd15));
+assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd17));
+assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd17));
+assign vns_csrbank2_dfii_pi2_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi2_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd18));
+assign vns_csrbank2_dfii_pi2_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd18));
+assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd19));
+assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd19));
+assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd20));
+assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd20));
+assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[13:0];
+assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd21));
+assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd21));
+assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd22));
+assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd22));
+assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd23));
+assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd23));
+assign vns_csrbank2_dfii_pi3_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi3_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd24));
+assign vns_csrbank2_dfii_pi3_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd24));
+assign soc_litedramcore_sel = soc_litedramcore_storage[0];
+assign soc_litedramcore_cke = soc_litedramcore_storage[1];
+assign soc_litedramcore_odt = soc_litedramcore_storage[2];
+assign soc_litedramcore_reset_n = soc_litedramcore_storage[3];
+assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0];
+assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0];
+assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0];
+assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_status[31:0];
+assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata_we;
+assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0];
+assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0];
+assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_status[31:0];
+assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata_we;
+assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0];
+assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0];
+assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_status[31:0];
+assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata_we;
+assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0];
+assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0];
+assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_status[31:0];
+assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata_we;
+assign vns_adr = soc_litedramcore_adr;
+assign vns_we = soc_litedramcore_we;
+assign vns_dat_w = soc_litedramcore_dat_w;
+assign soc_litedramcore_dat_r = vns_dat_r;
+assign vns_interface0_bank_bus_adr = vns_adr;
+assign vns_interface1_bank_bus_adr = vns_adr;
+assign vns_interface2_bank_bus_adr = vns_adr;
+assign vns_interface0_bank_bus_we = vns_we;
+assign vns_interface1_bank_bus_we = vns_we;
+assign vns_interface2_bank_bus_we = vns_we;
+assign vns_interface0_bank_bus_dat_w = vns_dat_w;
+assign vns_interface1_bank_bus_dat_w = vns_dat_w;
+assign vns_interface2_bank_bus_dat_w = vns_dat_w;
+assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r);
// synthesis translate_off
reg dummy_d_286;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed0 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0];
end
1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1];
end
2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2];
end
2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3];
end
3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4];
end
3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5];
end
3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6];
end
default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7];
end
endcase
// synthesis translate_off
reg dummy_d_287;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed1 <= 14'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed1 <= 14'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_288;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed2 <= 3'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
// synthesis translate_off
reg dummy_d_289;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
// synthesis translate_off
reg dummy_d_290;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
// synthesis translate_off
reg dummy_d_291;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
// synthesis translate_off
reg dummy_d_292;
// synthesis translate_on
always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_t_array_muxed0 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
// synthesis translate_off
reg dummy_d_293;
// synthesis translate_on
always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_t_array_muxed1 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
// synthesis translate_off
reg dummy_d_294;
// synthesis translate_on
always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_t_array_muxed2 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_295;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed6 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0];
end
1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1];
end
2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2];
end
2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3];
end
3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4];
end
3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5];
end
3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6];
end
default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7];
end
endcase
// synthesis translate_off
reg dummy_d_296;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed7 <= 14'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed7 <= 14'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_297;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed8 <= 3'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
// synthesis translate_off
reg dummy_d_298;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed9 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
// synthesis translate_off
reg dummy_d_299;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed10 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
// synthesis translate_off
reg dummy_d_300;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed11 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
// synthesis translate_off
reg dummy_d_301;
// synthesis translate_on
always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_t_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
// synthesis translate_off
reg dummy_d_302;
// synthesis translate_on
always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_t_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
// synthesis translate_off
reg dummy_d_303;
// synthesis translate_on
always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_t_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_304;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed12 <= 21'd0;
- case (roundrobin0_grant)
+ vns_rhs_array_muxed12 <= 21'd0;
+ case (vns_roundrobin0_grant)
default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_305;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (roundrobin0_grant)
+ vns_rhs_array_muxed13 <= 1'd0;
+ case (vns_roundrobin0_grant)
default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_306;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (roundrobin0_grant)
+ vns_rhs_array_muxed14 <= 1'd0;
+ case (vns_roundrobin0_grant)
default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_307;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed15 <= 21'd0;
- case (roundrobin1_grant)
+ vns_rhs_array_muxed15 <= 21'd0;
+ case (vns_roundrobin1_grant)
default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_308;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (roundrobin1_grant)
+ vns_rhs_array_muxed16 <= 1'd0;
+ case (vns_roundrobin1_grant)
default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_309;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (roundrobin1_grant)
+ vns_rhs_array_muxed17 <= 1'd0;
+ case (vns_roundrobin1_grant)
default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_310;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed18 <= 21'd0;
- case (roundrobin2_grant)
+ vns_rhs_array_muxed18 <= 21'd0;
+ case (vns_roundrobin2_grant)
default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_311;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (roundrobin2_grant)
+ vns_rhs_array_muxed19 <= 1'd0;
+ case (vns_roundrobin2_grant)
default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_312;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (roundrobin2_grant)
+ vns_rhs_array_muxed20 <= 1'd0;
+ case (vns_roundrobin2_grant)
default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_313;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed21 <= 21'd0;
- case (roundrobin3_grant)
+ vns_rhs_array_muxed21 <= 21'd0;
+ case (vns_roundrobin3_grant)
default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_314;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (roundrobin3_grant)
+ vns_rhs_array_muxed22 <= 1'd0;
+ case (vns_roundrobin3_grant)
default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_315;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (roundrobin3_grant)
+ vns_rhs_array_muxed23 <= 1'd0;
+ case (vns_roundrobin3_grant)
default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_316;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed24 <= 21'd0;
- case (roundrobin4_grant)
+ vns_rhs_array_muxed24 <= 21'd0;
+ case (vns_roundrobin4_grant)
default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_317;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (roundrobin4_grant)
+ vns_rhs_array_muxed25 <= 1'd0;
+ case (vns_roundrobin4_grant)
default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_318;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (roundrobin4_grant)
+ vns_rhs_array_muxed26 <= 1'd0;
+ case (vns_roundrobin4_grant)
default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_319;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed27 <= 21'd0;
- case (roundrobin5_grant)
+ vns_rhs_array_muxed27 <= 21'd0;
+ case (vns_roundrobin5_grant)
default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_320;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (roundrobin5_grant)
+ vns_rhs_array_muxed28 <= 1'd0;
+ case (vns_roundrobin5_grant)
default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_321;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (roundrobin5_grant)
+ vns_rhs_array_muxed29 <= 1'd0;
+ case (vns_roundrobin5_grant)
default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_322;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed30 <= 21'd0;
- case (roundrobin6_grant)
+ vns_rhs_array_muxed30 <= 21'd0;
+ case (vns_roundrobin6_grant)
default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_323;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (roundrobin6_grant)
+ vns_rhs_array_muxed31 <= 1'd0;
+ case (vns_roundrobin6_grant)
default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_324;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (roundrobin6_grant)
+ vns_rhs_array_muxed32 <= 1'd0;
+ case (vns_roundrobin6_grant)
default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_325;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed33 <= 21'd0;
- case (roundrobin7_grant)
+ vns_rhs_array_muxed33 <= 21'd0;
+ case (vns_roundrobin7_grant)
default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_326;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (roundrobin7_grant)
+ vns_rhs_array_muxed34 <= 1'd0;
+ case (vns_roundrobin7_grant)
default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_327;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (roundrobin7_grant)
+ vns_rhs_array_muxed35 <= 1'd0;
+ case (vns_roundrobin7_grant)
default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_328;
// synthesis translate_on
always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed0 <= 3'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_329;
// synthesis translate_on
always @(*) begin
- array_muxed1 <= 14'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed1 <= 14'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
+ vns_array_muxed1 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
+ vns_array_muxed1 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_330;
// synthesis translate_on
always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed2 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed2 <= 1'd0;
+ vns_array_muxed2 <= 1'd0;
end
1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_331;
// synthesis translate_on
always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed3 <= 1'd0;
+ vns_array_muxed3 <= 1'd0;
end
1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_332;
// synthesis translate_on
always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed4 <= 1'd0;
+ vns_array_muxed4 <= 1'd0;
end
1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_333;
// synthesis translate_on
always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed5 <= 1'd0;
+ vns_array_muxed5 <= 1'd0;
end
1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_334;
// synthesis translate_on
always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed6 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed6 <= 1'd0;
+ vns_array_muxed6 <= 1'd0;
end
1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
reg dummy_d_335;
// synthesis translate_on
always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed7 <= 3'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_336;
// synthesis translate_on
always @(*) begin
- array_muxed8 <= 14'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed8 <= 14'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
+ vns_array_muxed8 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
+ vns_array_muxed8 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_337;
// synthesis translate_on
always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed9 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed9 <= 1'd0;
+ vns_array_muxed9 <= 1'd0;
end
1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_338;
// synthesis translate_on
always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed10 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed10 <= 1'd0;
+ vns_array_muxed10 <= 1'd0;
end
1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_339;
// synthesis translate_on
always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed11 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed11 <= 1'd0;
+ vns_array_muxed11 <= 1'd0;
end
1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_340;
// synthesis translate_on
always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed12 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed12 <= 1'd0;
+ vns_array_muxed12 <= 1'd0;
end
1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_341;
// synthesis translate_on
always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed13 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed13 <= 1'd0;
+ vns_array_muxed13 <= 1'd0;
end
1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
reg dummy_d_342;
// synthesis translate_on
always @(*) begin
- array_muxed14 <= 3'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed14 <= 3'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed14 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_343;
// synthesis translate_on
always @(*) begin
- array_muxed15 <= 14'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed15 <= 14'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed15 <= litedramcore_nop_a;
+ vns_array_muxed15 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed15 <= litedramcore_cmd_payload_a;
+ vns_array_muxed15 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_344;
// synthesis translate_on
always @(*) begin
- array_muxed16 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed16 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed16 <= 1'd0;
+ vns_array_muxed16 <= 1'd0;
end
1'd1: begin
- array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_345;
// synthesis translate_on
always @(*) begin
- array_muxed17 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed17 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed17 <= 1'd0;
+ vns_array_muxed17 <= 1'd0;
end
1'd1: begin
- array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_346;
// synthesis translate_on
always @(*) begin
- array_muxed18 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed18 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed18 <= 1'd0;
+ vns_array_muxed18 <= 1'd0;
end
1'd1: begin
- array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_347;
// synthesis translate_on
always @(*) begin
- array_muxed19 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed19 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed19 <= 1'd0;
+ vns_array_muxed19 <= 1'd0;
end
1'd1: begin
- array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_348;
// synthesis translate_on
always @(*) begin
- array_muxed20 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed20 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed20 <= 1'd0;
+ vns_array_muxed20 <= 1'd0;
end
1'd1: begin
- array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
reg dummy_d_349;
// synthesis translate_on
always @(*) begin
- array_muxed21 <= 3'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed21 <= 3'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed21 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_350;
// synthesis translate_on
always @(*) begin
- array_muxed22 <= 14'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed22 <= 14'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed22 <= litedramcore_nop_a;
+ vns_array_muxed22 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed22 <= litedramcore_cmd_payload_a;
+ vns_array_muxed22 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_351;
// synthesis translate_on
always @(*) begin
- array_muxed23 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed23 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed23 <= 1'd0;
+ vns_array_muxed23 <= 1'd0;
end
1'd1: begin
- array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_352;
// synthesis translate_on
always @(*) begin
- array_muxed24 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed24 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed24 <= 1'd0;
+ vns_array_muxed24 <= 1'd0;
end
1'd1: begin
- array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_353;
// synthesis translate_on
always @(*) begin
- array_muxed25 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed25 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed25 <= 1'd0;
+ vns_array_muxed25 <= 1'd0;
end
1'd1: begin
- array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_354;
// synthesis translate_on
always @(*) begin
- array_muxed26 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed26 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed26 <= 1'd0;
+ vns_array_muxed26 <= 1'd0;
end
1'd1: begin
- array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_355;
// synthesis translate_on
always @(*) begin
- array_muxed27 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed27 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed27 <= 1'd0;
+ vns_array_muxed27 <= 1'd0;
end
1'd1: begin
- array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
dummy_d_355 = dummy_s;
// synthesis translate_on
end
-assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
-assign xilinxasyncresetsynchronizerimpl1 = ((~sys_pll_locked) | sys_pll_reset);
-assign xilinxasyncresetsynchronizerimpl2 = ((~sys_pll_locked) | sys_pll_reset);
-assign xilinxasyncresetsynchronizerimpl3 = ((~iodelay_pll_locked) | iodelay_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset);
+assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset);
+assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset);
+assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset);
always @(posedge iodelay_clk) begin
- if ((reset_counter != 1'd0)) begin
- reset_counter <= (reset_counter - 1'd1);
+ if ((soc_reset_counter != 1'd0)) begin
+ soc_reset_counter <= (soc_reset_counter - 1'd1);
end else begin
- ic_reset <= 1'd0;
+ soc_ic_reset <= 1'd0;
end
if (iodelay_rst) begin
- reset_counter <= 4'd15;
- ic_reset <= 1'd1;
+ soc_reset_counter <= 4'd15;
+ soc_ic_reset <= 1'd1;
end
end
always @(posedge sys_clk) begin
- state <= next_state;
- a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1);
- a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1);
- a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en;
- a7ddrphy_dfi_p0_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_dfi_p1_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_dfi_p2_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_dfi_p3_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_wrdata_en_last <= a7ddrphy_wrdata_en;
- a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value <= (a7ddrphy_bitslip0_value + 1'd1);
+ vns_state <= vns_next_state;
+ soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en;
+ soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip0_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip0_value <= 1'd0;
end
- a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1);
+ soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip1_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip1_value <= 1'd0;
end
- a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1);
+ soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip2_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip2_value <= 1'd0;
end
- a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1);
+ soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip3_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip3_value <= 1'd0;
end
- a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1);
+ soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip4_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip4_value <= 1'd0;
end
- a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1);
+ soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip5_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip5_value <= 1'd0;
end
- a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1);
+ soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip6_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip6_value <= 1'd0;
end
- a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1);
+ soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip7_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip7_value <= 1'd0;
end
- a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1);
+ soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip8_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip8_value <= 1'd0;
end
- a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1);
+ soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip9_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip9_value <= 1'd0;
end
- a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1);
+ soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip10_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip10_value <= 1'd0;
end
- a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1);
+ soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip11_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip11_value <= 1'd0;
end
- a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1);
+ soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip12_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip12_value <= 1'd0;
end
- a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1);
+ soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip13_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip13_value <= 1'd0;
end
- a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1);
+ soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip14_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip14_value <= 1'd0;
end
- a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1);
+ soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip15_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip15_value <= 1'd0;
end
- a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]};
- if (litedramcore_inti_p0_rddata_valid) begin
- litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
+ soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[23:8]};
+ if (soc_litedramcore_inti_p0_rddata_valid) begin
+ soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata;
end
- if (litedramcore_inti_p1_rddata_valid) begin
- litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata;
+ if (soc_litedramcore_inti_p1_rddata_valid) begin
+ soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata;
end
- if (litedramcore_inti_p2_rddata_valid) begin
- litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata;
+ if (soc_litedramcore_inti_p2_rddata_valid) begin
+ soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata;
end
- if (litedramcore_inti_p3_rddata_valid) begin
- litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata;
+ if (soc_litedramcore_inti_p3_rddata_valid) begin
+ soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata;
end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin
+ soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1);
end else begin
- litedramcore_timer_count1 <= 10'd781;
+ soc_litedramcore_timer_count1 <= 10'd781;
end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
+ soc_litedramcore_postponer_req_o <= 1'd0;
+ if (soc_litedramcore_postponer_req_i) begin
+ soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1);
+ if ((soc_litedramcore_postponer_count == 1'd0)) begin
+ soc_litedramcore_postponer_count <= 1'd0;
+ soc_litedramcore_postponer_req_o <= 1'd1;
end
end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
+ if (soc_litedramcore_sequencer_start0) begin
+ soc_litedramcore_sequencer_count <= 1'd0;
end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 6'd35)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 6'd35)) begin
- litedramcore_sequencer_counter <= 1'd0;
+ if (soc_litedramcore_sequencer_done1) begin
+ if ((soc_litedramcore_sequencer_count != 1'd0)) begin
+ soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd0;
+ if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin
+ soc_litedramcore_cmd_payload_a <= 11'd1024;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_sequencer_counter == 2'd3)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd1;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
+ soc_litedramcore_sequencer_counter <= 1'd0;
end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ if ((soc_litedramcore_sequencer_counter != 1'd0)) begin
+ soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1);
end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
+ if (soc_litedramcore_sequencer_start1) begin
+ soc_litedramcore_sequencer_counter <= 1'd1;
end
end
end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin
+ soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1);
end else begin
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
+ soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ soc_litedramcore_zqcs_executer_done <= 1'd0;
+ if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin
+ soc_litedramcore_cmd_payload_a <= 11'd1024;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
+ soc_litedramcore_zqcs_executer_counter <= 1'd0;
end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin
+ soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1);
end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
+ if (soc_litedramcore_zqcs_executer_start) begin
+ soc_litedramcore_zqcs_executer_counter <= 1'd1;
end
end
end
- refresher_state <= refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
+ vns_refresher_state <= vns_refresher_next_state;
+ if (soc_litedramcore_bankmachine0_row_close) begin
+ soc_litedramcore_bankmachine0_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine0_row_open) begin
+ soc_litedramcore_bankmachine0_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine0_twtpcon_valid) begin
+ soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine0_trccon_valid) begin
+ soc_litedramcore_bankmachine0_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin
+ soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine0_trascon_valid) begin
+ soc_litedramcore_bankmachine0_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
end
end
end
- bankmachine0_state <= bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
+ vns_bankmachine0_state <= vns_bankmachine0_next_state;
+ if (soc_litedramcore_bankmachine1_row_close) begin
+ soc_litedramcore_bankmachine1_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine1_row_open) begin
+ soc_litedramcore_bankmachine1_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine1_twtpcon_valid) begin
+ soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine1_trccon_valid) begin
+ soc_litedramcore_bankmachine1_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin
+ soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine1_trascon_valid) begin
+ soc_litedramcore_bankmachine1_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
end
end
end
- bankmachine1_state <= bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
+ vns_bankmachine1_state <= vns_bankmachine1_next_state;
+ if (soc_litedramcore_bankmachine2_row_close) begin
+ soc_litedramcore_bankmachine2_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine2_row_open) begin
+ soc_litedramcore_bankmachine2_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine2_twtpcon_valid) begin
+ soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine2_trccon_valid) begin
+ soc_litedramcore_bankmachine2_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin
+ soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine2_trascon_valid) begin
+ soc_litedramcore_bankmachine2_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
end
end
end
- bankmachine2_state <= bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
+ vns_bankmachine2_state <= vns_bankmachine2_next_state;
+ if (soc_litedramcore_bankmachine3_row_close) begin
+ soc_litedramcore_bankmachine3_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine3_row_open) begin
+ soc_litedramcore_bankmachine3_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine3_twtpcon_valid) begin
+ soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine3_trccon_valid) begin
+ soc_litedramcore_bankmachine3_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin
+ soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine3_trascon_valid) begin
+ soc_litedramcore_bankmachine3_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
end
end
end
- bankmachine3_state <= bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
+ vns_bankmachine3_state <= vns_bankmachine3_next_state;
+ if (soc_litedramcore_bankmachine4_row_close) begin
+ soc_litedramcore_bankmachine4_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine4_row_open) begin
+ soc_litedramcore_bankmachine4_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine4_twtpcon_valid) begin
+ soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine4_trccon_valid) begin
+ soc_litedramcore_bankmachine4_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin
+ soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine4_trascon_valid) begin
+ soc_litedramcore_bankmachine4_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
end
end
end
- bankmachine4_state <= bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
+ vns_bankmachine4_state <= vns_bankmachine4_next_state;
+ if (soc_litedramcore_bankmachine5_row_close) begin
+ soc_litedramcore_bankmachine5_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine5_row_open) begin
+ soc_litedramcore_bankmachine5_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine5_twtpcon_valid) begin
+ soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine5_trccon_valid) begin
+ soc_litedramcore_bankmachine5_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin
+ soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine5_trascon_valid) begin
+ soc_litedramcore_bankmachine5_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
end
end
end
- bankmachine5_state <= bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
+ vns_bankmachine5_state <= vns_bankmachine5_next_state;
+ if (soc_litedramcore_bankmachine6_row_close) begin
+ soc_litedramcore_bankmachine6_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine6_row_open) begin
+ soc_litedramcore_bankmachine6_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine6_twtpcon_valid) begin
+ soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine6_trccon_valid) begin
+ soc_litedramcore_bankmachine6_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin
+ soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine6_trascon_valid) begin
+ soc_litedramcore_bankmachine6_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
end
end
end
- bankmachine6_state <= bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
+ vns_bankmachine6_state <= vns_bankmachine6_next_state;
+ if (soc_litedramcore_bankmachine7_row_close) begin
+ soc_litedramcore_bankmachine7_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+ if (soc_litedramcore_bankmachine7_row_open) begin
+ soc_litedramcore_bankmachine7_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end
end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine7_twtpcon_valid) begin
+ soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine7_trccon_valid) begin
+ soc_litedramcore_bankmachine7_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin
+ soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine7_trascon_valid) begin
+ soc_litedramcore_bankmachine7_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
end
end
end
- bankmachine7_state <= bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
+ vns_bankmachine7_state <= vns_bankmachine7_next_state;
+ if ((~soc_litedramcore_en0)) begin
+ soc_litedramcore_time0 <= 5'd31;
end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ if ((~soc_litedramcore_max_time0)) begin
+ soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1);
end
end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
+ if ((~soc_litedramcore_en1)) begin
+ soc_litedramcore_time1 <= 4'd15;
end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ if ((~soc_litedramcore_max_time1)) begin
+ soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1);
end
end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
+ if (soc_litedramcore_choose_cmd_ce) begin
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end
end
end
end
end
1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end
end
end
end
end
2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end
end
end
end
end
2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end
end
end
end
end
3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end
end
end
end
end
3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end
end
end
end
end
3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end
end
end
end
end
3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end
end
end
end
endcase
end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
+ if (soc_litedramcore_choose_req_ce) begin
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end
end
end
end
end
1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end
end
end
end
end
2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end
end
end
end
end
2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end
end
end
end
end
3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end
end
end
end
end
3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end
end
end
end
end
3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end
end
end
end
end
3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end
end
end
end
endcase
end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= array_muxed14;
- litedramcore_dfi_p2_address <= array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- litedramcore_dfi_p2_we_n <= (~array_muxed18);
- litedramcore_dfi_p2_rddata_en <= array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= array_muxed21;
- litedramcore_dfi_p3_address <= array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- litedramcore_dfi_p3_we_n <= (~array_muxed25);
- litedramcore_dfi_p3_rddata_en <= array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
+ soc_litedramcore_dfi_p0_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p0_bank <= vns_array_muxed0;
+ soc_litedramcore_dfi_p0_address <= vns_array_muxed1;
+ soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2);
+ soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3);
+ soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4);
+ soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5;
+ soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6;
+ soc_litedramcore_dfi_p1_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p1_bank <= vns_array_muxed7;
+ soc_litedramcore_dfi_p1_address <= vns_array_muxed8;
+ soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9);
+ soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10);
+ soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11);
+ soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12;
+ soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13;
+ soc_litedramcore_dfi_p2_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p2_bank <= vns_array_muxed14;
+ soc_litedramcore_dfi_p2_address <= vns_array_muxed15;
+ soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16);
+ soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17);
+ soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18);
+ soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19;
+ soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20;
+ soc_litedramcore_dfi_p3_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p3_bank <= vns_array_muxed21;
+ soc_litedramcore_dfi_p3_address <= vns_array_muxed22;
+ soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23);
+ soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24);
+ soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25);
+ soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26;
+ soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27;
+ if (soc_litedramcore_trrdcon_valid) begin
+ soc_litedramcore_trrdcon_count <= 1'd1;
if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
+ soc_litedramcore_trrdcon_ready <= 1'd1;
end else begin
- litedramcore_trrdcon_ready <= 1'd0;
+ soc_litedramcore_trrdcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
+ if ((~soc_litedramcore_trrdcon_ready)) begin
+ soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1);
+ if ((soc_litedramcore_trrdcon_count == 1'd1)) begin
+ soc_litedramcore_trrdcon_ready <= 1'd1;
end
end
end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid};
+ if ((soc_litedramcore_tfawcon_count < 3'd4)) begin
+ if ((soc_litedramcore_tfawcon_count == 2'd3)) begin
+ soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid);
end else begin
- litedramcore_tfawcon_ready <= 1'd1;
+ soc_litedramcore_tfawcon_ready <= 1'd1;
end
end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd0;
+ if (soc_litedramcore_tccdcon_valid) begin
+ soc_litedramcore_tccdcon_count <= 1'd0;
if (1'd1) begin
- litedramcore_tccdcon_ready <= 1'd1;
+ soc_litedramcore_tccdcon_ready <= 1'd1;
end else begin
- litedramcore_tccdcon_ready <= 1'd0;
+ soc_litedramcore_tccdcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
+ if ((~soc_litedramcore_tccdcon_ready)) begin
+ soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1);
+ if ((soc_litedramcore_tccdcon_count == 1'd1)) begin
+ soc_litedramcore_tccdcon_ready <= 1'd1;
end
end
end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd4;
+ if (soc_litedramcore_twtrcon_valid) begin
+ soc_litedramcore_twtrcon_count <= 3'd4;
if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
+ soc_litedramcore_twtrcon_ready <= 1'd1;
end else begin
- litedramcore_twtrcon_ready <= 1'd0;
+ soc_litedramcore_twtrcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- multiplexer_state <= multiplexer_next_state;
- new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- new_master_wdata_ready1 <= new_master_wdata_ready0;
- new_master_wdata_ready2 <= new_master_wdata_ready1;
- new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- new_master_rdata_valid1 <= new_master_rdata_valid0;
- new_master_rdata_valid2 <= new_master_rdata_valid1;
- new_master_rdata_valid3 <= new_master_rdata_valid2;
- new_master_rdata_valid4 <= new_master_rdata_valid3;
- new_master_rdata_valid5 <= new_master_rdata_valid4;
- new_master_rdata_valid6 <= new_master_rdata_valid5;
- new_master_rdata_valid7 <= new_master_rdata_valid6;
- new_master_rdata_valid8 <= new_master_rdata_valid7;
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[0])
+ if ((~soc_litedramcore_twtrcon_ready)) begin
+ soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1);
+ if ((soc_litedramcore_twtrcon_count == 1'd1)) begin
+ soc_litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_multiplexer_state <= vns_multiplexer_next_state;
+ vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
+ vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
+ vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
+ vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
+ vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
+ vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
+ vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
+ vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
+ vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
+ vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
+ vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
+ vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
+ vns_interface0_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank0_sel) begin
+ case (vns_interface0_bank_bus_adr[0])
1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w;
end
1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w;
end
endcase
end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
+ if (vns_csrbank0_init_done0_re) begin
+ soc_init_done_storage <= vns_csrbank0_init_done0_r;
end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
+ soc_init_done_re <= vns_csrbank0_init_done0_re;
+ if (vns_csrbank0_init_error0_re) begin
+ soc_init_error_storage <= vns_csrbank0_init_error0_r;
end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[3:0])
+ soc_init_error_re <= vns_csrbank0_init_error0_re;
+ vns_interface1_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank1_sel) begin
+ case (vns_interface1_bank_bus_adr[3:0])
1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w;
end
1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w;
end
2'd2: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w;
end
2'd3: begin
- interface1_bank_bus_dat_r <= a7ddrphy_cdly_rst_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
end
3'd4: begin
- interface1_bank_bus_dat_r <= a7ddrphy_cdly_inc_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
end
3'd5: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w;
end
3'd6: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
end
3'd7: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
end
4'd8: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
end
4'd9: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
end
endcase
end
- if (csrbank1_half_sys8x_taps0_re) begin
- a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+ if (vns_csrbank1_half_sys8x_taps0_re) begin
+ soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r;
end
- a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
- if (csrbank1_wlevel_en0_re) begin
- a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+ soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re;
+ if (vns_csrbank1_wlevel_en0_re) begin
+ soc_a7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r;
end
- a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
- if (csrbank1_dly_sel0_re) begin
- a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+ soc_a7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re;
+ if (vns_csrbank1_dly_sel0_re) begin
+ soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank1_dly_sel0_r;
end
- a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[4:0])
+ soc_a7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re;
+ vns_interface2_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank2_sel) begin
+ case (vns_interface2_bank_bus_adr[4:0])
1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w;
end
1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w;
end
2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w;
end
2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w;
end
3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w;
end
3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w;
end
3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata_w;
end
3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w;
end
4'd8: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
end
4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w;
end
4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w;
end
4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w;
end
4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata_w;
end
4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w;
end
4'd14: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
end
4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w;
end
5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w;
end
5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w;
end
5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata_w;
end
5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w;
end
5'd20: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w;
end
5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w;
end
5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w;
end
5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w;
end
5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata_w;
end
endcase
end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ if (vns_csrbank2_dfii_control0_re) begin
+ soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r;
end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ soc_litedramcore_re <= vns_csrbank2_dfii_control0_re;
+ if (vns_csrbank2_dfii_pi0_command0_re) begin
+ soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r;
end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
+ soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re;
+ if (vns_csrbank2_dfii_pi0_address0_re) begin
+ soc_litedramcore_phaseinjector0_address_storage[13:0] <= vns_csrbank2_dfii_pi0_address0_r;
end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re;
+ if (vns_csrbank2_dfii_pi0_baddress0_re) begin
+ soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r;
end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re;
+ if (vns_csrbank2_dfii_pi0_wrdata0_re) begin
+ soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r;
end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re;
+ if (vns_csrbank2_dfii_pi1_command0_re) begin
+ soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r;
end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
+ soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re;
+ if (vns_csrbank2_dfii_pi1_address0_re) begin
+ soc_litedramcore_phaseinjector1_address_storage[13:0] <= vns_csrbank2_dfii_pi1_address0_r;
end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re;
+ if (vns_csrbank2_dfii_pi1_baddress0_re) begin
+ soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r;
end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re;
+ if (vns_csrbank2_dfii_pi1_wrdata0_re) begin
+ soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r;
end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- if (csrbank2_dfii_pi2_command0_re) begin
- litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+ soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re;
+ if (vns_csrbank2_dfii_pi2_command0_re) begin
+ soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r;
end
- litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
+ soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re;
+ if (vns_csrbank2_dfii_pi2_address0_re) begin
+ soc_litedramcore_phaseinjector2_address_storage[13:0] <= vns_csrbank2_dfii_pi2_address0_r;
end
- litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
- if (csrbank2_dfii_pi2_baddress0_re) begin
- litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+ soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re;
+ if (vns_csrbank2_dfii_pi2_baddress0_re) begin
+ soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r;
end
- litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re;
+ if (vns_csrbank2_dfii_pi2_wrdata0_re) begin
+ soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r;
end
- litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
- if (csrbank2_dfii_pi3_command0_re) begin
- litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+ soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re;
+ if (vns_csrbank2_dfii_pi3_command0_re) begin
+ soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r;
end
- litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
+ soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re;
+ if (vns_csrbank2_dfii_pi3_address0_re) begin
+ soc_litedramcore_phaseinjector3_address_storage[13:0] <= vns_csrbank2_dfii_pi3_address0_r;
end
- litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
- if (csrbank2_dfii_pi3_baddress0_re) begin
- litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+ soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re;
+ if (vns_csrbank2_dfii_pi3_baddress0_re) begin
+ soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r;
end
- litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re;
+ if (vns_csrbank2_dfii_pi3_wrdata0_re) begin
+ soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r;
end
- litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+ soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re;
if (sys_rst) begin
- a7ddrphy_half_sys8x_taps_storage <= 5'd8;
- a7ddrphy_half_sys8x_taps_re <= 1'd0;
- a7ddrphy_wlevel_en_storage <= 1'd0;
- a7ddrphy_wlevel_en_re <= 1'd0;
- a7ddrphy_dly_sel_storage <= 2'd0;
- a7ddrphy_dly_sel_re <= 1'd0;
- a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
- a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
- a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
- a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
- a7ddrphy_dqs_oe_delayed <= 1'd0;
- a7ddrphy_dqspattern_o1 <= 8'd0;
- a7ddrphy_dq_oe_delayed <= 1'd0;
- a7ddrphy_bitslip0_value <= 4'd0;
- a7ddrphy_bitslip1_value <= 4'd0;
- a7ddrphy_bitslip2_value <= 4'd0;
- a7ddrphy_bitslip3_value <= 4'd0;
- a7ddrphy_bitslip4_value <= 4'd0;
- a7ddrphy_bitslip5_value <= 4'd0;
- a7ddrphy_bitslip6_value <= 4'd0;
- a7ddrphy_bitslip7_value <= 4'd0;
- a7ddrphy_bitslip8_value <= 4'd0;
- a7ddrphy_bitslip9_value <= 4'd0;
- a7ddrphy_bitslip10_value <= 4'd0;
- a7ddrphy_bitslip11_value <= 4'd0;
- a7ddrphy_bitslip12_value <= 4'd0;
- a7ddrphy_bitslip13_value <= 4'd0;
- a7ddrphy_bitslip14_value <= 4'd0;
- a7ddrphy_bitslip15_value <= 4'd0;
- a7ddrphy_rddata_en_last <= 8'd0;
- a7ddrphy_wrdata_en_last <= 4'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_status <= 32'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_status <= 32'd0;
- litedramcore_phaseinjector2_command_storage <= 6'd0;
- litedramcore_phaseinjector2_command_re <= 1'd0;
- litedramcore_phaseinjector2_address_re <= 1'd0;
- litedramcore_phaseinjector2_baddress_re <= 1'd0;
- litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- litedramcore_phaseinjector2_status <= 32'd0;
- litedramcore_phaseinjector3_command_storage <= 6'd0;
- litedramcore_phaseinjector3_command_re <= 1'd0;
- litedramcore_phaseinjector3_address_re <= 1'd0;
- litedramcore_phaseinjector3_baddress_re <= 1'd0;
- litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- litedramcore_phaseinjector3_status <= 32'd0;
- litedramcore_dfi_p0_address <= 14'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 14'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_dfi_p2_address <= 14'd0;
- litedramcore_dfi_p2_bank <= 3'd0;
- litedramcore_dfi_p2_cas_n <= 1'd1;
- litedramcore_dfi_p2_cs_n <= 1'd1;
- litedramcore_dfi_p2_ras_n <= 1'd1;
- litedramcore_dfi_p2_we_n <= 1'd1;
- litedramcore_dfi_p2_wrdata_en <= 1'd0;
- litedramcore_dfi_p2_rddata_en <= 1'd0;
- litedramcore_dfi_p3_address <= 14'd0;
- litedramcore_dfi_p3_bank <= 3'd0;
- litedramcore_dfi_p3_cas_n <= 1'd1;
- litedramcore_dfi_p3_cs_n <= 1'd1;
- litedramcore_dfi_p3_ras_n <= 1'd1;
- litedramcore_dfi_p3_we_n <= 1'd1;
- litedramcore_dfi_p3_wrdata_en <= 1'd0;
- litedramcore_dfi_p3_rddata_en <= 1'd0;
- litedramcore_timer_count1 <= 10'd781;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 6'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_row <= 14'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 3'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_row <= 14'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 3'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_row <= 14'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 3'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_row <= 14'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 3'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_row <= 14'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 3'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_row <= 14'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 3'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_row <= 14'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 3'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_row <= 14'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 3'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- state <= 1'd0;
- refresher_state <= 2'd0;
- bankmachine0_state <= 4'd0;
- bankmachine1_state <= 4'd0;
- bankmachine2_state <= 4'd0;
- bankmachine3_state <= 4'd0;
- bankmachine4_state <= 4'd0;
- bankmachine5_state <= 4'd0;
- bankmachine6_state <= 4'd0;
- bankmachine7_state <= 4'd0;
- multiplexer_state <= 4'd0;
- new_master_wdata_ready0 <= 1'd0;
- new_master_wdata_ready1 <= 1'd0;
- new_master_wdata_ready2 <= 1'd0;
- new_master_rdata_valid0 <= 1'd0;
- new_master_rdata_valid1 <= 1'd0;
- new_master_rdata_valid2 <= 1'd0;
- new_master_rdata_valid3 <= 1'd0;
- new_master_rdata_valid4 <= 1'd0;
- new_master_rdata_valid5 <= 1'd0;
- new_master_rdata_valid6 <= 1'd0;
- new_master_rdata_valid7 <= 1'd0;
- new_master_rdata_valid8 <= 1'd0;
+ soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ soc_a7ddrphy_wlevel_en_storage <= 1'd0;
+ soc_a7ddrphy_wlevel_en_re <= 1'd0;
+ soc_a7ddrphy_dly_sel_storage <= 2'd0;
+ soc_a7ddrphy_dly_sel_re <= 1'd0;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dqs_oe_delayed <= 1'd0;
+ soc_a7ddrphy_dqspattern_o1 <= 8'd0;
+ soc_a7ddrphy_dq_oe_delayed <= 1'd0;
+ soc_a7ddrphy_bitslip0_value <= 4'd0;
+ soc_a7ddrphy_bitslip1_value <= 4'd0;
+ soc_a7ddrphy_bitslip2_value <= 4'd0;
+ soc_a7ddrphy_bitslip3_value <= 4'd0;
+ soc_a7ddrphy_bitslip4_value <= 4'd0;
+ soc_a7ddrphy_bitslip5_value <= 4'd0;
+ soc_a7ddrphy_bitslip6_value <= 4'd0;
+ soc_a7ddrphy_bitslip7_value <= 4'd0;
+ soc_a7ddrphy_bitslip8_value <= 4'd0;
+ soc_a7ddrphy_bitslip9_value <= 4'd0;
+ soc_a7ddrphy_bitslip10_value <= 4'd0;
+ soc_a7ddrphy_bitslip11_value <= 4'd0;
+ soc_a7ddrphy_bitslip12_value <= 4'd0;
+ soc_a7ddrphy_bitslip13_value <= 4'd0;
+ soc_a7ddrphy_bitslip14_value <= 4'd0;
+ soc_a7ddrphy_bitslip15_value <= 4'd0;
+ soc_a7ddrphy_rddata_en_last <= 8'd0;
+ soc_a7ddrphy_wrdata_en_last <= 4'd0;
+ soc_litedramcore_storage <= 4'd1;
+ soc_litedramcore_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector0_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_status <= 32'd0;
+ soc_litedramcore_phaseinjector1_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector1_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_status <= 32'd0;
+ soc_litedramcore_phaseinjector2_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector2_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_status <= 32'd0;
+ soc_litedramcore_phaseinjector3_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector3_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_status <= 32'd0;
+ soc_litedramcore_dfi_p0_address <= 14'd0;
+ soc_litedramcore_dfi_p0_bank <= 3'd0;
+ soc_litedramcore_dfi_p0_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p0_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p0_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p0_we_n <= 1'd1;
+ soc_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p0_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p1_address <= 14'd0;
+ soc_litedramcore_dfi_p1_bank <= 3'd0;
+ soc_litedramcore_dfi_p1_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p1_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p1_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p1_we_n <= 1'd1;
+ soc_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p1_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p2_address <= 14'd0;
+ soc_litedramcore_dfi_p2_bank <= 3'd0;
+ soc_litedramcore_dfi_p2_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p2_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p2_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p2_we_n <= 1'd1;
+ soc_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p2_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p3_address <= 14'd0;
+ soc_litedramcore_dfi_p3_bank <= 3'd0;
+ soc_litedramcore_dfi_p3_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p3_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p3_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p3_we_n <= 1'd1;
+ soc_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p3_rddata_en <= 1'd0;
+ soc_litedramcore_timer_count1 <= 10'd781;
+ soc_litedramcore_postponer_req_o <= 1'd0;
+ soc_litedramcore_postponer_count <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd0;
+ soc_litedramcore_sequencer_counter <= 6'd0;
+ soc_litedramcore_sequencer_count <= 1'd0;
+ soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ soc_litedramcore_zqcs_executer_done <= 1'd0;
+ soc_litedramcore_zqcs_executer_counter <= 5'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine0_row <= 14'd0;
+ soc_litedramcore_bankmachine0_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine1_row <= 14'd0;
+ soc_litedramcore_bankmachine1_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine2_row <= 14'd0;
+ soc_litedramcore_bankmachine2_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine3_row <= 14'd0;
+ soc_litedramcore_bankmachine3_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine4_row <= 14'd0;
+ soc_litedramcore_bankmachine4_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine5_row <= 14'd0;
+ soc_litedramcore_bankmachine5_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine6_row <= 14'd0;
+ soc_litedramcore_bankmachine6_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine7_row <= 14'd0;
+ soc_litedramcore_bankmachine7_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trascon_count <= 3'd0;
+ soc_litedramcore_choose_cmd_grant <= 3'd0;
+ soc_litedramcore_choose_req_grant <= 3'd0;
+ soc_litedramcore_trrdcon_ready <= 1'd0;
+ soc_litedramcore_trrdcon_count <= 1'd0;
+ soc_litedramcore_tfawcon_ready <= 1'd1;
+ soc_litedramcore_tfawcon_window <= 5'd0;
+ soc_litedramcore_tccdcon_ready <= 1'd0;
+ soc_litedramcore_tccdcon_count <= 1'd0;
+ soc_litedramcore_twtrcon_ready <= 1'd0;
+ soc_litedramcore_twtrcon_count <= 3'd0;
+ soc_litedramcore_time0 <= 5'd0;
+ soc_litedramcore_time1 <= 4'd0;
+ soc_init_done_storage <= 1'd0;
+ soc_init_done_re <= 1'd0;
+ soc_init_error_storage <= 1'd0;
+ soc_init_error_re <= 1'd0;
+ vns_state <= 1'd0;
+ vns_refresher_state <= 2'd0;
+ vns_bankmachine0_state <= 4'd0;
+ vns_bankmachine1_state <= 4'd0;
+ vns_bankmachine2_state <= 4'd0;
+ vns_bankmachine3_state <= 4'd0;
+ vns_bankmachine4_state <= 4'd0;
+ vns_bankmachine5_state <= 4'd0;
+ vns_bankmachine6_state <= 4'd0;
+ vns_bankmachine7_state <= 4'd0;
+ vns_multiplexer_state <= 4'd0;
+ vns_new_master_wdata_ready0 <= 1'd0;
+ vns_new_master_wdata_ready1 <= 1'd0;
+ vns_new_master_wdata_ready2 <= 1'd0;
+ vns_new_master_rdata_valid0 <= 1'd0;
+ vns_new_master_rdata_valid1 <= 1'd0;
+ vns_new_master_rdata_valid2 <= 1'd0;
+ vns_new_master_rdata_valid3 <= 1'd0;
+ vns_new_master_rdata_valid4 <= 1'd0;
+ vns_new_master_rdata_valid5 <= 1'd0;
+ vns_new_master_rdata_valid6 <= 1'd0;
+ vns_new_master_rdata_valid7 <= 1'd0;
+ vns_new_master_rdata_valid8 <= 1'd0;
end
end
BUFG BUFG(
- .I(s7pll0_clkout0),
- .O(s7pll0_clkout_buf0)
+ .I(soc_clkout0),
+ .O(soc_clkout_buf0)
);
BUFG BUFG_1(
- .I(s7pll0_clkout1),
- .O(s7pll0_clkout_buf1)
+ .I(soc_clkout1),
+ .O(soc_clkout_buf1)
);
BUFG BUFG_2(
- .I(s7pll0_clkout2),
- .O(s7pll0_clkout_buf2)
+ .I(soc_clkout2),
+ .O(soc_clkout_buf2)
);
BUFG BUFG_3(
- .I(s7pll1_clkout),
- .O(s7pll1_clkout_buf)
+ .I(soc_clkout3),
+ .O(soc_clkout_buf3)
);
IDELAYCTRL IDELAYCTRL(
.REFCLK(iodelay_clk),
- .RST(ic_reset)
+ .RST(soc_ic_reset)
);
OSERDESE2 #(
.D8(1'd1),
.OCE(1'd1),
.RST(sys_rst),
- .OQ(a7ddrphy_sd_clk_se_nodelay)
+ .OQ(soc_a7ddrphy_sd_clk_se_nodelay)
);
OBUFDS OBUFDS(
- .I(a7ddrphy_sd_clk_se_nodelay),
+ .I(soc_a7ddrphy_sd_clk_se_nodelay),
.O(ddram_clk_p),
.OB(ddram_clk_n)
);
) OSERDESE2_1 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[0]),
- .D2(a7ddrphy_dfi_p0_address[0]),
- .D3(a7ddrphy_dfi_p1_address[0]),
- .D4(a7ddrphy_dfi_p1_address[0]),
- .D5(a7ddrphy_dfi_p2_address[0]),
- .D6(a7ddrphy_dfi_p2_address[0]),
- .D7(a7ddrphy_dfi_p3_address[0]),
- .D8(a7ddrphy_dfi_p3_address[0]),
+ .D1(soc_a7ddrphy_dfi_p0_address[0]),
+ .D2(soc_a7ddrphy_dfi_p0_address[0]),
+ .D3(soc_a7ddrphy_dfi_p1_address[0]),
+ .D4(soc_a7ddrphy_dfi_p1_address[0]),
+ .D5(soc_a7ddrphy_dfi_p2_address[0]),
+ .D6(soc_a7ddrphy_dfi_p2_address[0]),
+ .D7(soc_a7ddrphy_dfi_p3_address[0]),
+ .D8(soc_a7ddrphy_dfi_p3_address[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[0])
) OSERDESE2_2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[1]),
- .D2(a7ddrphy_dfi_p0_address[1]),
- .D3(a7ddrphy_dfi_p1_address[1]),
- .D4(a7ddrphy_dfi_p1_address[1]),
- .D5(a7ddrphy_dfi_p2_address[1]),
- .D6(a7ddrphy_dfi_p2_address[1]),
- .D7(a7ddrphy_dfi_p3_address[1]),
- .D8(a7ddrphy_dfi_p3_address[1]),
+ .D1(soc_a7ddrphy_dfi_p0_address[1]),
+ .D2(soc_a7ddrphy_dfi_p0_address[1]),
+ .D3(soc_a7ddrphy_dfi_p1_address[1]),
+ .D4(soc_a7ddrphy_dfi_p1_address[1]),
+ .D5(soc_a7ddrphy_dfi_p2_address[1]),
+ .D6(soc_a7ddrphy_dfi_p2_address[1]),
+ .D7(soc_a7ddrphy_dfi_p3_address[1]),
+ .D8(soc_a7ddrphy_dfi_p3_address[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[1])
) OSERDESE2_3 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[2]),
- .D2(a7ddrphy_dfi_p0_address[2]),
- .D3(a7ddrphy_dfi_p1_address[2]),
- .D4(a7ddrphy_dfi_p1_address[2]),
- .D5(a7ddrphy_dfi_p2_address[2]),
- .D6(a7ddrphy_dfi_p2_address[2]),
- .D7(a7ddrphy_dfi_p3_address[2]),
- .D8(a7ddrphy_dfi_p3_address[2]),
+ .D1(soc_a7ddrphy_dfi_p0_address[2]),
+ .D2(soc_a7ddrphy_dfi_p0_address[2]),
+ .D3(soc_a7ddrphy_dfi_p1_address[2]),
+ .D4(soc_a7ddrphy_dfi_p1_address[2]),
+ .D5(soc_a7ddrphy_dfi_p2_address[2]),
+ .D6(soc_a7ddrphy_dfi_p2_address[2]),
+ .D7(soc_a7ddrphy_dfi_p3_address[2]),
+ .D8(soc_a7ddrphy_dfi_p3_address[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[2])
) OSERDESE2_4 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[3]),
- .D2(a7ddrphy_dfi_p0_address[3]),
- .D3(a7ddrphy_dfi_p1_address[3]),
- .D4(a7ddrphy_dfi_p1_address[3]),
- .D5(a7ddrphy_dfi_p2_address[3]),
- .D6(a7ddrphy_dfi_p2_address[3]),
- .D7(a7ddrphy_dfi_p3_address[3]),
- .D8(a7ddrphy_dfi_p3_address[3]),
+ .D1(soc_a7ddrphy_dfi_p0_address[3]),
+ .D2(soc_a7ddrphy_dfi_p0_address[3]),
+ .D3(soc_a7ddrphy_dfi_p1_address[3]),
+ .D4(soc_a7ddrphy_dfi_p1_address[3]),
+ .D5(soc_a7ddrphy_dfi_p2_address[3]),
+ .D6(soc_a7ddrphy_dfi_p2_address[3]),
+ .D7(soc_a7ddrphy_dfi_p3_address[3]),
+ .D8(soc_a7ddrphy_dfi_p3_address[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[3])
) OSERDESE2_5 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[4]),
- .D2(a7ddrphy_dfi_p0_address[4]),
- .D3(a7ddrphy_dfi_p1_address[4]),
- .D4(a7ddrphy_dfi_p1_address[4]),
- .D5(a7ddrphy_dfi_p2_address[4]),
- .D6(a7ddrphy_dfi_p2_address[4]),
- .D7(a7ddrphy_dfi_p3_address[4]),
- .D8(a7ddrphy_dfi_p3_address[4]),
+ .D1(soc_a7ddrphy_dfi_p0_address[4]),
+ .D2(soc_a7ddrphy_dfi_p0_address[4]),
+ .D3(soc_a7ddrphy_dfi_p1_address[4]),
+ .D4(soc_a7ddrphy_dfi_p1_address[4]),
+ .D5(soc_a7ddrphy_dfi_p2_address[4]),
+ .D6(soc_a7ddrphy_dfi_p2_address[4]),
+ .D7(soc_a7ddrphy_dfi_p3_address[4]),
+ .D8(soc_a7ddrphy_dfi_p3_address[4]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[4])
) OSERDESE2_6 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[5]),
- .D2(a7ddrphy_dfi_p0_address[5]),
- .D3(a7ddrphy_dfi_p1_address[5]),
- .D4(a7ddrphy_dfi_p1_address[5]),
- .D5(a7ddrphy_dfi_p2_address[5]),
- .D6(a7ddrphy_dfi_p2_address[5]),
- .D7(a7ddrphy_dfi_p3_address[5]),
- .D8(a7ddrphy_dfi_p3_address[5]),
+ .D1(soc_a7ddrphy_dfi_p0_address[5]),
+ .D2(soc_a7ddrphy_dfi_p0_address[5]),
+ .D3(soc_a7ddrphy_dfi_p1_address[5]),
+ .D4(soc_a7ddrphy_dfi_p1_address[5]),
+ .D5(soc_a7ddrphy_dfi_p2_address[5]),
+ .D6(soc_a7ddrphy_dfi_p2_address[5]),
+ .D7(soc_a7ddrphy_dfi_p3_address[5]),
+ .D8(soc_a7ddrphy_dfi_p3_address[5]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[5])
) OSERDESE2_7 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[6]),
- .D2(a7ddrphy_dfi_p0_address[6]),
- .D3(a7ddrphy_dfi_p1_address[6]),
- .D4(a7ddrphy_dfi_p1_address[6]),
- .D5(a7ddrphy_dfi_p2_address[6]),
- .D6(a7ddrphy_dfi_p2_address[6]),
- .D7(a7ddrphy_dfi_p3_address[6]),
- .D8(a7ddrphy_dfi_p3_address[6]),
+ .D1(soc_a7ddrphy_dfi_p0_address[6]),
+ .D2(soc_a7ddrphy_dfi_p0_address[6]),
+ .D3(soc_a7ddrphy_dfi_p1_address[6]),
+ .D4(soc_a7ddrphy_dfi_p1_address[6]),
+ .D5(soc_a7ddrphy_dfi_p2_address[6]),
+ .D6(soc_a7ddrphy_dfi_p2_address[6]),
+ .D7(soc_a7ddrphy_dfi_p3_address[6]),
+ .D8(soc_a7ddrphy_dfi_p3_address[6]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[6])
) OSERDESE2_8 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[7]),
- .D2(a7ddrphy_dfi_p0_address[7]),
- .D3(a7ddrphy_dfi_p1_address[7]),
- .D4(a7ddrphy_dfi_p1_address[7]),
- .D5(a7ddrphy_dfi_p2_address[7]),
- .D6(a7ddrphy_dfi_p2_address[7]),
- .D7(a7ddrphy_dfi_p3_address[7]),
- .D8(a7ddrphy_dfi_p3_address[7]),
+ .D1(soc_a7ddrphy_dfi_p0_address[7]),
+ .D2(soc_a7ddrphy_dfi_p0_address[7]),
+ .D3(soc_a7ddrphy_dfi_p1_address[7]),
+ .D4(soc_a7ddrphy_dfi_p1_address[7]),
+ .D5(soc_a7ddrphy_dfi_p2_address[7]),
+ .D6(soc_a7ddrphy_dfi_p2_address[7]),
+ .D7(soc_a7ddrphy_dfi_p3_address[7]),
+ .D8(soc_a7ddrphy_dfi_p3_address[7]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[7])
) OSERDESE2_9 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[8]),
- .D2(a7ddrphy_dfi_p0_address[8]),
- .D3(a7ddrphy_dfi_p1_address[8]),
- .D4(a7ddrphy_dfi_p1_address[8]),
- .D5(a7ddrphy_dfi_p2_address[8]),
- .D6(a7ddrphy_dfi_p2_address[8]),
- .D7(a7ddrphy_dfi_p3_address[8]),
- .D8(a7ddrphy_dfi_p3_address[8]),
+ .D1(soc_a7ddrphy_dfi_p0_address[8]),
+ .D2(soc_a7ddrphy_dfi_p0_address[8]),
+ .D3(soc_a7ddrphy_dfi_p1_address[8]),
+ .D4(soc_a7ddrphy_dfi_p1_address[8]),
+ .D5(soc_a7ddrphy_dfi_p2_address[8]),
+ .D6(soc_a7ddrphy_dfi_p2_address[8]),
+ .D7(soc_a7ddrphy_dfi_p3_address[8]),
+ .D8(soc_a7ddrphy_dfi_p3_address[8]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[8])
) OSERDESE2_10 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[9]),
- .D2(a7ddrphy_dfi_p0_address[9]),
- .D3(a7ddrphy_dfi_p1_address[9]),
- .D4(a7ddrphy_dfi_p1_address[9]),
- .D5(a7ddrphy_dfi_p2_address[9]),
- .D6(a7ddrphy_dfi_p2_address[9]),
- .D7(a7ddrphy_dfi_p3_address[9]),
- .D8(a7ddrphy_dfi_p3_address[9]),
+ .D1(soc_a7ddrphy_dfi_p0_address[9]),
+ .D2(soc_a7ddrphy_dfi_p0_address[9]),
+ .D3(soc_a7ddrphy_dfi_p1_address[9]),
+ .D4(soc_a7ddrphy_dfi_p1_address[9]),
+ .D5(soc_a7ddrphy_dfi_p2_address[9]),
+ .D6(soc_a7ddrphy_dfi_p2_address[9]),
+ .D7(soc_a7ddrphy_dfi_p3_address[9]),
+ .D8(soc_a7ddrphy_dfi_p3_address[9]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[9])
) OSERDESE2_11 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[10]),
- .D2(a7ddrphy_dfi_p0_address[10]),
- .D3(a7ddrphy_dfi_p1_address[10]),
- .D4(a7ddrphy_dfi_p1_address[10]),
- .D5(a7ddrphy_dfi_p2_address[10]),
- .D6(a7ddrphy_dfi_p2_address[10]),
- .D7(a7ddrphy_dfi_p3_address[10]),
- .D8(a7ddrphy_dfi_p3_address[10]),
+ .D1(soc_a7ddrphy_dfi_p0_address[10]),
+ .D2(soc_a7ddrphy_dfi_p0_address[10]),
+ .D3(soc_a7ddrphy_dfi_p1_address[10]),
+ .D4(soc_a7ddrphy_dfi_p1_address[10]),
+ .D5(soc_a7ddrphy_dfi_p2_address[10]),
+ .D6(soc_a7ddrphy_dfi_p2_address[10]),
+ .D7(soc_a7ddrphy_dfi_p3_address[10]),
+ .D8(soc_a7ddrphy_dfi_p3_address[10]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[10])
) OSERDESE2_12 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[11]),
- .D2(a7ddrphy_dfi_p0_address[11]),
- .D3(a7ddrphy_dfi_p1_address[11]),
- .D4(a7ddrphy_dfi_p1_address[11]),
- .D5(a7ddrphy_dfi_p2_address[11]),
- .D6(a7ddrphy_dfi_p2_address[11]),
- .D7(a7ddrphy_dfi_p3_address[11]),
- .D8(a7ddrphy_dfi_p3_address[11]),
+ .D1(soc_a7ddrphy_dfi_p0_address[11]),
+ .D2(soc_a7ddrphy_dfi_p0_address[11]),
+ .D3(soc_a7ddrphy_dfi_p1_address[11]),
+ .D4(soc_a7ddrphy_dfi_p1_address[11]),
+ .D5(soc_a7ddrphy_dfi_p2_address[11]),
+ .D6(soc_a7ddrphy_dfi_p2_address[11]),
+ .D7(soc_a7ddrphy_dfi_p3_address[11]),
+ .D8(soc_a7ddrphy_dfi_p3_address[11]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[11])
) OSERDESE2_13 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[12]),
- .D2(a7ddrphy_dfi_p0_address[12]),
- .D3(a7ddrphy_dfi_p1_address[12]),
- .D4(a7ddrphy_dfi_p1_address[12]),
- .D5(a7ddrphy_dfi_p2_address[12]),
- .D6(a7ddrphy_dfi_p2_address[12]),
- .D7(a7ddrphy_dfi_p3_address[12]),
- .D8(a7ddrphy_dfi_p3_address[12]),
+ .D1(soc_a7ddrphy_dfi_p0_address[12]),
+ .D2(soc_a7ddrphy_dfi_p0_address[12]),
+ .D3(soc_a7ddrphy_dfi_p1_address[12]),
+ .D4(soc_a7ddrphy_dfi_p1_address[12]),
+ .D5(soc_a7ddrphy_dfi_p2_address[12]),
+ .D6(soc_a7ddrphy_dfi_p2_address[12]),
+ .D7(soc_a7ddrphy_dfi_p3_address[12]),
+ .D8(soc_a7ddrphy_dfi_p3_address[12]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[12])
) OSERDESE2_14 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[13]),
- .D2(a7ddrphy_dfi_p0_address[13]),
- .D3(a7ddrphy_dfi_p1_address[13]),
- .D4(a7ddrphy_dfi_p1_address[13]),
- .D5(a7ddrphy_dfi_p2_address[13]),
- .D6(a7ddrphy_dfi_p2_address[13]),
- .D7(a7ddrphy_dfi_p3_address[13]),
- .D8(a7ddrphy_dfi_p3_address[13]),
+ .D1(soc_a7ddrphy_dfi_p0_address[13]),
+ .D2(soc_a7ddrphy_dfi_p0_address[13]),
+ .D3(soc_a7ddrphy_dfi_p1_address[13]),
+ .D4(soc_a7ddrphy_dfi_p1_address[13]),
+ .D5(soc_a7ddrphy_dfi_p2_address[13]),
+ .D6(soc_a7ddrphy_dfi_p2_address[13]),
+ .D7(soc_a7ddrphy_dfi_p3_address[13]),
+ .D8(soc_a7ddrphy_dfi_p3_address[13]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[13])
) OSERDESE2_15 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_bank[0]),
- .D2(a7ddrphy_dfi_p0_bank[0]),
- .D3(a7ddrphy_dfi_p1_bank[0]),
- .D4(a7ddrphy_dfi_p1_bank[0]),
- .D5(a7ddrphy_dfi_p2_bank[0]),
- .D6(a7ddrphy_dfi_p2_bank[0]),
- .D7(a7ddrphy_dfi_p3_bank[0]),
- .D8(a7ddrphy_dfi_p3_bank[0]),
+ .D1(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[0]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[0])
) OSERDESE2_16 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_bank[1]),
- .D2(a7ddrphy_dfi_p0_bank[1]),
- .D3(a7ddrphy_dfi_p1_bank[1]),
- .D4(a7ddrphy_dfi_p1_bank[1]),
- .D5(a7ddrphy_dfi_p2_bank[1]),
- .D6(a7ddrphy_dfi_p2_bank[1]),
- .D7(a7ddrphy_dfi_p3_bank[1]),
- .D8(a7ddrphy_dfi_p3_bank[1]),
+ .D1(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[1]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[1])
) OSERDESE2_17 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_bank[2]),
- .D2(a7ddrphy_dfi_p0_bank[2]),
- .D3(a7ddrphy_dfi_p1_bank[2]),
- .D4(a7ddrphy_dfi_p1_bank[2]),
- .D5(a7ddrphy_dfi_p2_bank[2]),
- .D6(a7ddrphy_dfi_p2_bank[2]),
- .D7(a7ddrphy_dfi_p3_bank[2]),
- .D8(a7ddrphy_dfi_p3_bank[2]),
+ .D1(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[2]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[2])
) OSERDESE2_18 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_ras_n),
- .D2(a7ddrphy_dfi_p0_ras_n),
- .D3(a7ddrphy_dfi_p1_ras_n),
- .D4(a7ddrphy_dfi_p1_ras_n),
- .D5(a7ddrphy_dfi_p2_ras_n),
- .D6(a7ddrphy_dfi_p2_ras_n),
- .D7(a7ddrphy_dfi_p3_ras_n),
- .D8(a7ddrphy_dfi_p3_ras_n),
+ .D1(soc_a7ddrphy_dfi_p0_ras_n),
+ .D2(soc_a7ddrphy_dfi_p0_ras_n),
+ .D3(soc_a7ddrphy_dfi_p1_ras_n),
+ .D4(soc_a7ddrphy_dfi_p1_ras_n),
+ .D5(soc_a7ddrphy_dfi_p2_ras_n),
+ .D6(soc_a7ddrphy_dfi_p2_ras_n),
+ .D7(soc_a7ddrphy_dfi_p3_ras_n),
+ .D8(soc_a7ddrphy_dfi_p3_ras_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ras_n)
) OSERDESE2_19 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_cas_n),
- .D2(a7ddrphy_dfi_p0_cas_n),
- .D3(a7ddrphy_dfi_p1_cas_n),
- .D4(a7ddrphy_dfi_p1_cas_n),
- .D5(a7ddrphy_dfi_p2_cas_n),
- .D6(a7ddrphy_dfi_p2_cas_n),
- .D7(a7ddrphy_dfi_p3_cas_n),
- .D8(a7ddrphy_dfi_p3_cas_n),
+ .D1(soc_a7ddrphy_dfi_p0_cas_n),
+ .D2(soc_a7ddrphy_dfi_p0_cas_n),
+ .D3(soc_a7ddrphy_dfi_p1_cas_n),
+ .D4(soc_a7ddrphy_dfi_p1_cas_n),
+ .D5(soc_a7ddrphy_dfi_p2_cas_n),
+ .D6(soc_a7ddrphy_dfi_p2_cas_n),
+ .D7(soc_a7ddrphy_dfi_p3_cas_n),
+ .D8(soc_a7ddrphy_dfi_p3_cas_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cas_n)
) OSERDESE2_20 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_we_n),
- .D2(a7ddrphy_dfi_p0_we_n),
- .D3(a7ddrphy_dfi_p1_we_n),
- .D4(a7ddrphy_dfi_p1_we_n),
- .D5(a7ddrphy_dfi_p2_we_n),
- .D6(a7ddrphy_dfi_p2_we_n),
- .D7(a7ddrphy_dfi_p3_we_n),
- .D8(a7ddrphy_dfi_p3_we_n),
+ .D1(soc_a7ddrphy_dfi_p0_we_n),
+ .D2(soc_a7ddrphy_dfi_p0_we_n),
+ .D3(soc_a7ddrphy_dfi_p1_we_n),
+ .D4(soc_a7ddrphy_dfi_p1_we_n),
+ .D5(soc_a7ddrphy_dfi_p2_we_n),
+ .D6(soc_a7ddrphy_dfi_p2_we_n),
+ .D7(soc_a7ddrphy_dfi_p3_we_n),
+ .D8(soc_a7ddrphy_dfi_p3_we_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_we_n)
) OSERDESE2_21 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_cke),
- .D2(a7ddrphy_dfi_p0_cke),
- .D3(a7ddrphy_dfi_p1_cke),
- .D4(a7ddrphy_dfi_p1_cke),
- .D5(a7ddrphy_dfi_p2_cke),
- .D6(a7ddrphy_dfi_p2_cke),
- .D7(a7ddrphy_dfi_p3_cke),
- .D8(a7ddrphy_dfi_p3_cke),
+ .D1(soc_a7ddrphy_dfi_p0_cke),
+ .D2(soc_a7ddrphy_dfi_p0_cke),
+ .D3(soc_a7ddrphy_dfi_p1_cke),
+ .D4(soc_a7ddrphy_dfi_p1_cke),
+ .D5(soc_a7ddrphy_dfi_p2_cke),
+ .D6(soc_a7ddrphy_dfi_p2_cke),
+ .D7(soc_a7ddrphy_dfi_p3_cke),
+ .D8(soc_a7ddrphy_dfi_p3_cke),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cke)
) OSERDESE2_22 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_odt),
- .D2(a7ddrphy_dfi_p0_odt),
- .D3(a7ddrphy_dfi_p1_odt),
- .D4(a7ddrphy_dfi_p1_odt),
- .D5(a7ddrphy_dfi_p2_odt),
- .D6(a7ddrphy_dfi_p2_odt),
- .D7(a7ddrphy_dfi_p3_odt),
- .D8(a7ddrphy_dfi_p3_odt),
+ .D1(soc_a7ddrphy_dfi_p0_odt),
+ .D2(soc_a7ddrphy_dfi_p0_odt),
+ .D3(soc_a7ddrphy_dfi_p1_odt),
+ .D4(soc_a7ddrphy_dfi_p1_odt),
+ .D5(soc_a7ddrphy_dfi_p2_odt),
+ .D6(soc_a7ddrphy_dfi_p2_odt),
+ .D7(soc_a7ddrphy_dfi_p3_odt),
+ .D8(soc_a7ddrphy_dfi_p3_odt),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_odt)
) OSERDESE2_23 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_reset_n),
- .D2(a7ddrphy_dfi_p0_reset_n),
- .D3(a7ddrphy_dfi_p1_reset_n),
- .D4(a7ddrphy_dfi_p1_reset_n),
- .D5(a7ddrphy_dfi_p2_reset_n),
- .D6(a7ddrphy_dfi_p2_reset_n),
- .D7(a7ddrphy_dfi_p3_reset_n),
- .D8(a7ddrphy_dfi_p3_reset_n),
+ .D1(soc_a7ddrphy_dfi_p0_reset_n),
+ .D2(soc_a7ddrphy_dfi_p0_reset_n),
+ .D3(soc_a7ddrphy_dfi_p1_reset_n),
+ .D4(soc_a7ddrphy_dfi_p1_reset_n),
+ .D5(soc_a7ddrphy_dfi_p2_reset_n),
+ .D6(soc_a7ddrphy_dfi_p2_reset_n),
+ .D7(soc_a7ddrphy_dfi_p3_reset_n),
+ .D8(soc_a7ddrphy_dfi_p3_reset_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_reset_n)
) OSERDESE2_24 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_cs_n),
- .D2(a7ddrphy_dfi_p0_cs_n),
- .D3(a7ddrphy_dfi_p1_cs_n),
- .D4(a7ddrphy_dfi_p1_cs_n),
- .D5(a7ddrphy_dfi_p2_cs_n),
- .D6(a7ddrphy_dfi_p2_cs_n),
- .D7(a7ddrphy_dfi_p3_cs_n),
- .D8(a7ddrphy_dfi_p3_cs_n),
+ .D1(soc_a7ddrphy_dfi_p0_cs_n),
+ .D2(soc_a7ddrphy_dfi_p0_cs_n),
+ .D3(soc_a7ddrphy_dfi_p1_cs_n),
+ .D4(soc_a7ddrphy_dfi_p1_cs_n),
+ .D5(soc_a7ddrphy_dfi_p2_cs_n),
+ .D6(soc_a7ddrphy_dfi_p2_cs_n),
+ .D7(soc_a7ddrphy_dfi_p3_cs_n),
+ .D8(soc_a7ddrphy_dfi_p3_cs_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cs_n)
) OSERDESE2_25 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata_mask[0]),
- .D2(a7ddrphy_dfi_p0_wrdata_mask[2]),
- .D3(a7ddrphy_dfi_p1_wrdata_mask[0]),
- .D4(a7ddrphy_dfi_p1_wrdata_mask[2]),
- .D5(a7ddrphy_dfi_p2_wrdata_mask[0]),
- .D6(a7ddrphy_dfi_p2_wrdata_mask[2]),
- .D7(a7ddrphy_dfi_p3_wrdata_mask[0]),
- .D8(a7ddrphy_dfi_p3_wrdata_mask[2]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm[0])
) OSERDESE2_26 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata_mask[1]),
- .D2(a7ddrphy_dfi_p0_wrdata_mask[3]),
- .D3(a7ddrphy_dfi_p1_wrdata_mask[1]),
- .D4(a7ddrphy_dfi_p1_wrdata_mask[3]),
- .D5(a7ddrphy_dfi_p2_wrdata_mask[1]),
- .D6(a7ddrphy_dfi_p2_wrdata_mask[3]),
- .D7(a7ddrphy_dfi_p3_wrdata_mask[1]),
- .D8(a7ddrphy_dfi_p3_wrdata_mask[3]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm[1])
) OSERDESE2_27 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dqspattern_o1[0]),
- .D2(a7ddrphy_dqspattern_o1[1]),
- .D3(a7ddrphy_dqspattern_o1[2]),
- .D4(a7ddrphy_dqspattern_o1[3]),
- .D5(a7ddrphy_dqspattern_o1[4]),
- .D6(a7ddrphy_dqspattern_o1[5]),
- .D7(a7ddrphy_dqspattern_o1[6]),
- .D8(a7ddrphy_dqspattern_o1[7]),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dqs_oe_delayed)),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
.TCE(1'd1),
- .OFB(a7ddrphy0),
- .OQ(a7ddrphy_dqs_o_no_delay0),
- .TQ(a7ddrphy_dqs_t0)
+ .OFB(soc_a7ddrphy0),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay0),
+ .TQ(soc_a7ddrphy_dqs_t0)
);
IDELAYE2 #(
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2 (
- .IDATAIN(a7ddrphy_dqs_i[0]),
- .DATAOUT(a7ddrphy_dqs_i_delayed[0])
+ .IDATAIN(soc_a7ddrphy_dqs_i[0]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0])
);
IOBUFDS IOBUFDS(
- .I(a7ddrphy_dqs_o_no_delay0),
- .T(a7ddrphy_dqs_t0),
+ .I(soc_a7ddrphy_dqs_o_no_delay0),
+ .T(soc_a7ddrphy_dqs_t0),
.IO(ddram_dqs_p[0]),
.IOB(ddram_dqs_n[0]),
- .O(a7ddrphy_dqs_i[0])
+ .O(soc_a7ddrphy_dqs_i[0])
);
OSERDESE2 #(
) OSERDESE2_28 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dqspattern_o1[0]),
- .D2(a7ddrphy_dqspattern_o1[1]),
- .D3(a7ddrphy_dqspattern_o1[2]),
- .D4(a7ddrphy_dqspattern_o1[3]),
- .D5(a7ddrphy_dqspattern_o1[4]),
- .D6(a7ddrphy_dqspattern_o1[5]),
- .D7(a7ddrphy_dqspattern_o1[6]),
- .D8(a7ddrphy_dqspattern_o1[7]),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dqs_oe_delayed)),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
.TCE(1'd1),
- .OFB(a7ddrphy1),
- .OQ(a7ddrphy_dqs_o_no_delay1),
- .TQ(a7ddrphy_dqs_t1)
+ .OFB(soc_a7ddrphy1),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay1),
+ .TQ(soc_a7ddrphy_dqs_t1)
);
IDELAYE2 #(
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_1 (
- .IDATAIN(a7ddrphy_dqs_i[1]),
- .DATAOUT(a7ddrphy_dqs_i_delayed[1])
+ .IDATAIN(soc_a7ddrphy_dqs_i[1]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1])
);
IOBUFDS IOBUFDS_1(
- .I(a7ddrphy_dqs_o_no_delay1),
- .T(a7ddrphy_dqs_t1),
+ .I(soc_a7ddrphy_dqs_o_no_delay1),
+ .T(soc_a7ddrphy_dqs_t1),
.IO(ddram_dqs_p[1]),
.IOB(ddram_dqs_n[1]),
- .O(a7ddrphy_dqs_i[1])
+ .O(soc_a7ddrphy_dqs_i[1])
);
OSERDESE2 #(
) OSERDESE2_29 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[0]),
- .D2(a7ddrphy_dfi_p0_wrdata[16]),
- .D3(a7ddrphy_dfi_p1_wrdata[0]),
- .D4(a7ddrphy_dfi_p1_wrdata[16]),
- .D5(a7ddrphy_dfi_p2_wrdata[0]),
- .D6(a7ddrphy_dfi_p2_wrdata[16]),
- .D7(a7ddrphy_dfi_p3_wrdata[0]),
- .D8(a7ddrphy_dfi_p3_wrdata[16]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay0),
- .TQ(a7ddrphy_dq_t0)
+ .OQ(soc_a7ddrphy_dq_o_nodelay0),
+ .TQ(soc_a7ddrphy_dq_t0)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed0),
+ .DDLY(soc_a7ddrphy_dq_i_delayed0),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data0[7]),
- .Q2(a7ddrphy_dq_i_data0[6]),
- .Q3(a7ddrphy_dq_i_data0[5]),
- .Q4(a7ddrphy_dq_i_data0[4]),
- .Q5(a7ddrphy_dq_i_data0[3]),
- .Q6(a7ddrphy_dq_i_data0[2]),
- .Q7(a7ddrphy_dq_i_data0[1]),
- .Q8(a7ddrphy_dq_i_data0[0])
+ .Q1(soc_a7ddrphy_dq_i_data0[7]),
+ .Q2(soc_a7ddrphy_dq_i_data0[6]),
+ .Q3(soc_a7ddrphy_dq_i_data0[5]),
+ .Q4(soc_a7ddrphy_dq_i_data0[4]),
+ .Q5(soc_a7ddrphy_dq_i_data0[3]),
+ .Q6(soc_a7ddrphy_dq_i_data0[2]),
+ .Q7(soc_a7ddrphy_dq_i_data0[1]),
+ .Q8(soc_a7ddrphy_dq_i_data0[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_2 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay0),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed0)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed0)
);
IOBUF IOBUF(
- .I(a7ddrphy_dq_o_nodelay0),
- .T(a7ddrphy_dq_t0),
+ .I(soc_a7ddrphy_dq_o_nodelay0),
+ .T(soc_a7ddrphy_dq_t0),
.IO(ddram_dq[0]),
- .O(a7ddrphy_dq_i_nodelay0)
+ .O(soc_a7ddrphy_dq_i_nodelay0)
);
OSERDESE2 #(
) OSERDESE2_30 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[1]),
- .D2(a7ddrphy_dfi_p0_wrdata[17]),
- .D3(a7ddrphy_dfi_p1_wrdata[1]),
- .D4(a7ddrphy_dfi_p1_wrdata[17]),
- .D5(a7ddrphy_dfi_p2_wrdata[1]),
- .D6(a7ddrphy_dfi_p2_wrdata[17]),
- .D7(a7ddrphy_dfi_p3_wrdata[1]),
- .D8(a7ddrphy_dfi_p3_wrdata[17]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay1),
- .TQ(a7ddrphy_dq_t1)
+ .OQ(soc_a7ddrphy_dq_o_nodelay1),
+ .TQ(soc_a7ddrphy_dq_t1)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed1),
+ .DDLY(soc_a7ddrphy_dq_i_delayed1),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data1[7]),
- .Q2(a7ddrphy_dq_i_data1[6]),
- .Q3(a7ddrphy_dq_i_data1[5]),
- .Q4(a7ddrphy_dq_i_data1[4]),
- .Q5(a7ddrphy_dq_i_data1[3]),
- .Q6(a7ddrphy_dq_i_data1[2]),
- .Q7(a7ddrphy_dq_i_data1[1]),
- .Q8(a7ddrphy_dq_i_data1[0])
+ .Q1(soc_a7ddrphy_dq_i_data1[7]),
+ .Q2(soc_a7ddrphy_dq_i_data1[6]),
+ .Q3(soc_a7ddrphy_dq_i_data1[5]),
+ .Q4(soc_a7ddrphy_dq_i_data1[4]),
+ .Q5(soc_a7ddrphy_dq_i_data1[3]),
+ .Q6(soc_a7ddrphy_dq_i_data1[2]),
+ .Q7(soc_a7ddrphy_dq_i_data1[1]),
+ .Q8(soc_a7ddrphy_dq_i_data1[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_3 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay1),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed1)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed1)
);
IOBUF IOBUF_1(
- .I(a7ddrphy_dq_o_nodelay1),
- .T(a7ddrphy_dq_t1),
+ .I(soc_a7ddrphy_dq_o_nodelay1),
+ .T(soc_a7ddrphy_dq_t1),
.IO(ddram_dq[1]),
- .O(a7ddrphy_dq_i_nodelay1)
+ .O(soc_a7ddrphy_dq_i_nodelay1)
);
OSERDESE2 #(
) OSERDESE2_31 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[2]),
- .D2(a7ddrphy_dfi_p0_wrdata[18]),
- .D3(a7ddrphy_dfi_p1_wrdata[2]),
- .D4(a7ddrphy_dfi_p1_wrdata[18]),
- .D5(a7ddrphy_dfi_p2_wrdata[2]),
- .D6(a7ddrphy_dfi_p2_wrdata[18]),
- .D7(a7ddrphy_dfi_p3_wrdata[2]),
- .D8(a7ddrphy_dfi_p3_wrdata[18]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay2),
- .TQ(a7ddrphy_dq_t2)
+ .OQ(soc_a7ddrphy_dq_o_nodelay2),
+ .TQ(soc_a7ddrphy_dq_t2)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed2),
+ .DDLY(soc_a7ddrphy_dq_i_delayed2),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data2[7]),
- .Q2(a7ddrphy_dq_i_data2[6]),
- .Q3(a7ddrphy_dq_i_data2[5]),
- .Q4(a7ddrphy_dq_i_data2[4]),
- .Q5(a7ddrphy_dq_i_data2[3]),
- .Q6(a7ddrphy_dq_i_data2[2]),
- .Q7(a7ddrphy_dq_i_data2[1]),
- .Q8(a7ddrphy_dq_i_data2[0])
+ .Q1(soc_a7ddrphy_dq_i_data2[7]),
+ .Q2(soc_a7ddrphy_dq_i_data2[6]),
+ .Q3(soc_a7ddrphy_dq_i_data2[5]),
+ .Q4(soc_a7ddrphy_dq_i_data2[4]),
+ .Q5(soc_a7ddrphy_dq_i_data2[3]),
+ .Q6(soc_a7ddrphy_dq_i_data2[2]),
+ .Q7(soc_a7ddrphy_dq_i_data2[1]),
+ .Q8(soc_a7ddrphy_dq_i_data2[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_4 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay2),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed2)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed2)
);
IOBUF IOBUF_2(
- .I(a7ddrphy_dq_o_nodelay2),
- .T(a7ddrphy_dq_t2),
+ .I(soc_a7ddrphy_dq_o_nodelay2),
+ .T(soc_a7ddrphy_dq_t2),
.IO(ddram_dq[2]),
- .O(a7ddrphy_dq_i_nodelay2)
+ .O(soc_a7ddrphy_dq_i_nodelay2)
);
OSERDESE2 #(
) OSERDESE2_32 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[3]),
- .D2(a7ddrphy_dfi_p0_wrdata[19]),
- .D3(a7ddrphy_dfi_p1_wrdata[3]),
- .D4(a7ddrphy_dfi_p1_wrdata[19]),
- .D5(a7ddrphy_dfi_p2_wrdata[3]),
- .D6(a7ddrphy_dfi_p2_wrdata[19]),
- .D7(a7ddrphy_dfi_p3_wrdata[3]),
- .D8(a7ddrphy_dfi_p3_wrdata[19]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay3),
- .TQ(a7ddrphy_dq_t3)
+ .OQ(soc_a7ddrphy_dq_o_nodelay3),
+ .TQ(soc_a7ddrphy_dq_t3)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed3),
+ .DDLY(soc_a7ddrphy_dq_i_delayed3),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data3[7]),
- .Q2(a7ddrphy_dq_i_data3[6]),
- .Q3(a7ddrphy_dq_i_data3[5]),
- .Q4(a7ddrphy_dq_i_data3[4]),
- .Q5(a7ddrphy_dq_i_data3[3]),
- .Q6(a7ddrphy_dq_i_data3[2]),
- .Q7(a7ddrphy_dq_i_data3[1]),
- .Q8(a7ddrphy_dq_i_data3[0])
+ .Q1(soc_a7ddrphy_dq_i_data3[7]),
+ .Q2(soc_a7ddrphy_dq_i_data3[6]),
+ .Q3(soc_a7ddrphy_dq_i_data3[5]),
+ .Q4(soc_a7ddrphy_dq_i_data3[4]),
+ .Q5(soc_a7ddrphy_dq_i_data3[3]),
+ .Q6(soc_a7ddrphy_dq_i_data3[2]),
+ .Q7(soc_a7ddrphy_dq_i_data3[1]),
+ .Q8(soc_a7ddrphy_dq_i_data3[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_5 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay3),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed3)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed3)
);
IOBUF IOBUF_3(
- .I(a7ddrphy_dq_o_nodelay3),
- .T(a7ddrphy_dq_t3),
+ .I(soc_a7ddrphy_dq_o_nodelay3),
+ .T(soc_a7ddrphy_dq_t3),
.IO(ddram_dq[3]),
- .O(a7ddrphy_dq_i_nodelay3)
+ .O(soc_a7ddrphy_dq_i_nodelay3)
);
OSERDESE2 #(
) OSERDESE2_33 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[4]),
- .D2(a7ddrphy_dfi_p0_wrdata[20]),
- .D3(a7ddrphy_dfi_p1_wrdata[4]),
- .D4(a7ddrphy_dfi_p1_wrdata[20]),
- .D5(a7ddrphy_dfi_p2_wrdata[4]),
- .D6(a7ddrphy_dfi_p2_wrdata[20]),
- .D7(a7ddrphy_dfi_p3_wrdata[4]),
- .D8(a7ddrphy_dfi_p3_wrdata[20]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay4),
- .TQ(a7ddrphy_dq_t4)
+ .OQ(soc_a7ddrphy_dq_o_nodelay4),
+ .TQ(soc_a7ddrphy_dq_t4)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed4),
+ .DDLY(soc_a7ddrphy_dq_i_delayed4),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data4[7]),
- .Q2(a7ddrphy_dq_i_data4[6]),
- .Q3(a7ddrphy_dq_i_data4[5]),
- .Q4(a7ddrphy_dq_i_data4[4]),
- .Q5(a7ddrphy_dq_i_data4[3]),
- .Q6(a7ddrphy_dq_i_data4[2]),
- .Q7(a7ddrphy_dq_i_data4[1]),
- .Q8(a7ddrphy_dq_i_data4[0])
+ .Q1(soc_a7ddrphy_dq_i_data4[7]),
+ .Q2(soc_a7ddrphy_dq_i_data4[6]),
+ .Q3(soc_a7ddrphy_dq_i_data4[5]),
+ .Q4(soc_a7ddrphy_dq_i_data4[4]),
+ .Q5(soc_a7ddrphy_dq_i_data4[3]),
+ .Q6(soc_a7ddrphy_dq_i_data4[2]),
+ .Q7(soc_a7ddrphy_dq_i_data4[1]),
+ .Q8(soc_a7ddrphy_dq_i_data4[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_6 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay4),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed4)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed4)
);
IOBUF IOBUF_4(
- .I(a7ddrphy_dq_o_nodelay4),
- .T(a7ddrphy_dq_t4),
+ .I(soc_a7ddrphy_dq_o_nodelay4),
+ .T(soc_a7ddrphy_dq_t4),
.IO(ddram_dq[4]),
- .O(a7ddrphy_dq_i_nodelay4)
+ .O(soc_a7ddrphy_dq_i_nodelay4)
);
OSERDESE2 #(
) OSERDESE2_34 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[5]),
- .D2(a7ddrphy_dfi_p0_wrdata[21]),
- .D3(a7ddrphy_dfi_p1_wrdata[5]),
- .D4(a7ddrphy_dfi_p1_wrdata[21]),
- .D5(a7ddrphy_dfi_p2_wrdata[5]),
- .D6(a7ddrphy_dfi_p2_wrdata[21]),
- .D7(a7ddrphy_dfi_p3_wrdata[5]),
- .D8(a7ddrphy_dfi_p3_wrdata[21]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay5),
- .TQ(a7ddrphy_dq_t5)
+ .OQ(soc_a7ddrphy_dq_o_nodelay5),
+ .TQ(soc_a7ddrphy_dq_t5)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed5),
+ .DDLY(soc_a7ddrphy_dq_i_delayed5),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data5[7]),
- .Q2(a7ddrphy_dq_i_data5[6]),
- .Q3(a7ddrphy_dq_i_data5[5]),
- .Q4(a7ddrphy_dq_i_data5[4]),
- .Q5(a7ddrphy_dq_i_data5[3]),
- .Q6(a7ddrphy_dq_i_data5[2]),
- .Q7(a7ddrphy_dq_i_data5[1]),
- .Q8(a7ddrphy_dq_i_data5[0])
+ .Q1(soc_a7ddrphy_dq_i_data5[7]),
+ .Q2(soc_a7ddrphy_dq_i_data5[6]),
+ .Q3(soc_a7ddrphy_dq_i_data5[5]),
+ .Q4(soc_a7ddrphy_dq_i_data5[4]),
+ .Q5(soc_a7ddrphy_dq_i_data5[3]),
+ .Q6(soc_a7ddrphy_dq_i_data5[2]),
+ .Q7(soc_a7ddrphy_dq_i_data5[1]),
+ .Q8(soc_a7ddrphy_dq_i_data5[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_7 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay5),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed5)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed5)
);
IOBUF IOBUF_5(
- .I(a7ddrphy_dq_o_nodelay5),
- .T(a7ddrphy_dq_t5),
+ .I(soc_a7ddrphy_dq_o_nodelay5),
+ .T(soc_a7ddrphy_dq_t5),
.IO(ddram_dq[5]),
- .O(a7ddrphy_dq_i_nodelay5)
+ .O(soc_a7ddrphy_dq_i_nodelay5)
);
OSERDESE2 #(
) OSERDESE2_35 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[6]),
- .D2(a7ddrphy_dfi_p0_wrdata[22]),
- .D3(a7ddrphy_dfi_p1_wrdata[6]),
- .D4(a7ddrphy_dfi_p1_wrdata[22]),
- .D5(a7ddrphy_dfi_p2_wrdata[6]),
- .D6(a7ddrphy_dfi_p2_wrdata[22]),
- .D7(a7ddrphy_dfi_p3_wrdata[6]),
- .D8(a7ddrphy_dfi_p3_wrdata[22]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay6),
- .TQ(a7ddrphy_dq_t6)
+ .OQ(soc_a7ddrphy_dq_o_nodelay6),
+ .TQ(soc_a7ddrphy_dq_t6)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed6),
+ .DDLY(soc_a7ddrphy_dq_i_delayed6),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data6[7]),
- .Q2(a7ddrphy_dq_i_data6[6]),
- .Q3(a7ddrphy_dq_i_data6[5]),
- .Q4(a7ddrphy_dq_i_data6[4]),
- .Q5(a7ddrphy_dq_i_data6[3]),
- .Q6(a7ddrphy_dq_i_data6[2]),
- .Q7(a7ddrphy_dq_i_data6[1]),
- .Q8(a7ddrphy_dq_i_data6[0])
+ .Q1(soc_a7ddrphy_dq_i_data6[7]),
+ .Q2(soc_a7ddrphy_dq_i_data6[6]),
+ .Q3(soc_a7ddrphy_dq_i_data6[5]),
+ .Q4(soc_a7ddrphy_dq_i_data6[4]),
+ .Q5(soc_a7ddrphy_dq_i_data6[3]),
+ .Q6(soc_a7ddrphy_dq_i_data6[2]),
+ .Q7(soc_a7ddrphy_dq_i_data6[1]),
+ .Q8(soc_a7ddrphy_dq_i_data6[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_8 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay6),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed6)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed6)
);
IOBUF IOBUF_6(
- .I(a7ddrphy_dq_o_nodelay6),
- .T(a7ddrphy_dq_t6),
+ .I(soc_a7ddrphy_dq_o_nodelay6),
+ .T(soc_a7ddrphy_dq_t6),
.IO(ddram_dq[6]),
- .O(a7ddrphy_dq_i_nodelay6)
+ .O(soc_a7ddrphy_dq_i_nodelay6)
);
OSERDESE2 #(
) OSERDESE2_36 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[7]),
- .D2(a7ddrphy_dfi_p0_wrdata[23]),
- .D3(a7ddrphy_dfi_p1_wrdata[7]),
- .D4(a7ddrphy_dfi_p1_wrdata[23]),
- .D5(a7ddrphy_dfi_p2_wrdata[7]),
- .D6(a7ddrphy_dfi_p2_wrdata[23]),
- .D7(a7ddrphy_dfi_p3_wrdata[7]),
- .D8(a7ddrphy_dfi_p3_wrdata[23]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay7),
- .TQ(a7ddrphy_dq_t7)
+ .OQ(soc_a7ddrphy_dq_o_nodelay7),
+ .TQ(soc_a7ddrphy_dq_t7)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed7),
+ .DDLY(soc_a7ddrphy_dq_i_delayed7),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data7[7]),
- .Q2(a7ddrphy_dq_i_data7[6]),
- .Q3(a7ddrphy_dq_i_data7[5]),
- .Q4(a7ddrphy_dq_i_data7[4]),
- .Q5(a7ddrphy_dq_i_data7[3]),
- .Q6(a7ddrphy_dq_i_data7[2]),
- .Q7(a7ddrphy_dq_i_data7[1]),
- .Q8(a7ddrphy_dq_i_data7[0])
+ .Q1(soc_a7ddrphy_dq_i_data7[7]),
+ .Q2(soc_a7ddrphy_dq_i_data7[6]),
+ .Q3(soc_a7ddrphy_dq_i_data7[5]),
+ .Q4(soc_a7ddrphy_dq_i_data7[4]),
+ .Q5(soc_a7ddrphy_dq_i_data7[3]),
+ .Q6(soc_a7ddrphy_dq_i_data7[2]),
+ .Q7(soc_a7ddrphy_dq_i_data7[1]),
+ .Q8(soc_a7ddrphy_dq_i_data7[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_9 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay7),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed7)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed7)
);
IOBUF IOBUF_7(
- .I(a7ddrphy_dq_o_nodelay7),
- .T(a7ddrphy_dq_t7),
+ .I(soc_a7ddrphy_dq_o_nodelay7),
+ .T(soc_a7ddrphy_dq_t7),
.IO(ddram_dq[7]),
- .O(a7ddrphy_dq_i_nodelay7)
+ .O(soc_a7ddrphy_dq_i_nodelay7)
);
OSERDESE2 #(
) OSERDESE2_37 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[8]),
- .D2(a7ddrphy_dfi_p0_wrdata[24]),
- .D3(a7ddrphy_dfi_p1_wrdata[8]),
- .D4(a7ddrphy_dfi_p1_wrdata[24]),
- .D5(a7ddrphy_dfi_p2_wrdata[8]),
- .D6(a7ddrphy_dfi_p2_wrdata[24]),
- .D7(a7ddrphy_dfi_p3_wrdata[8]),
- .D8(a7ddrphy_dfi_p3_wrdata[24]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay8),
- .TQ(a7ddrphy_dq_t8)
+ .OQ(soc_a7ddrphy_dq_o_nodelay8),
+ .TQ(soc_a7ddrphy_dq_t8)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed8),
+ .DDLY(soc_a7ddrphy_dq_i_delayed8),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data8[7]),
- .Q2(a7ddrphy_dq_i_data8[6]),
- .Q3(a7ddrphy_dq_i_data8[5]),
- .Q4(a7ddrphy_dq_i_data8[4]),
- .Q5(a7ddrphy_dq_i_data8[3]),
- .Q6(a7ddrphy_dq_i_data8[2]),
- .Q7(a7ddrphy_dq_i_data8[1]),
- .Q8(a7ddrphy_dq_i_data8[0])
+ .Q1(soc_a7ddrphy_dq_i_data8[7]),
+ .Q2(soc_a7ddrphy_dq_i_data8[6]),
+ .Q3(soc_a7ddrphy_dq_i_data8[5]),
+ .Q4(soc_a7ddrphy_dq_i_data8[4]),
+ .Q5(soc_a7ddrphy_dq_i_data8[3]),
+ .Q6(soc_a7ddrphy_dq_i_data8[2]),
+ .Q7(soc_a7ddrphy_dq_i_data8[1]),
+ .Q8(soc_a7ddrphy_dq_i_data8[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_10 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay8),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed8)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed8)
);
IOBUF IOBUF_8(
- .I(a7ddrphy_dq_o_nodelay8),
- .T(a7ddrphy_dq_t8),
+ .I(soc_a7ddrphy_dq_o_nodelay8),
+ .T(soc_a7ddrphy_dq_t8),
.IO(ddram_dq[8]),
- .O(a7ddrphy_dq_i_nodelay8)
+ .O(soc_a7ddrphy_dq_i_nodelay8)
);
OSERDESE2 #(
) OSERDESE2_38 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[9]),
- .D2(a7ddrphy_dfi_p0_wrdata[25]),
- .D3(a7ddrphy_dfi_p1_wrdata[9]),
- .D4(a7ddrphy_dfi_p1_wrdata[25]),
- .D5(a7ddrphy_dfi_p2_wrdata[9]),
- .D6(a7ddrphy_dfi_p2_wrdata[25]),
- .D7(a7ddrphy_dfi_p3_wrdata[9]),
- .D8(a7ddrphy_dfi_p3_wrdata[25]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay9),
- .TQ(a7ddrphy_dq_t9)
+ .OQ(soc_a7ddrphy_dq_o_nodelay9),
+ .TQ(soc_a7ddrphy_dq_t9)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed9),
+ .DDLY(soc_a7ddrphy_dq_i_delayed9),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data9[7]),
- .Q2(a7ddrphy_dq_i_data9[6]),
- .Q3(a7ddrphy_dq_i_data9[5]),
- .Q4(a7ddrphy_dq_i_data9[4]),
- .Q5(a7ddrphy_dq_i_data9[3]),
- .Q6(a7ddrphy_dq_i_data9[2]),
- .Q7(a7ddrphy_dq_i_data9[1]),
- .Q8(a7ddrphy_dq_i_data9[0])
+ .Q1(soc_a7ddrphy_dq_i_data9[7]),
+ .Q2(soc_a7ddrphy_dq_i_data9[6]),
+ .Q3(soc_a7ddrphy_dq_i_data9[5]),
+ .Q4(soc_a7ddrphy_dq_i_data9[4]),
+ .Q5(soc_a7ddrphy_dq_i_data9[3]),
+ .Q6(soc_a7ddrphy_dq_i_data9[2]),
+ .Q7(soc_a7ddrphy_dq_i_data9[1]),
+ .Q8(soc_a7ddrphy_dq_i_data9[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_11 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay9),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed9)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed9)
);
IOBUF IOBUF_9(
- .I(a7ddrphy_dq_o_nodelay9),
- .T(a7ddrphy_dq_t9),
+ .I(soc_a7ddrphy_dq_o_nodelay9),
+ .T(soc_a7ddrphy_dq_t9),
.IO(ddram_dq[9]),
- .O(a7ddrphy_dq_i_nodelay9)
+ .O(soc_a7ddrphy_dq_i_nodelay9)
);
OSERDESE2 #(
) OSERDESE2_39 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[10]),
- .D2(a7ddrphy_dfi_p0_wrdata[26]),
- .D3(a7ddrphy_dfi_p1_wrdata[10]),
- .D4(a7ddrphy_dfi_p1_wrdata[26]),
- .D5(a7ddrphy_dfi_p2_wrdata[10]),
- .D6(a7ddrphy_dfi_p2_wrdata[26]),
- .D7(a7ddrphy_dfi_p3_wrdata[10]),
- .D8(a7ddrphy_dfi_p3_wrdata[26]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay10),
- .TQ(a7ddrphy_dq_t10)
+ .OQ(soc_a7ddrphy_dq_o_nodelay10),
+ .TQ(soc_a7ddrphy_dq_t10)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed10),
+ .DDLY(soc_a7ddrphy_dq_i_delayed10),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data10[7]),
- .Q2(a7ddrphy_dq_i_data10[6]),
- .Q3(a7ddrphy_dq_i_data10[5]),
- .Q4(a7ddrphy_dq_i_data10[4]),
- .Q5(a7ddrphy_dq_i_data10[3]),
- .Q6(a7ddrphy_dq_i_data10[2]),
- .Q7(a7ddrphy_dq_i_data10[1]),
- .Q8(a7ddrphy_dq_i_data10[0])
+ .Q1(soc_a7ddrphy_dq_i_data10[7]),
+ .Q2(soc_a7ddrphy_dq_i_data10[6]),
+ .Q3(soc_a7ddrphy_dq_i_data10[5]),
+ .Q4(soc_a7ddrphy_dq_i_data10[4]),
+ .Q5(soc_a7ddrphy_dq_i_data10[3]),
+ .Q6(soc_a7ddrphy_dq_i_data10[2]),
+ .Q7(soc_a7ddrphy_dq_i_data10[1]),
+ .Q8(soc_a7ddrphy_dq_i_data10[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_12 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay10),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed10)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed10)
);
IOBUF IOBUF_10(
- .I(a7ddrphy_dq_o_nodelay10),
- .T(a7ddrphy_dq_t10),
+ .I(soc_a7ddrphy_dq_o_nodelay10),
+ .T(soc_a7ddrphy_dq_t10),
.IO(ddram_dq[10]),
- .O(a7ddrphy_dq_i_nodelay10)
+ .O(soc_a7ddrphy_dq_i_nodelay10)
);
OSERDESE2 #(
) OSERDESE2_40 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[11]),
- .D2(a7ddrphy_dfi_p0_wrdata[27]),
- .D3(a7ddrphy_dfi_p1_wrdata[11]),
- .D4(a7ddrphy_dfi_p1_wrdata[27]),
- .D5(a7ddrphy_dfi_p2_wrdata[11]),
- .D6(a7ddrphy_dfi_p2_wrdata[27]),
- .D7(a7ddrphy_dfi_p3_wrdata[11]),
- .D8(a7ddrphy_dfi_p3_wrdata[27]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay11),
- .TQ(a7ddrphy_dq_t11)
+ .OQ(soc_a7ddrphy_dq_o_nodelay11),
+ .TQ(soc_a7ddrphy_dq_t11)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed11),
+ .DDLY(soc_a7ddrphy_dq_i_delayed11),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data11[7]),
- .Q2(a7ddrphy_dq_i_data11[6]),
- .Q3(a7ddrphy_dq_i_data11[5]),
- .Q4(a7ddrphy_dq_i_data11[4]),
- .Q5(a7ddrphy_dq_i_data11[3]),
- .Q6(a7ddrphy_dq_i_data11[2]),
- .Q7(a7ddrphy_dq_i_data11[1]),
- .Q8(a7ddrphy_dq_i_data11[0])
+ .Q1(soc_a7ddrphy_dq_i_data11[7]),
+ .Q2(soc_a7ddrphy_dq_i_data11[6]),
+ .Q3(soc_a7ddrphy_dq_i_data11[5]),
+ .Q4(soc_a7ddrphy_dq_i_data11[4]),
+ .Q5(soc_a7ddrphy_dq_i_data11[3]),
+ .Q6(soc_a7ddrphy_dq_i_data11[2]),
+ .Q7(soc_a7ddrphy_dq_i_data11[1]),
+ .Q8(soc_a7ddrphy_dq_i_data11[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_13 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay11),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed11)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed11)
);
IOBUF IOBUF_11(
- .I(a7ddrphy_dq_o_nodelay11),
- .T(a7ddrphy_dq_t11),
+ .I(soc_a7ddrphy_dq_o_nodelay11),
+ .T(soc_a7ddrphy_dq_t11),
.IO(ddram_dq[11]),
- .O(a7ddrphy_dq_i_nodelay11)
+ .O(soc_a7ddrphy_dq_i_nodelay11)
);
OSERDESE2 #(
) OSERDESE2_41 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[12]),
- .D2(a7ddrphy_dfi_p0_wrdata[28]),
- .D3(a7ddrphy_dfi_p1_wrdata[12]),
- .D4(a7ddrphy_dfi_p1_wrdata[28]),
- .D5(a7ddrphy_dfi_p2_wrdata[12]),
- .D6(a7ddrphy_dfi_p2_wrdata[28]),
- .D7(a7ddrphy_dfi_p3_wrdata[12]),
- .D8(a7ddrphy_dfi_p3_wrdata[28]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay12),
- .TQ(a7ddrphy_dq_t12)
+ .OQ(soc_a7ddrphy_dq_o_nodelay12),
+ .TQ(soc_a7ddrphy_dq_t12)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed12),
+ .DDLY(soc_a7ddrphy_dq_i_delayed12),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data12[7]),
- .Q2(a7ddrphy_dq_i_data12[6]),
- .Q3(a7ddrphy_dq_i_data12[5]),
- .Q4(a7ddrphy_dq_i_data12[4]),
- .Q5(a7ddrphy_dq_i_data12[3]),
- .Q6(a7ddrphy_dq_i_data12[2]),
- .Q7(a7ddrphy_dq_i_data12[1]),
- .Q8(a7ddrphy_dq_i_data12[0])
+ .Q1(soc_a7ddrphy_dq_i_data12[7]),
+ .Q2(soc_a7ddrphy_dq_i_data12[6]),
+ .Q3(soc_a7ddrphy_dq_i_data12[5]),
+ .Q4(soc_a7ddrphy_dq_i_data12[4]),
+ .Q5(soc_a7ddrphy_dq_i_data12[3]),
+ .Q6(soc_a7ddrphy_dq_i_data12[2]),
+ .Q7(soc_a7ddrphy_dq_i_data12[1]),
+ .Q8(soc_a7ddrphy_dq_i_data12[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_14 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay12),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed12)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed12)
);
IOBUF IOBUF_12(
- .I(a7ddrphy_dq_o_nodelay12),
- .T(a7ddrphy_dq_t12),
+ .I(soc_a7ddrphy_dq_o_nodelay12),
+ .T(soc_a7ddrphy_dq_t12),
.IO(ddram_dq[12]),
- .O(a7ddrphy_dq_i_nodelay12)
+ .O(soc_a7ddrphy_dq_i_nodelay12)
);
OSERDESE2 #(
) OSERDESE2_42 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[13]),
- .D2(a7ddrphy_dfi_p0_wrdata[29]),
- .D3(a7ddrphy_dfi_p1_wrdata[13]),
- .D4(a7ddrphy_dfi_p1_wrdata[29]),
- .D5(a7ddrphy_dfi_p2_wrdata[13]),
- .D6(a7ddrphy_dfi_p2_wrdata[29]),
- .D7(a7ddrphy_dfi_p3_wrdata[13]),
- .D8(a7ddrphy_dfi_p3_wrdata[29]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay13),
- .TQ(a7ddrphy_dq_t13)
+ .OQ(soc_a7ddrphy_dq_o_nodelay13),
+ .TQ(soc_a7ddrphy_dq_t13)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed13),
+ .DDLY(soc_a7ddrphy_dq_i_delayed13),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data13[7]),
- .Q2(a7ddrphy_dq_i_data13[6]),
- .Q3(a7ddrphy_dq_i_data13[5]),
- .Q4(a7ddrphy_dq_i_data13[4]),
- .Q5(a7ddrphy_dq_i_data13[3]),
- .Q6(a7ddrphy_dq_i_data13[2]),
- .Q7(a7ddrphy_dq_i_data13[1]),
- .Q8(a7ddrphy_dq_i_data13[0])
+ .Q1(soc_a7ddrphy_dq_i_data13[7]),
+ .Q2(soc_a7ddrphy_dq_i_data13[6]),
+ .Q3(soc_a7ddrphy_dq_i_data13[5]),
+ .Q4(soc_a7ddrphy_dq_i_data13[4]),
+ .Q5(soc_a7ddrphy_dq_i_data13[3]),
+ .Q6(soc_a7ddrphy_dq_i_data13[2]),
+ .Q7(soc_a7ddrphy_dq_i_data13[1]),
+ .Q8(soc_a7ddrphy_dq_i_data13[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_15 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay13),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed13)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed13)
);
IOBUF IOBUF_13(
- .I(a7ddrphy_dq_o_nodelay13),
- .T(a7ddrphy_dq_t13),
+ .I(soc_a7ddrphy_dq_o_nodelay13),
+ .T(soc_a7ddrphy_dq_t13),
.IO(ddram_dq[13]),
- .O(a7ddrphy_dq_i_nodelay13)
+ .O(soc_a7ddrphy_dq_i_nodelay13)
);
OSERDESE2 #(
) OSERDESE2_43 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[14]),
- .D2(a7ddrphy_dfi_p0_wrdata[30]),
- .D3(a7ddrphy_dfi_p1_wrdata[14]),
- .D4(a7ddrphy_dfi_p1_wrdata[30]),
- .D5(a7ddrphy_dfi_p2_wrdata[14]),
- .D6(a7ddrphy_dfi_p2_wrdata[30]),
- .D7(a7ddrphy_dfi_p3_wrdata[14]),
- .D8(a7ddrphy_dfi_p3_wrdata[30]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay14),
- .TQ(a7ddrphy_dq_t14)
+ .OQ(soc_a7ddrphy_dq_o_nodelay14),
+ .TQ(soc_a7ddrphy_dq_t14)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed14),
+ .DDLY(soc_a7ddrphy_dq_i_delayed14),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data14[7]),
- .Q2(a7ddrphy_dq_i_data14[6]),
- .Q3(a7ddrphy_dq_i_data14[5]),
- .Q4(a7ddrphy_dq_i_data14[4]),
- .Q5(a7ddrphy_dq_i_data14[3]),
- .Q6(a7ddrphy_dq_i_data14[2]),
- .Q7(a7ddrphy_dq_i_data14[1]),
- .Q8(a7ddrphy_dq_i_data14[0])
+ .Q1(soc_a7ddrphy_dq_i_data14[7]),
+ .Q2(soc_a7ddrphy_dq_i_data14[6]),
+ .Q3(soc_a7ddrphy_dq_i_data14[5]),
+ .Q4(soc_a7ddrphy_dq_i_data14[4]),
+ .Q5(soc_a7ddrphy_dq_i_data14[3]),
+ .Q6(soc_a7ddrphy_dq_i_data14[2]),
+ .Q7(soc_a7ddrphy_dq_i_data14[1]),
+ .Q8(soc_a7ddrphy_dq_i_data14[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_16 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay14),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed14)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed14)
);
IOBUF IOBUF_14(
- .I(a7ddrphy_dq_o_nodelay14),
- .T(a7ddrphy_dq_t14),
+ .I(soc_a7ddrphy_dq_o_nodelay14),
+ .T(soc_a7ddrphy_dq_t14),
.IO(ddram_dq[14]),
- .O(a7ddrphy_dq_i_nodelay14)
+ .O(soc_a7ddrphy_dq_i_nodelay14)
);
OSERDESE2 #(
) OSERDESE2_44 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[15]),
- .D2(a7ddrphy_dfi_p0_wrdata[31]),
- .D3(a7ddrphy_dfi_p1_wrdata[15]),
- .D4(a7ddrphy_dfi_p1_wrdata[31]),
- .D5(a7ddrphy_dfi_p2_wrdata[15]),
- .D6(a7ddrphy_dfi_p2_wrdata[31]),
- .D7(a7ddrphy_dfi_p3_wrdata[15]),
- .D8(a7ddrphy_dfi_p3_wrdata[31]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay15),
- .TQ(a7ddrphy_dq_t15)
+ .OQ(soc_a7ddrphy_dq_o_nodelay15),
+ .TQ(soc_a7ddrphy_dq_t15)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed15),
+ .DDLY(soc_a7ddrphy_dq_i_delayed15),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data15[7]),
- .Q2(a7ddrphy_dq_i_data15[6]),
- .Q3(a7ddrphy_dq_i_data15[5]),
- .Q4(a7ddrphy_dq_i_data15[4]),
- .Q5(a7ddrphy_dq_i_data15[3]),
- .Q6(a7ddrphy_dq_i_data15[2]),
- .Q7(a7ddrphy_dq_i_data15[1]),
- .Q8(a7ddrphy_dq_i_data15[0])
+ .Q1(soc_a7ddrphy_dq_i_data15[7]),
+ .Q2(soc_a7ddrphy_dq_i_data15[6]),
+ .Q3(soc_a7ddrphy_dq_i_data15[5]),
+ .Q4(soc_a7ddrphy_dq_i_data15[4]),
+ .Q5(soc_a7ddrphy_dq_i_data15[3]),
+ .Q6(soc_a7ddrphy_dq_i_data15[2]),
+ .Q7(soc_a7ddrphy_dq_i_data15[1]),
+ .Q8(soc_a7ddrphy_dq_i_data15[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_17 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay15),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed15)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed15)
);
IOBUF IOBUF_15(
- .I(a7ddrphy_dq_o_nodelay15),
- .T(a7ddrphy_dq_t15),
+ .I(soc_a7ddrphy_dq_o_nodelay15),
+ .T(soc_a7ddrphy_dq_t15),
.IO(ddram_dq[15]),
- .O(a7ddrphy_dq_i_nodelay15)
+ .O(soc_a7ddrphy_dq_i_nodelay15)
);
reg [23:0] storage[0:15];
reg [23:0] memdat;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+ storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+ memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_1[0:15];
reg [23:0] memdat_1;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+ storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_2[0:15];
reg [23:0] memdat_2;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+ storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_3[0:15];
reg [23:0] memdat_3;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+ storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_4[0:15];
reg [23:0] memdat_4;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+ storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_5[0:15];
reg [23:0] memdat_5;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+ storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_6[0:15];
reg [23:0] memdat_6;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+ storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_7[0:15];
reg [23:0] memdat_7;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+ storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
PLLE2_ADV #(
.CLKFBOUT_MULT(5'd16),
.CLKIN1_PERIOD(10.0),
- .CLKOUT0_DIVIDE(5'd16),
+ .CLKOUT0_DIVIDE(4'd8),
.CLKOUT0_PHASE(1'd0),
- .CLKOUT1_DIVIDE(3'd4),
+ .CLKOUT1_DIVIDE(5'd16),
.CLKOUT1_PHASE(1'd0),
.CLKOUT2_DIVIDE(3'd4),
- .CLKOUT2_PHASE(7'd90),
+ .CLKOUT2_PHASE(1'd0),
+ .CLKOUT3_DIVIDE(3'd4),
+ .CLKOUT3_PHASE(7'd90),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
- .CLKFBIN(pll_fb0),
- .CLKIN1(s7pll0_clkin),
- .RST(sys_pll_reset),
- .CLKFBOUT(pll_fb0),
- .CLKOUT0(s7pll0_clkout0),
- .CLKOUT1(s7pll0_clkout1),
- .CLKOUT2(s7pll0_clkout2),
- .LOCKED(sys_pll_locked)
-);
-
-PLLE2_ADV #(
- .CLKFBOUT_MULT(5'd16),
- .CLKIN1_PERIOD(10.0),
- .CLKOUT0_DIVIDE(4'd8),
- .CLKOUT0_PHASE(1'd0),
- .DIVCLK_DIVIDE(1'd1),
- .REF_JITTER1(0.01),
- .STARTUP_WAIT("FALSE")
-) PLLE2_ADV_1 (
- .CLKFBIN(pll_fb1),
- .CLKIN1(s7pll1_clkin),
- .RST(iodelay_pll_reset),
- .CLKFBOUT(pll_fb1),
- .CLKOUT0(s7pll1_clkout),
- .LOCKED(iodelay_pll_locked)
+ .CLKFBIN(vns_pll_fb),
+ .CLKIN1(soc_clkin),
+ .RST(soc_reset),
+ .CLKFBOUT(vns_pll_fb),
+ .CLKOUT0(soc_clkout0),
+ .CLKOUT1(soc_clkout1),
+ .CLKOUT2(soc_clkout2),
+ .CLKOUT3(soc_clkout3),
+ .LOCKED(soc_locked)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE (
- .C(sys_clk),
+ .C(iodelay_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl0),
- .Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_1 (
- .C(sys_clk),
+ .C(iodelay_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl0_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl0),
- .Q(sys_rst)
+ .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(iodelay_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_2 (
- .C(sys4x_clk),
+ .C(sys_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl1),
- .Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_3 (
- .C(sys4x_clk),
+ .C(sys_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl1_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl1),
- .Q(xilinxasyncresetsynchronizerimpl1_expr)
+ .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(sys_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_4 (
- .C(sys4x_dqs_clk),
+ .C(sys4x_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl2),
- .Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_5 (
- .C(sys4x_dqs_clk),
+ .C(sys4x_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl2_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl2),
- .Q(xilinxasyncresetsynchronizerimpl2_expr)
+ .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_expr)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_6 (
- .C(iodelay_clk),
+ .C(sys4x_dqs_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl3),
- .Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_7 (
- .C(iodelay_clk),
+ .C(sys4x_dqs_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl3_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl3),
- .Q(iodelay_rst)
+ .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(vns_xilinxasyncresetsynchronizerimpl3_expr)
);
endmodule
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:52
+// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:04
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
output wire [127:0] user_port_native_0_rdata_data
);
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-wire [31:0] litedramcore_dat_w;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-wire [31:0] litedramcore_wishbone_dat_r;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
+reg [13:0] soc_litedramcore_adr = 14'd0;
+reg soc_litedramcore_we = 1'd0;
+wire [31:0] soc_litedramcore_dat_w;
+wire [31:0] soc_litedramcore_dat_r;
+wire [29:0] soc_litedramcore_wishbone_adr;
+wire [31:0] soc_litedramcore_wishbone_dat_w;
+wire [31:0] soc_litedramcore_wishbone_dat_r;
+wire [3:0] soc_litedramcore_wishbone_sel;
+wire soc_litedramcore_wishbone_cyc;
+wire soc_litedramcore_wishbone_stb;
+reg soc_litedramcore_wishbone_ack = 1'd0;
+wire soc_litedramcore_wishbone_we;
+wire [2:0] soc_litedramcore_wishbone_cti;
+wire [1:0] soc_litedramcore_wishbone_bte;
+reg soc_litedramcore_wishbone_err = 1'd0;
wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire sys4x_dqs_clk;
wire iodelay_clk;
wire iodelay_rst;
-wire sys_pll_reset;
-wire sys_pll_locked;
-wire s7pll0_clkin;
-wire s7pll0_clkout0;
-wire s7pll0_clkout_buf0;
-wire s7pll0_clkout1;
-wire s7pll0_clkout_buf1;
-wire s7pll0_clkout2;
-wire s7pll0_clkout_buf2;
-wire iodelay_pll_reset;
-wire iodelay_pll_locked;
-wire s7pll1_clkin;
-wire s7pll1_clkout;
-wire s7pll1_clkout_buf;
-reg [3:0] reset_counter = 4'd15;
-reg ic_reset = 1'd1;
-reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg a7ddrphy_wlevel_en_storage = 1'd0;
-reg a7ddrphy_wlevel_en_re = 1'd0;
-wire a7ddrphy_wlevel_strobe_re;
-wire a7ddrphy_wlevel_strobe_r;
-wire a7ddrphy_wlevel_strobe_we;
-reg a7ddrphy_wlevel_strobe_w = 1'd0;
-wire a7ddrphy_cdly_rst_re;
-wire a7ddrphy_cdly_rst_r;
-wire a7ddrphy_cdly_rst_we;
-reg a7ddrphy_cdly_rst_w = 1'd0;
-wire a7ddrphy_cdly_inc_re;
-wire a7ddrphy_cdly_inc_r;
-wire a7ddrphy_cdly_inc_we;
-reg a7ddrphy_cdly_inc_w = 1'd0;
-reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg a7ddrphy_dly_sel_re = 1'd0;
-wire a7ddrphy_rdly_dq_rst_re;
-wire a7ddrphy_rdly_dq_rst_r;
-wire a7ddrphy_rdly_dq_rst_we;
-reg a7ddrphy_rdly_dq_rst_w = 1'd0;
-wire a7ddrphy_rdly_dq_inc_re;
-wire a7ddrphy_rdly_dq_inc_r;
-wire a7ddrphy_rdly_dq_inc_we;
-reg a7ddrphy_rdly_dq_inc_w = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_rst_re;
-wire a7ddrphy_rdly_dq_bitslip_rst_r;
-wire a7ddrphy_rdly_dq_bitslip_rst_we;
-reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_re;
-wire a7ddrphy_rdly_dq_bitslip_r;
-wire a7ddrphy_rdly_dq_bitslip_we;
-reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-wire [14:0] a7ddrphy_dfi_p0_address;
-wire [2:0] a7ddrphy_dfi_p0_bank;
-wire a7ddrphy_dfi_p0_cas_n;
-wire a7ddrphy_dfi_p0_cs_n;
-wire a7ddrphy_dfi_p0_ras_n;
-wire a7ddrphy_dfi_p0_we_n;
-wire a7ddrphy_dfi_p0_cke;
-wire a7ddrphy_dfi_p0_odt;
-wire a7ddrphy_dfi_p0_reset_n;
-wire a7ddrphy_dfi_p0_act_n;
-wire [31:0] a7ddrphy_dfi_p0_wrdata;
-wire a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-reg a7ddrphy_dfi_p0_rddata_valid = 1'd0;
-wire [14:0] a7ddrphy_dfi_p1_address;
-wire [2:0] a7ddrphy_dfi_p1_bank;
-wire a7ddrphy_dfi_p1_cas_n;
-wire a7ddrphy_dfi_p1_cs_n;
-wire a7ddrphy_dfi_p1_ras_n;
-wire a7ddrphy_dfi_p1_we_n;
-wire a7ddrphy_dfi_p1_cke;
-wire a7ddrphy_dfi_p1_odt;
-wire a7ddrphy_dfi_p1_reset_n;
-wire a7ddrphy_dfi_p1_act_n;
-wire [31:0] a7ddrphy_dfi_p1_wrdata;
-wire a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-reg a7ddrphy_dfi_p1_rddata_valid = 1'd0;
-wire [14:0] a7ddrphy_dfi_p2_address;
-wire [2:0] a7ddrphy_dfi_p2_bank;
-wire a7ddrphy_dfi_p2_cas_n;
-wire a7ddrphy_dfi_p2_cs_n;
-wire a7ddrphy_dfi_p2_ras_n;
-wire a7ddrphy_dfi_p2_we_n;
-wire a7ddrphy_dfi_p2_cke;
-wire a7ddrphy_dfi_p2_odt;
-wire a7ddrphy_dfi_p2_reset_n;
-wire a7ddrphy_dfi_p2_act_n;
-wire [31:0] a7ddrphy_dfi_p2_wrdata;
-wire a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-reg a7ddrphy_dfi_p2_rddata_valid = 1'd0;
-wire [14:0] a7ddrphy_dfi_p3_address;
-wire [2:0] a7ddrphy_dfi_p3_bank;
-wire a7ddrphy_dfi_p3_cas_n;
-wire a7ddrphy_dfi_p3_cs_n;
-wire a7ddrphy_dfi_p3_ras_n;
-wire a7ddrphy_dfi_p3_we_n;
-wire a7ddrphy_dfi_p3_cke;
-wire a7ddrphy_dfi_p3_odt;
-wire a7ddrphy_dfi_p3_reset_n;
-wire a7ddrphy_dfi_p3_act_n;
-wire [31:0] a7ddrphy_dfi_p3_wrdata;
-wire a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-reg a7ddrphy_dfi_p3_rddata_valid = 1'd0;
-wire a7ddrphy_sd_clk_se_nodelay;
-reg a7ddrphy_dqs_oe = 1'd0;
-reg a7ddrphy_dqs_oe_delayed = 1'd0;
-wire a7ddrphy_dqspattern0;
-wire a7ddrphy_dqspattern1;
-reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire [1:0] a7ddrphy_dqs_i;
-wire [1:0] a7ddrphy_dqs_i_delayed;
-wire a7ddrphy_dqs_o_no_delay0;
-wire a7ddrphy_dqs_t0;
-wire a7ddrphy0;
-wire a7ddrphy_dqs_o_no_delay1;
-wire a7ddrphy_dqs_t1;
-wire a7ddrphy1;
-wire a7ddrphy_dq_oe;
-reg a7ddrphy_dq_oe_delayed = 1'd0;
-wire a7ddrphy_dq_o_nodelay0;
-wire a7ddrphy_dq_i_nodelay0;
-wire a7ddrphy_dq_i_delayed0;
-wire a7ddrphy_dq_t0;
-wire [7:0] a7ddrphy_dq_i_data0;
-wire [7:0] a7ddrphy_bitslip0_i;
-reg [7:0] a7ddrphy_bitslip0_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip0_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip0_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay1;
-wire a7ddrphy_dq_i_nodelay1;
-wire a7ddrphy_dq_i_delayed1;
-wire a7ddrphy_dq_t1;
-wire [7:0] a7ddrphy_dq_i_data1;
-wire [7:0] a7ddrphy_bitslip1_i;
-reg [7:0] a7ddrphy_bitslip1_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip1_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip1_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay2;
-wire a7ddrphy_dq_i_nodelay2;
-wire a7ddrphy_dq_i_delayed2;
-wire a7ddrphy_dq_t2;
-wire [7:0] a7ddrphy_dq_i_data2;
-wire [7:0] a7ddrphy_bitslip2_i;
-reg [7:0] a7ddrphy_bitslip2_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip2_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip2_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay3;
-wire a7ddrphy_dq_i_nodelay3;
-wire a7ddrphy_dq_i_delayed3;
-wire a7ddrphy_dq_t3;
-wire [7:0] a7ddrphy_dq_i_data3;
-wire [7:0] a7ddrphy_bitslip3_i;
-reg [7:0] a7ddrphy_bitslip3_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip3_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip3_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay4;
-wire a7ddrphy_dq_i_nodelay4;
-wire a7ddrphy_dq_i_delayed4;
-wire a7ddrphy_dq_t4;
-wire [7:0] a7ddrphy_dq_i_data4;
-wire [7:0] a7ddrphy_bitslip4_i;
-reg [7:0] a7ddrphy_bitslip4_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip4_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip4_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay5;
-wire a7ddrphy_dq_i_nodelay5;
-wire a7ddrphy_dq_i_delayed5;
-wire a7ddrphy_dq_t5;
-wire [7:0] a7ddrphy_dq_i_data5;
-wire [7:0] a7ddrphy_bitslip5_i;
-reg [7:0] a7ddrphy_bitslip5_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip5_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip5_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay6;
-wire a7ddrphy_dq_i_nodelay6;
-wire a7ddrphy_dq_i_delayed6;
-wire a7ddrphy_dq_t6;
-wire [7:0] a7ddrphy_dq_i_data6;
-wire [7:0] a7ddrphy_bitslip6_i;
-reg [7:0] a7ddrphy_bitslip6_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip6_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip6_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay7;
-wire a7ddrphy_dq_i_nodelay7;
-wire a7ddrphy_dq_i_delayed7;
-wire a7ddrphy_dq_t7;
-wire [7:0] a7ddrphy_dq_i_data7;
-wire [7:0] a7ddrphy_bitslip7_i;
-reg [7:0] a7ddrphy_bitslip7_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip7_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip7_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay8;
-wire a7ddrphy_dq_i_nodelay8;
-wire a7ddrphy_dq_i_delayed8;
-wire a7ddrphy_dq_t8;
-wire [7:0] a7ddrphy_dq_i_data8;
-wire [7:0] a7ddrphy_bitslip8_i;
-reg [7:0] a7ddrphy_bitslip8_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip8_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip8_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay9;
-wire a7ddrphy_dq_i_nodelay9;
-wire a7ddrphy_dq_i_delayed9;
-wire a7ddrphy_dq_t9;
-wire [7:0] a7ddrphy_dq_i_data9;
-wire [7:0] a7ddrphy_bitslip9_i;
-reg [7:0] a7ddrphy_bitslip9_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip9_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip9_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay10;
-wire a7ddrphy_dq_i_nodelay10;
-wire a7ddrphy_dq_i_delayed10;
-wire a7ddrphy_dq_t10;
-wire [7:0] a7ddrphy_dq_i_data10;
-wire [7:0] a7ddrphy_bitslip10_i;
-reg [7:0] a7ddrphy_bitslip10_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip10_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip10_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay11;
-wire a7ddrphy_dq_i_nodelay11;
-wire a7ddrphy_dq_i_delayed11;
-wire a7ddrphy_dq_t11;
-wire [7:0] a7ddrphy_dq_i_data11;
-wire [7:0] a7ddrphy_bitslip11_i;
-reg [7:0] a7ddrphy_bitslip11_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip11_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip11_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay12;
-wire a7ddrphy_dq_i_nodelay12;
-wire a7ddrphy_dq_i_delayed12;
-wire a7ddrphy_dq_t12;
-wire [7:0] a7ddrphy_dq_i_data12;
-wire [7:0] a7ddrphy_bitslip12_i;
-reg [7:0] a7ddrphy_bitslip12_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip12_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip12_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay13;
-wire a7ddrphy_dq_i_nodelay13;
-wire a7ddrphy_dq_i_delayed13;
-wire a7ddrphy_dq_t13;
-wire [7:0] a7ddrphy_dq_i_data13;
-wire [7:0] a7ddrphy_bitslip13_i;
-reg [7:0] a7ddrphy_bitslip13_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip13_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip13_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay14;
-wire a7ddrphy_dq_i_nodelay14;
-wire a7ddrphy_dq_i_delayed14;
-wire a7ddrphy_dq_t14;
-wire [7:0] a7ddrphy_dq_i_data14;
-wire [7:0] a7ddrphy_bitslip14_i;
-reg [7:0] a7ddrphy_bitslip14_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip14_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip14_r = 24'd0;
-wire a7ddrphy_dq_o_nodelay15;
-wire a7ddrphy_dq_i_nodelay15;
-wire a7ddrphy_dq_i_delayed15;
-wire a7ddrphy_dq_t15;
-wire [7:0] a7ddrphy_dq_i_data15;
-wire [7:0] a7ddrphy_bitslip15_i;
-reg [7:0] a7ddrphy_bitslip15_o = 8'd0;
-reg [3:0] a7ddrphy_bitslip15_value = 4'd0;
-reg [23:0] a7ddrphy_bitslip15_r = 24'd0;
-wire [7:0] a7ddrphy_rddata_en;
-reg [7:0] a7ddrphy_rddata_en_last = 8'd0;
-wire [3:0] a7ddrphy_wrdata_en;
-reg [3:0] a7ddrphy_wrdata_en_last = 4'd0;
-wire [14:0] litedramcore_inti_p0_address;
-wire [2:0] litedramcore_inti_p0_bank;
-reg litedramcore_inti_p0_cas_n = 1'd1;
-reg litedramcore_inti_p0_cs_n = 1'd1;
-reg litedramcore_inti_p0_ras_n = 1'd1;
-reg litedramcore_inti_p0_we_n = 1'd1;
-wire litedramcore_inti_p0_cke;
-wire litedramcore_inti_p0_odt;
-wire litedramcore_inti_p0_reset_n;
-reg litedramcore_inti_p0_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p0_wrdata;
-wire litedramcore_inti_p0_wrdata_en;
-wire [3:0] litedramcore_inti_p0_wrdata_mask;
-wire litedramcore_inti_p0_rddata_en;
-reg [31:0] litedramcore_inti_p0_rddata = 32'd0;
-reg litedramcore_inti_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_inti_p1_address;
-wire [2:0] litedramcore_inti_p1_bank;
-reg litedramcore_inti_p1_cas_n = 1'd1;
-reg litedramcore_inti_p1_cs_n = 1'd1;
-reg litedramcore_inti_p1_ras_n = 1'd1;
-reg litedramcore_inti_p1_we_n = 1'd1;
-wire litedramcore_inti_p1_cke;
-wire litedramcore_inti_p1_odt;
-wire litedramcore_inti_p1_reset_n;
-reg litedramcore_inti_p1_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p1_wrdata;
-wire litedramcore_inti_p1_wrdata_en;
-wire [3:0] litedramcore_inti_p1_wrdata_mask;
-wire litedramcore_inti_p1_rddata_en;
-reg [31:0] litedramcore_inti_p1_rddata = 32'd0;
-reg litedramcore_inti_p1_rddata_valid = 1'd0;
-wire [14:0] litedramcore_inti_p2_address;
-wire [2:0] litedramcore_inti_p2_bank;
-reg litedramcore_inti_p2_cas_n = 1'd1;
-reg litedramcore_inti_p2_cs_n = 1'd1;
-reg litedramcore_inti_p2_ras_n = 1'd1;
-reg litedramcore_inti_p2_we_n = 1'd1;
-wire litedramcore_inti_p2_cke;
-wire litedramcore_inti_p2_odt;
-wire litedramcore_inti_p2_reset_n;
-reg litedramcore_inti_p2_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p2_wrdata;
-wire litedramcore_inti_p2_wrdata_en;
-wire [3:0] litedramcore_inti_p2_wrdata_mask;
-wire litedramcore_inti_p2_rddata_en;
-reg [31:0] litedramcore_inti_p2_rddata = 32'd0;
-reg litedramcore_inti_p2_rddata_valid = 1'd0;
-wire [14:0] litedramcore_inti_p3_address;
-wire [2:0] litedramcore_inti_p3_bank;
-reg litedramcore_inti_p3_cas_n = 1'd1;
-reg litedramcore_inti_p3_cs_n = 1'd1;
-reg litedramcore_inti_p3_ras_n = 1'd1;
-reg litedramcore_inti_p3_we_n = 1'd1;
-wire litedramcore_inti_p3_cke;
-wire litedramcore_inti_p3_odt;
-wire litedramcore_inti_p3_reset_n;
-reg litedramcore_inti_p3_act_n = 1'd1;
-wire [31:0] litedramcore_inti_p3_wrdata;
-wire litedramcore_inti_p3_wrdata_en;
-wire [3:0] litedramcore_inti_p3_wrdata_mask;
-wire litedramcore_inti_p3_rddata_en;
-reg [31:0] litedramcore_inti_p3_rddata = 32'd0;
-reg litedramcore_inti_p3_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [31:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [3:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [31:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [3:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p2_address;
-wire [2:0] litedramcore_slave_p2_bank;
-wire litedramcore_slave_p2_cas_n;
-wire litedramcore_slave_p2_cs_n;
-wire litedramcore_slave_p2_ras_n;
-wire litedramcore_slave_p2_we_n;
-wire litedramcore_slave_p2_cke;
-wire litedramcore_slave_p2_odt;
-wire litedramcore_slave_p2_reset_n;
-wire litedramcore_slave_p2_act_n;
-wire [31:0] litedramcore_slave_p2_wrdata;
-wire litedramcore_slave_p2_wrdata_en;
-wire [3:0] litedramcore_slave_p2_wrdata_mask;
-wire litedramcore_slave_p2_rddata_en;
-reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p3_address;
-wire [2:0] litedramcore_slave_p3_bank;
-wire litedramcore_slave_p3_cas_n;
-wire litedramcore_slave_p3_cs_n;
-wire litedramcore_slave_p3_ras_n;
-wire litedramcore_slave_p3_we_n;
-wire litedramcore_slave_p3_cke;
-wire litedramcore_slave_p3_odt;
-wire litedramcore_slave_p3_reset_n;
-wire litedramcore_slave_p3_act_n;
-wire [31:0] litedramcore_slave_p3_wrdata;
-wire litedramcore_slave_p3_wrdata_en;
-wire [3:0] litedramcore_slave_p3_wrdata_mask;
-wire litedramcore_slave_p3_rddata_en;
-reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [14:0] litedramcore_master_p0_address = 15'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [14:0] litedramcore_master_p1_address = 15'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-reg [14:0] litedramcore_master_p2_address = 15'd0;
-reg [2:0] litedramcore_master_p2_bank = 3'd0;
-reg litedramcore_master_p2_cas_n = 1'd1;
-reg litedramcore_master_p2_cs_n = 1'd1;
-reg litedramcore_master_p2_ras_n = 1'd1;
-reg litedramcore_master_p2_we_n = 1'd1;
-reg litedramcore_master_p2_cke = 1'd0;
-reg litedramcore_master_p2_odt = 1'd0;
-reg litedramcore_master_p2_reset_n = 1'd0;
-reg litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p2_rddata;
-wire litedramcore_master_p2_rddata_valid;
-reg [14:0] litedramcore_master_p3_address = 15'd0;
-reg [2:0] litedramcore_master_p3_bank = 3'd0;
-reg litedramcore_master_p3_cas_n = 1'd1;
-reg litedramcore_master_p3_cs_n = 1'd1;
-reg litedramcore_master_p3_ras_n = 1'd1;
-reg litedramcore_master_p3_we_n = 1'd1;
-reg litedramcore_master_p3_cke = 1'd0;
-reg litedramcore_master_p3_odt = 1'd0;
-reg litedramcore_master_p3_reset_n = 1'd0;
-reg litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p3_rddata;
-wire litedramcore_master_p3_rddata_valid;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_re;
-wire litedramcore_phaseinjector0_command_issue_r;
-wire litedramcore_phaseinjector0_command_issue_we;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_status = 32'd0;
-wire litedramcore_phaseinjector0_we;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_re;
-wire litedramcore_phaseinjector1_command_issue_r;
-wire litedramcore_phaseinjector1_command_issue_we;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_status = 32'd0;
-wire litedramcore_phaseinjector1_we;
-reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg litedramcore_phaseinjector2_command_re = 1'd0;
-wire litedramcore_phaseinjector2_command_issue_re;
-wire litedramcore_phaseinjector2_command_issue_r;
-wire litedramcore_phaseinjector2_command_issue_we;
-reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
-reg litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_status = 32'd0;
-wire litedramcore_phaseinjector2_we;
-reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg litedramcore_phaseinjector3_command_re = 1'd0;
-wire litedramcore_phaseinjector3_command_issue_re;
-wire litedramcore_phaseinjector3_command_issue_r;
-wire litedramcore_phaseinjector3_command_issue_we;
-reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
-reg litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_status = 32'd0;
-wire litedramcore_phaseinjector3_we;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [21:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [21:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [21:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [21:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [21:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [21:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [21:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [21:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [127:0] litedramcore_interface_wdata = 128'd0;
-reg [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] litedramcore_interface_rdata;
-reg [14:0] litedramcore_dfi_p0_address = 15'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [14:0] litedramcore_dfi_p1_address = 15'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg [14:0] litedramcore_dfi_p2_address = 15'd0;
-reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg litedramcore_dfi_p2_cas_n = 1'd1;
-reg litedramcore_dfi_p2_cs_n = 1'd1;
-reg litedramcore_dfi_p2_ras_n = 1'd1;
-reg litedramcore_dfi_p2_we_n = 1'd1;
-wire litedramcore_dfi_p2_cke;
-wire litedramcore_dfi_p2_odt;
-wire litedramcore_dfi_p2_reset_n;
-reg litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p2_wrdata;
-reg litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p2_rddata;
-wire litedramcore_dfi_p2_rddata_valid;
-reg [14:0] litedramcore_dfi_p3_address = 15'd0;
-reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg litedramcore_dfi_p3_cas_n = 1'd1;
-reg litedramcore_dfi_p3_cs_n = 1'd1;
-reg litedramcore_dfi_p3_ras_n = 1'd1;
-reg litedramcore_dfi_p3_we_n = 1'd1;
-wire litedramcore_dfi_p3_cke;
-wire litedramcore_dfi_p3_odt;
-wire litedramcore_dfi_p3_reset_n;
-reg litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p3_wrdata;
-reg litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p3_rddata;
-wire litedramcore_dfi_p3_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [14:0] litedramcore_cmd_payload_a = 15'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [9:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [9:0] litedramcore_timer_count1 = 10'd781;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] litedramcore_sequencer_counter = 6'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [26:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [21:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine0_row = 15'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [21:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine1_row = 15'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [21:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine2_row = 15'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [21:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine3_row = 15'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [21:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine4_row = 15'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [21:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine5_row = 15'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [21:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine6_row = 15'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [21:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine7_row = 15'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [14:0] litedramcore_nop_a = 15'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-reg litedramcore_steerer4 = 1'd1;
-reg litedramcore_steerer5 = 1'd1;
-reg litedramcore_steerer6 = 1'd1;
-reg litedramcore_steerer7 = 1'd1;
-wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] litedramcore_tfawcon_count;
-reg [4:0] litedramcore_tfawcon_window = 5'd0;
-wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [24:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [127:0] user_port_wdata_payload_data;
-wire [15:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [127:0] user_port_rdata_payload_data;
-reg state = 1'd0;
-reg next_state = 1'd0;
-wire pll_fb0;
-wire pll_fb1;
-reg [1:0] refresher_state = 2'd0;
-reg [1:0] refresher_next_state = 2'd0;
-reg [3:0] bankmachine0_state = 4'd0;
-reg [3:0] bankmachine0_next_state = 4'd0;
-reg [3:0] bankmachine1_state = 4'd0;
-reg [3:0] bankmachine1_next_state = 4'd0;
-reg [3:0] bankmachine2_state = 4'd0;
-reg [3:0] bankmachine2_next_state = 4'd0;
-reg [3:0] bankmachine3_state = 4'd0;
-reg [3:0] bankmachine3_next_state = 4'd0;
-reg [3:0] bankmachine4_state = 4'd0;
-reg [3:0] bankmachine4_next_state = 4'd0;
-reg [3:0] bankmachine5_state = 4'd0;
-reg [3:0] bankmachine5_next_state = 4'd0;
-reg [3:0] bankmachine6_state = 4'd0;
-reg [3:0] bankmachine6_next_state = 4'd0;
-reg [3:0] bankmachine7_state = 4'd0;
-reg [3:0] bankmachine7_next_state = 4'd0;
-reg [3:0] multiplexer_state = 4'd0;
-reg [3:0] multiplexer_next_state = 4'd0;
-wire roundrobin0_request;
-wire roundrobin0_grant;
-wire roundrobin0_ce;
-wire roundrobin1_request;
-wire roundrobin1_grant;
-wire roundrobin1_ce;
-wire roundrobin2_request;
-wire roundrobin2_grant;
-wire roundrobin2_ce;
-wire roundrobin3_request;
-wire roundrobin3_grant;
-wire roundrobin3_ce;
-wire roundrobin4_request;
-wire roundrobin4_grant;
-wire roundrobin4_ce;
-wire roundrobin5_request;
-wire roundrobin5_grant;
-wire roundrobin5_ce;
-wire roundrobin6_request;
-wire roundrobin6_grant;
-wire roundrobin6_ce;
-wire roundrobin7_request;
-wire roundrobin7_grant;
-wire roundrobin7_ce;
-reg locked0 = 1'd0;
-reg locked1 = 1'd0;
-reg locked2 = 1'd0;
-reg locked3 = 1'd0;
-reg locked4 = 1'd0;
-reg locked5 = 1'd0;
-reg locked6 = 1'd0;
-reg locked7 = 1'd0;
-reg new_master_wdata_ready0 = 1'd0;
-reg new_master_wdata_ready1 = 1'd0;
-reg new_master_wdata_ready2 = 1'd0;
-reg new_master_rdata_valid0 = 1'd0;
-reg new_master_rdata_valid1 = 1'd0;
-reg new_master_rdata_valid2 = 1'd0;
-reg new_master_rdata_valid3 = 1'd0;
-reg new_master_rdata_valid4 = 1'd0;
-reg new_master_rdata_valid5 = 1'd0;
-reg new_master_rdata_valid6 = 1'd0;
-reg new_master_rdata_valid7 = 1'd0;
-reg new_master_rdata_valid8 = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-wire csrbank0_init_done0_re;
-wire csrbank0_init_done0_r;
-wire csrbank0_init_done0_we;
-wire csrbank0_init_done0_w;
-wire csrbank0_init_error0_re;
-wire csrbank0_init_error0_r;
-wire csrbank0_init_error0_we;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-wire csrbank1_half_sys8x_taps0_re;
-wire [4:0] csrbank1_half_sys8x_taps0_r;
-wire csrbank1_half_sys8x_taps0_we;
-wire [4:0] csrbank1_half_sys8x_taps0_w;
-wire csrbank1_wlevel_en0_re;
-wire csrbank1_wlevel_en0_r;
-wire csrbank1_wlevel_en0_we;
-wire csrbank1_wlevel_en0_w;
-wire csrbank1_dly_sel0_re;
-wire [1:0] csrbank1_dly_sel0_r;
-wire csrbank1_dly_sel0_we;
-wire [1:0] csrbank1_dly_sel0_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-wire csrbank2_dfii_control0_re;
-wire [3:0] csrbank2_dfii_control0_r;
-wire csrbank2_dfii_control0_we;
-wire [3:0] csrbank2_dfii_control0_w;
-wire csrbank2_dfii_pi0_command0_re;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-wire csrbank2_dfii_pi0_command0_we;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-wire csrbank2_dfii_pi0_address0_re;
-wire [14:0] csrbank2_dfii_pi0_address0_r;
-wire csrbank2_dfii_pi0_address0_we;
-wire [14:0] csrbank2_dfii_pi0_address0_w;
-wire csrbank2_dfii_pi0_baddress0_re;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-wire csrbank2_dfii_pi0_baddress0_we;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-wire csrbank2_dfii_pi0_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-wire csrbank2_dfii_pi0_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-wire csrbank2_dfii_pi0_rddata_re;
-wire [31:0] csrbank2_dfii_pi0_rddata_r;
-wire csrbank2_dfii_pi0_rddata_we;
-wire [31:0] csrbank2_dfii_pi0_rddata_w;
-wire csrbank2_dfii_pi1_command0_re;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-wire csrbank2_dfii_pi1_command0_we;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-wire csrbank2_dfii_pi1_address0_re;
-wire [14:0] csrbank2_dfii_pi1_address0_r;
-wire csrbank2_dfii_pi1_address0_we;
-wire [14:0] csrbank2_dfii_pi1_address0_w;
-wire csrbank2_dfii_pi1_baddress0_re;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-wire csrbank2_dfii_pi1_baddress0_we;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-wire csrbank2_dfii_pi1_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-wire csrbank2_dfii_pi1_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-wire csrbank2_dfii_pi1_rddata_re;
-wire [31:0] csrbank2_dfii_pi1_rddata_r;
-wire csrbank2_dfii_pi1_rddata_we;
-wire [31:0] csrbank2_dfii_pi1_rddata_w;
-wire csrbank2_dfii_pi2_command0_re;
-wire [5:0] csrbank2_dfii_pi2_command0_r;
-wire csrbank2_dfii_pi2_command0_we;
-wire [5:0] csrbank2_dfii_pi2_command0_w;
-wire csrbank2_dfii_pi2_address0_re;
-wire [14:0] csrbank2_dfii_pi2_address0_r;
-wire csrbank2_dfii_pi2_address0_we;
-wire [14:0] csrbank2_dfii_pi2_address0_w;
-wire csrbank2_dfii_pi2_baddress0_re;
-wire [2:0] csrbank2_dfii_pi2_baddress0_r;
-wire csrbank2_dfii_pi2_baddress0_we;
-wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-wire csrbank2_dfii_pi2_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
-wire csrbank2_dfii_pi2_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
-wire csrbank2_dfii_pi2_rddata_re;
-wire [31:0] csrbank2_dfii_pi2_rddata_r;
-wire csrbank2_dfii_pi2_rddata_we;
-wire [31:0] csrbank2_dfii_pi2_rddata_w;
-wire csrbank2_dfii_pi3_command0_re;
-wire [5:0] csrbank2_dfii_pi3_command0_r;
-wire csrbank2_dfii_pi3_command0_we;
-wire [5:0] csrbank2_dfii_pi3_command0_w;
-wire csrbank2_dfii_pi3_address0_re;
-wire [14:0] csrbank2_dfii_pi3_address0_r;
-wire csrbank2_dfii_pi3_address0_we;
-wire [14:0] csrbank2_dfii_pi3_address0_w;
-wire csrbank2_dfii_pi3_baddress0_re;
-wire [2:0] csrbank2_dfii_pi3_baddress0_r;
-wire csrbank2_dfii_pi3_baddress0_we;
-wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-wire csrbank2_dfii_pi3_wrdata0_re;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
-wire csrbank2_dfii_pi3_wrdata0_we;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
-wire csrbank2_dfii_pi3_rddata_re;
-wire [31:0] csrbank2_dfii_pi3_rddata_r;
-wire csrbank2_dfii_pi3_rddata_we;
-wire [31:0] csrbank2_dfii_pi3_rddata_w;
-wire csrbank2_sel;
-wire [13:0] adr;
-wire we;
-wire [31:0] dat_w;
-wire [31:0] dat_r;
-reg rhs_array_muxed0 = 1'd0;
-reg [14:0] rhs_array_muxed1 = 15'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [14:0] rhs_array_muxed7 = 15'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [21:0] rhs_array_muxed12 = 22'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [21:0] rhs_array_muxed15 = 22'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [21:0] rhs_array_muxed18 = 22'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [21:0] rhs_array_muxed21 = 22'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [21:0] rhs_array_muxed24 = 22'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [21:0] rhs_array_muxed27 = 22'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [21:0] rhs_array_muxed30 = 22'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [21:0] rhs_array_muxed33 = 22'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [14:0] array_muxed1 = 15'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [14:0] array_muxed8 = 15'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [14:0] array_muxed15 = 15'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [14:0] array_muxed22 = 15'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
-wire xilinxasyncresetsynchronizerimpl0;
-wire xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1;
-wire xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1_expr;
-wire xilinxasyncresetsynchronizerimpl2;
-wire xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2_expr;
-wire xilinxasyncresetsynchronizerimpl3;
-wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire soc_reset;
+wire soc_locked;
+wire soc_clkin;
+wire soc_clkout0;
+wire soc_clkout_buf0;
+wire soc_clkout1;
+wire soc_clkout_buf1;
+wire soc_clkout2;
+wire soc_clkout_buf2;
+wire soc_clkout3;
+wire soc_clkout_buf3;
+reg [3:0] soc_reset_counter = 4'd15;
+reg soc_ic_reset = 1'd1;
+reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg soc_a7ddrphy_wlevel_en_storage = 1'd0;
+reg soc_a7ddrphy_wlevel_en_re = 1'd0;
+wire soc_a7ddrphy_wlevel_strobe_re;
+wire soc_a7ddrphy_wlevel_strobe_r;
+wire soc_a7ddrphy_wlevel_strobe_we;
+reg soc_a7ddrphy_wlevel_strobe_w = 1'd0;
+wire soc_a7ddrphy_cdly_rst_re;
+wire soc_a7ddrphy_cdly_rst_r;
+wire soc_a7ddrphy_cdly_rst_we;
+reg soc_a7ddrphy_cdly_rst_w = 1'd0;
+wire soc_a7ddrphy_cdly_inc_re;
+wire soc_a7ddrphy_cdly_inc_r;
+wire soc_a7ddrphy_cdly_inc_we;
+reg soc_a7ddrphy_cdly_inc_w = 1'd0;
+reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
+reg soc_a7ddrphy_dly_sel_re = 1'd0;
+wire soc_a7ddrphy_rdly_dq_rst_re;
+wire soc_a7ddrphy_rdly_dq_rst_r;
+wire soc_a7ddrphy_rdly_dq_rst_we;
+reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_inc_re;
+wire soc_a7ddrphy_rdly_dq_inc_r;
+wire soc_a7ddrphy_rdly_dq_inc_we;
+reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p0_address;
+wire [2:0] soc_a7ddrphy_dfi_p0_bank;
+wire soc_a7ddrphy_dfi_p0_cas_n;
+wire soc_a7ddrphy_dfi_p0_cs_n;
+wire soc_a7ddrphy_dfi_p0_ras_n;
+wire soc_a7ddrphy_dfi_p0_we_n;
+wire soc_a7ddrphy_dfi_p0_cke;
+wire soc_a7ddrphy_dfi_p0_odt;
+wire soc_a7ddrphy_dfi_p0_reset_n;
+wire soc_a7ddrphy_dfi_p0_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
+wire soc_a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
+wire soc_a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p1_address;
+wire [2:0] soc_a7ddrphy_dfi_p1_bank;
+wire soc_a7ddrphy_dfi_p1_cas_n;
+wire soc_a7ddrphy_dfi_p1_cs_n;
+wire soc_a7ddrphy_dfi_p1_ras_n;
+wire soc_a7ddrphy_dfi_p1_we_n;
+wire soc_a7ddrphy_dfi_p1_cke;
+wire soc_a7ddrphy_dfi_p1_odt;
+wire soc_a7ddrphy_dfi_p1_reset_n;
+wire soc_a7ddrphy_dfi_p1_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
+wire soc_a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
+wire soc_a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p2_address;
+wire [2:0] soc_a7ddrphy_dfi_p2_bank;
+wire soc_a7ddrphy_dfi_p2_cas_n;
+wire soc_a7ddrphy_dfi_p2_cs_n;
+wire soc_a7ddrphy_dfi_p2_ras_n;
+wire soc_a7ddrphy_dfi_p2_we_n;
+wire soc_a7ddrphy_dfi_p2_cke;
+wire soc_a7ddrphy_dfi_p2_odt;
+wire soc_a7ddrphy_dfi_p2_reset_n;
+wire soc_a7ddrphy_dfi_p2_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
+wire soc_a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
+wire soc_a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p3_address;
+wire [2:0] soc_a7ddrphy_dfi_p3_bank;
+wire soc_a7ddrphy_dfi_p3_cas_n;
+wire soc_a7ddrphy_dfi_p3_cs_n;
+wire soc_a7ddrphy_dfi_p3_ras_n;
+wire soc_a7ddrphy_dfi_p3_we_n;
+wire soc_a7ddrphy_dfi_p3_cke;
+wire soc_a7ddrphy_dfi_p3_odt;
+wire soc_a7ddrphy_dfi_p3_reset_n;
+wire soc_a7ddrphy_dfi_p3_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
+wire soc_a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
+wire soc_a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
+wire soc_a7ddrphy_sd_clk_se_nodelay;
+reg soc_a7ddrphy_dqs_oe = 1'd0;
+reg soc_a7ddrphy_dqs_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dqspattern0;
+wire soc_a7ddrphy_dqspattern1;
+reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0;
+wire [1:0] soc_a7ddrphy_dqs_i;
+wire [1:0] soc_a7ddrphy_dqs_i_delayed;
+wire soc_a7ddrphy_dqs_o_no_delay0;
+wire soc_a7ddrphy_dqs_t0;
+wire soc_a7ddrphy0;
+wire soc_a7ddrphy_dqs_o_no_delay1;
+wire soc_a7ddrphy_dqs_t1;
+wire soc_a7ddrphy1;
+wire soc_a7ddrphy_dq_oe;
+reg soc_a7ddrphy_dq_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dq_o_nodelay0;
+wire soc_a7ddrphy_dq_i_nodelay0;
+wire soc_a7ddrphy_dq_i_delayed0;
+wire soc_a7ddrphy_dq_t0;
+wire [7:0] soc_a7ddrphy_dq_i_data0;
+wire [7:0] soc_a7ddrphy_bitslip0_i;
+reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip0_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip0_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay1;
+wire soc_a7ddrphy_dq_i_nodelay1;
+wire soc_a7ddrphy_dq_i_delayed1;
+wire soc_a7ddrphy_dq_t1;
+wire [7:0] soc_a7ddrphy_dq_i_data1;
+wire [7:0] soc_a7ddrphy_bitslip1_i;
+reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip1_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip1_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay2;
+wire soc_a7ddrphy_dq_i_nodelay2;
+wire soc_a7ddrphy_dq_i_delayed2;
+wire soc_a7ddrphy_dq_t2;
+wire [7:0] soc_a7ddrphy_dq_i_data2;
+wire [7:0] soc_a7ddrphy_bitslip2_i;
+reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip2_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip2_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay3;
+wire soc_a7ddrphy_dq_i_nodelay3;
+wire soc_a7ddrphy_dq_i_delayed3;
+wire soc_a7ddrphy_dq_t3;
+wire [7:0] soc_a7ddrphy_dq_i_data3;
+wire [7:0] soc_a7ddrphy_bitslip3_i;
+reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip3_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip3_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay4;
+wire soc_a7ddrphy_dq_i_nodelay4;
+wire soc_a7ddrphy_dq_i_delayed4;
+wire soc_a7ddrphy_dq_t4;
+wire [7:0] soc_a7ddrphy_dq_i_data4;
+wire [7:0] soc_a7ddrphy_bitslip4_i;
+reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip4_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip4_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay5;
+wire soc_a7ddrphy_dq_i_nodelay5;
+wire soc_a7ddrphy_dq_i_delayed5;
+wire soc_a7ddrphy_dq_t5;
+wire [7:0] soc_a7ddrphy_dq_i_data5;
+wire [7:0] soc_a7ddrphy_bitslip5_i;
+reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip5_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip5_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay6;
+wire soc_a7ddrphy_dq_i_nodelay6;
+wire soc_a7ddrphy_dq_i_delayed6;
+wire soc_a7ddrphy_dq_t6;
+wire [7:0] soc_a7ddrphy_dq_i_data6;
+wire [7:0] soc_a7ddrphy_bitslip6_i;
+reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip6_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip6_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay7;
+wire soc_a7ddrphy_dq_i_nodelay7;
+wire soc_a7ddrphy_dq_i_delayed7;
+wire soc_a7ddrphy_dq_t7;
+wire [7:0] soc_a7ddrphy_dq_i_data7;
+wire [7:0] soc_a7ddrphy_bitslip7_i;
+reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip7_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip7_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay8;
+wire soc_a7ddrphy_dq_i_nodelay8;
+wire soc_a7ddrphy_dq_i_delayed8;
+wire soc_a7ddrphy_dq_t8;
+wire [7:0] soc_a7ddrphy_dq_i_data8;
+wire [7:0] soc_a7ddrphy_bitslip8_i;
+reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip8_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip8_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay9;
+wire soc_a7ddrphy_dq_i_nodelay9;
+wire soc_a7ddrphy_dq_i_delayed9;
+wire soc_a7ddrphy_dq_t9;
+wire [7:0] soc_a7ddrphy_dq_i_data9;
+wire [7:0] soc_a7ddrphy_bitslip9_i;
+reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip9_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip9_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay10;
+wire soc_a7ddrphy_dq_i_nodelay10;
+wire soc_a7ddrphy_dq_i_delayed10;
+wire soc_a7ddrphy_dq_t10;
+wire [7:0] soc_a7ddrphy_dq_i_data10;
+wire [7:0] soc_a7ddrphy_bitslip10_i;
+reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip10_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip10_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay11;
+wire soc_a7ddrphy_dq_i_nodelay11;
+wire soc_a7ddrphy_dq_i_delayed11;
+wire soc_a7ddrphy_dq_t11;
+wire [7:0] soc_a7ddrphy_dq_i_data11;
+wire [7:0] soc_a7ddrphy_bitslip11_i;
+reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip11_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip11_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay12;
+wire soc_a7ddrphy_dq_i_nodelay12;
+wire soc_a7ddrphy_dq_i_delayed12;
+wire soc_a7ddrphy_dq_t12;
+wire [7:0] soc_a7ddrphy_dq_i_data12;
+wire [7:0] soc_a7ddrphy_bitslip12_i;
+reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip12_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip12_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay13;
+wire soc_a7ddrphy_dq_i_nodelay13;
+wire soc_a7ddrphy_dq_i_delayed13;
+wire soc_a7ddrphy_dq_t13;
+wire [7:0] soc_a7ddrphy_dq_i_data13;
+wire [7:0] soc_a7ddrphy_bitslip13_i;
+reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip13_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip13_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay14;
+wire soc_a7ddrphy_dq_i_nodelay14;
+wire soc_a7ddrphy_dq_i_delayed14;
+wire soc_a7ddrphy_dq_t14;
+wire [7:0] soc_a7ddrphy_dq_i_data14;
+wire [7:0] soc_a7ddrphy_bitslip14_i;
+reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip14_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip14_r = 24'd0;
+wire soc_a7ddrphy_dq_o_nodelay15;
+wire soc_a7ddrphy_dq_i_nodelay15;
+wire soc_a7ddrphy_dq_i_delayed15;
+wire soc_a7ddrphy_dq_t15;
+wire [7:0] soc_a7ddrphy_dq_i_data15;
+wire [7:0] soc_a7ddrphy_bitslip15_i;
+reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
+reg [3:0] soc_a7ddrphy_bitslip15_value = 4'd0;
+reg [23:0] soc_a7ddrphy_bitslip15_r = 24'd0;
+wire [7:0] soc_a7ddrphy_rddata_en;
+reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0;
+wire [3:0] soc_a7ddrphy_wrdata_en;
+reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0;
+wire [14:0] soc_litedramcore_inti_p0_address;
+wire [2:0] soc_litedramcore_inti_p0_bank;
+reg soc_litedramcore_inti_p0_cas_n = 1'd1;
+reg soc_litedramcore_inti_p0_cs_n = 1'd1;
+reg soc_litedramcore_inti_p0_ras_n = 1'd1;
+reg soc_litedramcore_inti_p0_we_n = 1'd1;
+wire soc_litedramcore_inti_p0_cke;
+wire soc_litedramcore_inti_p0_odt;
+wire soc_litedramcore_inti_p0_reset_n;
+reg soc_litedramcore_inti_p0_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p0_wrdata;
+wire soc_litedramcore_inti_p0_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p0_wrdata_mask;
+wire soc_litedramcore_inti_p0_rddata_en;
+reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0;
+reg soc_litedramcore_inti_p0_rddata_valid = 1'd0;
+wire [14:0] soc_litedramcore_inti_p1_address;
+wire [2:0] soc_litedramcore_inti_p1_bank;
+reg soc_litedramcore_inti_p1_cas_n = 1'd1;
+reg soc_litedramcore_inti_p1_cs_n = 1'd1;
+reg soc_litedramcore_inti_p1_ras_n = 1'd1;
+reg soc_litedramcore_inti_p1_we_n = 1'd1;
+wire soc_litedramcore_inti_p1_cke;
+wire soc_litedramcore_inti_p1_odt;
+wire soc_litedramcore_inti_p1_reset_n;
+reg soc_litedramcore_inti_p1_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p1_wrdata;
+wire soc_litedramcore_inti_p1_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p1_wrdata_mask;
+wire soc_litedramcore_inti_p1_rddata_en;
+reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0;
+reg soc_litedramcore_inti_p1_rddata_valid = 1'd0;
+wire [14:0] soc_litedramcore_inti_p2_address;
+wire [2:0] soc_litedramcore_inti_p2_bank;
+reg soc_litedramcore_inti_p2_cas_n = 1'd1;
+reg soc_litedramcore_inti_p2_cs_n = 1'd1;
+reg soc_litedramcore_inti_p2_ras_n = 1'd1;
+reg soc_litedramcore_inti_p2_we_n = 1'd1;
+wire soc_litedramcore_inti_p2_cke;
+wire soc_litedramcore_inti_p2_odt;
+wire soc_litedramcore_inti_p2_reset_n;
+reg soc_litedramcore_inti_p2_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p2_wrdata;
+wire soc_litedramcore_inti_p2_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p2_wrdata_mask;
+wire soc_litedramcore_inti_p2_rddata_en;
+reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0;
+reg soc_litedramcore_inti_p2_rddata_valid = 1'd0;
+wire [14:0] soc_litedramcore_inti_p3_address;
+wire [2:0] soc_litedramcore_inti_p3_bank;
+reg soc_litedramcore_inti_p3_cas_n = 1'd1;
+reg soc_litedramcore_inti_p3_cs_n = 1'd1;
+reg soc_litedramcore_inti_p3_ras_n = 1'd1;
+reg soc_litedramcore_inti_p3_we_n = 1'd1;
+wire soc_litedramcore_inti_p3_cke;
+wire soc_litedramcore_inti_p3_odt;
+wire soc_litedramcore_inti_p3_reset_n;
+reg soc_litedramcore_inti_p3_act_n = 1'd1;
+wire [31:0] soc_litedramcore_inti_p3_wrdata;
+wire soc_litedramcore_inti_p3_wrdata_en;
+wire [3:0] soc_litedramcore_inti_p3_wrdata_mask;
+wire soc_litedramcore_inti_p3_rddata_en;
+reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0;
+reg soc_litedramcore_inti_p3_rddata_valid = 1'd0;
+wire [14:0] soc_litedramcore_slave_p0_address;
+wire [2:0] soc_litedramcore_slave_p0_bank;
+wire soc_litedramcore_slave_p0_cas_n;
+wire soc_litedramcore_slave_p0_cs_n;
+wire soc_litedramcore_slave_p0_ras_n;
+wire soc_litedramcore_slave_p0_we_n;
+wire soc_litedramcore_slave_p0_cke;
+wire soc_litedramcore_slave_p0_odt;
+wire soc_litedramcore_slave_p0_reset_n;
+wire soc_litedramcore_slave_p0_act_n;
+wire [31:0] soc_litedramcore_slave_p0_wrdata;
+wire soc_litedramcore_slave_p0_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p0_wrdata_mask;
+wire soc_litedramcore_slave_p0_rddata_en;
+reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
+reg soc_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] soc_litedramcore_slave_p1_address;
+wire [2:0] soc_litedramcore_slave_p1_bank;
+wire soc_litedramcore_slave_p1_cas_n;
+wire soc_litedramcore_slave_p1_cs_n;
+wire soc_litedramcore_slave_p1_ras_n;
+wire soc_litedramcore_slave_p1_we_n;
+wire soc_litedramcore_slave_p1_cke;
+wire soc_litedramcore_slave_p1_odt;
+wire soc_litedramcore_slave_p1_reset_n;
+wire soc_litedramcore_slave_p1_act_n;
+wire [31:0] soc_litedramcore_slave_p1_wrdata;
+wire soc_litedramcore_slave_p1_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p1_wrdata_mask;
+wire soc_litedramcore_slave_p1_rddata_en;
+reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
+reg soc_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [14:0] soc_litedramcore_slave_p2_address;
+wire [2:0] soc_litedramcore_slave_p2_bank;
+wire soc_litedramcore_slave_p2_cas_n;
+wire soc_litedramcore_slave_p2_cs_n;
+wire soc_litedramcore_slave_p2_ras_n;
+wire soc_litedramcore_slave_p2_we_n;
+wire soc_litedramcore_slave_p2_cke;
+wire soc_litedramcore_slave_p2_odt;
+wire soc_litedramcore_slave_p2_reset_n;
+wire soc_litedramcore_slave_p2_act_n;
+wire [31:0] soc_litedramcore_slave_p2_wrdata;
+wire soc_litedramcore_slave_p2_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p2_wrdata_mask;
+wire soc_litedramcore_slave_p2_rddata_en;
+reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
+reg soc_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [14:0] soc_litedramcore_slave_p3_address;
+wire [2:0] soc_litedramcore_slave_p3_bank;
+wire soc_litedramcore_slave_p3_cas_n;
+wire soc_litedramcore_slave_p3_cs_n;
+wire soc_litedramcore_slave_p3_ras_n;
+wire soc_litedramcore_slave_p3_we_n;
+wire soc_litedramcore_slave_p3_cke;
+wire soc_litedramcore_slave_p3_odt;
+wire soc_litedramcore_slave_p3_reset_n;
+wire soc_litedramcore_slave_p3_act_n;
+wire [31:0] soc_litedramcore_slave_p3_wrdata;
+wire soc_litedramcore_slave_p3_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p3_wrdata_mask;
+wire soc_litedramcore_slave_p3_rddata_en;
+reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
+reg soc_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [14:0] soc_litedramcore_master_p0_address = 15'd0;
+reg [2:0] soc_litedramcore_master_p0_bank = 3'd0;
+reg soc_litedramcore_master_p0_cas_n = 1'd1;
+reg soc_litedramcore_master_p0_cs_n = 1'd1;
+reg soc_litedramcore_master_p0_ras_n = 1'd1;
+reg soc_litedramcore_master_p0_we_n = 1'd1;
+reg soc_litedramcore_master_p0_cke = 1'd0;
+reg soc_litedramcore_master_p0_odt = 1'd0;
+reg soc_litedramcore_master_p0_reset_n = 1'd0;
+reg soc_litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
+reg soc_litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p0_rddata;
+wire soc_litedramcore_master_p0_rddata_valid;
+reg [14:0] soc_litedramcore_master_p1_address = 15'd0;
+reg [2:0] soc_litedramcore_master_p1_bank = 3'd0;
+reg soc_litedramcore_master_p1_cas_n = 1'd1;
+reg soc_litedramcore_master_p1_cs_n = 1'd1;
+reg soc_litedramcore_master_p1_ras_n = 1'd1;
+reg soc_litedramcore_master_p1_we_n = 1'd1;
+reg soc_litedramcore_master_p1_cke = 1'd0;
+reg soc_litedramcore_master_p1_odt = 1'd0;
+reg soc_litedramcore_master_p1_reset_n = 1'd0;
+reg soc_litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
+reg soc_litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p1_rddata;
+wire soc_litedramcore_master_p1_rddata_valid;
+reg [14:0] soc_litedramcore_master_p2_address = 15'd0;
+reg [2:0] soc_litedramcore_master_p2_bank = 3'd0;
+reg soc_litedramcore_master_p2_cas_n = 1'd1;
+reg soc_litedramcore_master_p2_cs_n = 1'd1;
+reg soc_litedramcore_master_p2_ras_n = 1'd1;
+reg soc_litedramcore_master_p2_we_n = 1'd1;
+reg soc_litedramcore_master_p2_cke = 1'd0;
+reg soc_litedramcore_master_p2_odt = 1'd0;
+reg soc_litedramcore_master_p2_reset_n = 1'd0;
+reg soc_litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
+reg soc_litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p2_rddata;
+wire soc_litedramcore_master_p2_rddata_valid;
+reg [14:0] soc_litedramcore_master_p3_address = 15'd0;
+reg [2:0] soc_litedramcore_master_p3_bank = 3'd0;
+reg soc_litedramcore_master_p3_cas_n = 1'd1;
+reg soc_litedramcore_master_p3_cs_n = 1'd1;
+reg soc_litedramcore_master_p3_ras_n = 1'd1;
+reg soc_litedramcore_master_p3_we_n = 1'd1;
+reg soc_litedramcore_master_p3_cke = 1'd0;
+reg soc_litedramcore_master_p3_odt = 1'd0;
+reg soc_litedramcore_master_p3_reset_n = 1'd0;
+reg soc_litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
+reg soc_litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p3_rddata;
+wire soc_litedramcore_master_p3_rddata_valid;
+wire soc_litedramcore_sel;
+wire soc_litedramcore_cke;
+wire soc_litedramcore_odt;
+wire soc_litedramcore_reset_n;
+reg [3:0] soc_litedramcore_storage = 4'd1;
+reg soc_litedramcore_re = 1'd0;
+reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector0_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector0_command_issue_re;
+wire soc_litedramcore_phaseinjector0_command_issue_r;
+wire soc_litedramcore_phaseinjector0_command_issue_we;
+reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [14:0] soc_litedramcore_phaseinjector0_address_storage = 15'd0;
+reg soc_litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector0_status = 32'd0;
+wire soc_litedramcore_phaseinjector0_we;
+reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector1_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector1_command_issue_re;
+wire soc_litedramcore_phaseinjector1_command_issue_r;
+wire soc_litedramcore_phaseinjector1_command_issue_we;
+reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [14:0] soc_litedramcore_phaseinjector1_address_storage = 15'd0;
+reg soc_litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector1_status = 32'd0;
+wire soc_litedramcore_phaseinjector1_we;
+reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector2_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector2_command_issue_re;
+wire soc_litedramcore_phaseinjector2_command_issue_r;
+wire soc_litedramcore_phaseinjector2_command_issue_we;
+reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [14:0] soc_litedramcore_phaseinjector2_address_storage = 15'd0;
+reg soc_litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector2_status = 32'd0;
+wire soc_litedramcore_phaseinjector2_we;
+reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector3_command_re = 1'd0;
+wire soc_litedramcore_phaseinjector3_command_issue_re;
+wire soc_litedramcore_phaseinjector3_command_issue_r;
+wire soc_litedramcore_phaseinjector3_command_issue_we;
+reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [14:0] soc_litedramcore_phaseinjector3_address_storage = 15'd0;
+reg soc_litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector3_status = 32'd0;
+wire soc_litedramcore_phaseinjector3_we;
+wire soc_litedramcore_interface_bank0_valid;
+wire soc_litedramcore_interface_bank0_ready;
+wire soc_litedramcore_interface_bank0_we;
+wire [21:0] soc_litedramcore_interface_bank0_addr;
+wire soc_litedramcore_interface_bank0_lock;
+wire soc_litedramcore_interface_bank0_wdata_ready;
+wire soc_litedramcore_interface_bank0_rdata_valid;
+wire soc_litedramcore_interface_bank1_valid;
+wire soc_litedramcore_interface_bank1_ready;
+wire soc_litedramcore_interface_bank1_we;
+wire [21:0] soc_litedramcore_interface_bank1_addr;
+wire soc_litedramcore_interface_bank1_lock;
+wire soc_litedramcore_interface_bank1_wdata_ready;
+wire soc_litedramcore_interface_bank1_rdata_valid;
+wire soc_litedramcore_interface_bank2_valid;
+wire soc_litedramcore_interface_bank2_ready;
+wire soc_litedramcore_interface_bank2_we;
+wire [21:0] soc_litedramcore_interface_bank2_addr;
+wire soc_litedramcore_interface_bank2_lock;
+wire soc_litedramcore_interface_bank2_wdata_ready;
+wire soc_litedramcore_interface_bank2_rdata_valid;
+wire soc_litedramcore_interface_bank3_valid;
+wire soc_litedramcore_interface_bank3_ready;
+wire soc_litedramcore_interface_bank3_we;
+wire [21:0] soc_litedramcore_interface_bank3_addr;
+wire soc_litedramcore_interface_bank3_lock;
+wire soc_litedramcore_interface_bank3_wdata_ready;
+wire soc_litedramcore_interface_bank3_rdata_valid;
+wire soc_litedramcore_interface_bank4_valid;
+wire soc_litedramcore_interface_bank4_ready;
+wire soc_litedramcore_interface_bank4_we;
+wire [21:0] soc_litedramcore_interface_bank4_addr;
+wire soc_litedramcore_interface_bank4_lock;
+wire soc_litedramcore_interface_bank4_wdata_ready;
+wire soc_litedramcore_interface_bank4_rdata_valid;
+wire soc_litedramcore_interface_bank5_valid;
+wire soc_litedramcore_interface_bank5_ready;
+wire soc_litedramcore_interface_bank5_we;
+wire [21:0] soc_litedramcore_interface_bank5_addr;
+wire soc_litedramcore_interface_bank5_lock;
+wire soc_litedramcore_interface_bank5_wdata_ready;
+wire soc_litedramcore_interface_bank5_rdata_valid;
+wire soc_litedramcore_interface_bank6_valid;
+wire soc_litedramcore_interface_bank6_ready;
+wire soc_litedramcore_interface_bank6_we;
+wire [21:0] soc_litedramcore_interface_bank6_addr;
+wire soc_litedramcore_interface_bank6_lock;
+wire soc_litedramcore_interface_bank6_wdata_ready;
+wire soc_litedramcore_interface_bank6_rdata_valid;
+wire soc_litedramcore_interface_bank7_valid;
+wire soc_litedramcore_interface_bank7_ready;
+wire soc_litedramcore_interface_bank7_we;
+wire [21:0] soc_litedramcore_interface_bank7_addr;
+wire soc_litedramcore_interface_bank7_lock;
+wire soc_litedramcore_interface_bank7_wdata_ready;
+wire soc_litedramcore_interface_bank7_rdata_valid;
+reg [127:0] soc_litedramcore_interface_wdata = 128'd0;
+reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] soc_litedramcore_interface_rdata;
+reg [14:0] soc_litedramcore_dfi_p0_address = 15'd0;
+reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
+reg soc_litedramcore_dfi_p0_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p0_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p0_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p0_we_n = 1'd1;
+wire soc_litedramcore_dfi_p0_cke;
+wire soc_litedramcore_dfi_p0_odt;
+wire soc_litedramcore_dfi_p0_reset_n;
+reg soc_litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p0_wrdata;
+reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
+reg soc_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p0_rddata;
+wire soc_litedramcore_dfi_p0_rddata_valid;
+reg [14:0] soc_litedramcore_dfi_p1_address = 15'd0;
+reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
+reg soc_litedramcore_dfi_p1_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p1_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p1_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p1_we_n = 1'd1;
+wire soc_litedramcore_dfi_p1_cke;
+wire soc_litedramcore_dfi_p1_odt;
+wire soc_litedramcore_dfi_p1_reset_n;
+reg soc_litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p1_wrdata;
+reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
+reg soc_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p1_rddata;
+wire soc_litedramcore_dfi_p1_rddata_valid;
+reg [14:0] soc_litedramcore_dfi_p2_address = 15'd0;
+reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
+reg soc_litedramcore_dfi_p2_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p2_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p2_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p2_we_n = 1'd1;
+wire soc_litedramcore_dfi_p2_cke;
+wire soc_litedramcore_dfi_p2_odt;
+wire soc_litedramcore_dfi_p2_reset_n;
+reg soc_litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p2_wrdata;
+reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
+reg soc_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p2_rddata;
+wire soc_litedramcore_dfi_p2_rddata_valid;
+reg [14:0] soc_litedramcore_dfi_p3_address = 15'd0;
+reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
+reg soc_litedramcore_dfi_p3_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p3_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p3_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p3_we_n = 1'd1;
+wire soc_litedramcore_dfi_p3_cke;
+wire soc_litedramcore_dfi_p3_odt;
+wire soc_litedramcore_dfi_p3_reset_n;
+reg soc_litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p3_wrdata;
+reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
+reg soc_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p3_rddata;
+wire soc_litedramcore_dfi_p3_rddata_valid;
+reg soc_litedramcore_cmd_valid = 1'd0;
+reg soc_litedramcore_cmd_ready = 1'd0;
+reg soc_litedramcore_cmd_last = 1'd0;
+reg [14:0] soc_litedramcore_cmd_payload_a = 15'd0;
+reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
+reg soc_litedramcore_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_cmd_payload_we = 1'd0;
+reg soc_litedramcore_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_cmd_payload_is_write = 1'd0;
+wire soc_litedramcore_wants_refresh;
+wire soc_litedramcore_wants_zqcs;
+wire soc_litedramcore_timer_wait;
+wire soc_litedramcore_timer_done0;
+wire [9:0] soc_litedramcore_timer_count0;
+wire soc_litedramcore_timer_done1;
+reg [9:0] soc_litedramcore_timer_count1 = 10'd781;
+wire soc_litedramcore_postponer_req_i;
+reg soc_litedramcore_postponer_req_o = 1'd0;
+reg soc_litedramcore_postponer_count = 1'd0;
+reg soc_litedramcore_sequencer_start0 = 1'd0;
+wire soc_litedramcore_sequencer_done0;
+wire soc_litedramcore_sequencer_start1;
+reg soc_litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] soc_litedramcore_sequencer_counter = 6'd0;
+reg soc_litedramcore_sequencer_count = 1'd0;
+wire soc_litedramcore_zqcs_timer_wait;
+wire soc_litedramcore_zqcs_timer_done0;
+wire [26:0] soc_litedramcore_zqcs_timer_count0;
+wire soc_litedramcore_zqcs_timer_done1;
+reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg soc_litedramcore_zqcs_executer_start = 1'd0;
+reg soc_litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
+wire soc_litedramcore_bankmachine0_req_valid;
+wire soc_litedramcore_bankmachine0_req_ready;
+wire soc_litedramcore_bankmachine0_req_we;
+wire [21:0] soc_litedramcore_bankmachine0_req_addr;
+wire soc_litedramcore_bankmachine0_req_lock;
+reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine0_refresh_req;
+reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
+reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine0_row = 15'd0;
+reg soc_litedramcore_bankmachine0_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine0_row_hit;
+reg soc_litedramcore_bankmachine0_row_open = 1'd0;
+reg soc_litedramcore_bankmachine0_row_close = 1'd0;
+reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_req_valid;
+wire soc_litedramcore_bankmachine1_req_ready;
+wire soc_litedramcore_bankmachine1_req_we;
+wire [21:0] soc_litedramcore_bankmachine1_req_addr;
+wire soc_litedramcore_bankmachine1_req_lock;
+reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine1_refresh_req;
+reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
+reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine1_row = 15'd0;
+reg soc_litedramcore_bankmachine1_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine1_row_hit;
+reg soc_litedramcore_bankmachine1_row_open = 1'd0;
+reg soc_litedramcore_bankmachine1_row_close = 1'd0;
+reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_req_valid;
+wire soc_litedramcore_bankmachine2_req_ready;
+wire soc_litedramcore_bankmachine2_req_we;
+wire [21:0] soc_litedramcore_bankmachine2_req_addr;
+wire soc_litedramcore_bankmachine2_req_lock;
+reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine2_refresh_req;
+reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
+reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine2_row = 15'd0;
+reg soc_litedramcore_bankmachine2_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine2_row_hit;
+reg soc_litedramcore_bankmachine2_row_open = 1'd0;
+reg soc_litedramcore_bankmachine2_row_close = 1'd0;
+reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_req_valid;
+wire soc_litedramcore_bankmachine3_req_ready;
+wire soc_litedramcore_bankmachine3_req_we;
+wire [21:0] soc_litedramcore_bankmachine3_req_addr;
+wire soc_litedramcore_bankmachine3_req_lock;
+reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine3_refresh_req;
+reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
+reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine3_row = 15'd0;
+reg soc_litedramcore_bankmachine3_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine3_row_hit;
+reg soc_litedramcore_bankmachine3_row_open = 1'd0;
+reg soc_litedramcore_bankmachine3_row_close = 1'd0;
+reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_req_valid;
+wire soc_litedramcore_bankmachine4_req_ready;
+wire soc_litedramcore_bankmachine4_req_we;
+wire [21:0] soc_litedramcore_bankmachine4_req_addr;
+wire soc_litedramcore_bankmachine4_req_lock;
+reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine4_refresh_req;
+reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
+reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine4_row = 15'd0;
+reg soc_litedramcore_bankmachine4_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine4_row_hit;
+reg soc_litedramcore_bankmachine4_row_open = 1'd0;
+reg soc_litedramcore_bankmachine4_row_close = 1'd0;
+reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_req_valid;
+wire soc_litedramcore_bankmachine5_req_ready;
+wire soc_litedramcore_bankmachine5_req_we;
+wire [21:0] soc_litedramcore_bankmachine5_req_addr;
+wire soc_litedramcore_bankmachine5_req_lock;
+reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine5_refresh_req;
+reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
+reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine5_row = 15'd0;
+reg soc_litedramcore_bankmachine5_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine5_row_hit;
+reg soc_litedramcore_bankmachine5_row_open = 1'd0;
+reg soc_litedramcore_bankmachine5_row_close = 1'd0;
+reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_req_valid;
+wire soc_litedramcore_bankmachine6_req_ready;
+wire soc_litedramcore_bankmachine6_req_we;
+wire [21:0] soc_litedramcore_bankmachine6_req_addr;
+wire soc_litedramcore_bankmachine6_req_lock;
+reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine6_refresh_req;
+reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
+reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine6_row = 15'd0;
+reg soc_litedramcore_bankmachine6_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine6_row_hit;
+reg soc_litedramcore_bankmachine6_row_open = 1'd0;
+reg soc_litedramcore_bankmachine6_row_close = 1'd0;
+reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_req_valid;
+wire soc_litedramcore_bankmachine7_req_ready;
+wire soc_litedramcore_bankmachine7_req_we;
+wire [21:0] soc_litedramcore_bankmachine7_req_addr;
+wire soc_litedramcore_bankmachine7_req_lock;
+reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine7_refresh_req;
+reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [14:0] soc_litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
+reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [21:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_litedramcore_bankmachine7_row = 15'd0;
+reg soc_litedramcore_bankmachine7_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine7_row_hit;
+reg soc_litedramcore_bankmachine7_row_open = 1'd0;
+reg soc_litedramcore_bankmachine7_row_close = 1'd0;
+reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
+wire soc_litedramcore_ras_allowed;
+wire soc_litedramcore_cas_allowed;
+reg soc_litedramcore_choose_cmd_want_reads = 1'd0;
+reg soc_litedramcore_choose_cmd_want_writes = 1'd0;
+reg soc_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg soc_litedramcore_choose_cmd_want_activates = 1'd0;
+wire soc_litedramcore_choose_cmd_cmd_valid;
+reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] soc_litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
+reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_read;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] soc_litedramcore_choose_cmd_request;
+reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
+wire soc_litedramcore_choose_cmd_ce;
+reg soc_litedramcore_choose_req_want_reads = 1'd0;
+reg soc_litedramcore_choose_req_want_writes = 1'd0;
+reg soc_litedramcore_choose_req_want_cmds = 1'd0;
+reg soc_litedramcore_choose_req_want_activates = 1'd0;
+wire soc_litedramcore_choose_req_cmd_valid;
+reg soc_litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] soc_litedramcore_choose_req_cmd_payload_a;
+wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
+reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire soc_litedramcore_choose_req_cmd_payload_is_cmd;
+wire soc_litedramcore_choose_req_cmd_payload_is_read;
+wire soc_litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] soc_litedramcore_choose_req_valids = 8'd0;
+wire [7:0] soc_litedramcore_choose_req_request;
+reg [2:0] soc_litedramcore_choose_req_grant = 3'd0;
+wire soc_litedramcore_choose_req_ce;
+reg [14:0] soc_litedramcore_nop_a = 15'd0;
+reg [2:0] soc_litedramcore_nop_ba = 3'd0;
+reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
+reg soc_litedramcore_steerer0 = 1'd1;
+reg soc_litedramcore_steerer1 = 1'd1;
+reg soc_litedramcore_steerer2 = 1'd1;
+reg soc_litedramcore_steerer3 = 1'd1;
+reg soc_litedramcore_steerer4 = 1'd1;
+reg soc_litedramcore_steerer5 = 1'd1;
+reg soc_litedramcore_steerer6 = 1'd1;
+reg soc_litedramcore_steerer7 = 1'd1;
+wire soc_litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0;
+reg soc_litedramcore_trrdcon_count = 1'd0;
+wire soc_litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] soc_litedramcore_tfawcon_count;
+reg [4:0] soc_litedramcore_tfawcon_window = 5'd0;
+wire soc_litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0;
+reg soc_litedramcore_tccdcon_count = 1'd0;
+wire soc_litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_twtrcon_count = 3'd0;
+wire soc_litedramcore_read_available;
+wire soc_litedramcore_write_available;
+reg soc_litedramcore_en0 = 1'd0;
+wire soc_litedramcore_max_time0;
+reg [4:0] soc_litedramcore_time0 = 5'd0;
+reg soc_litedramcore_en1 = 1'd0;
+wire soc_litedramcore_max_time1;
+reg [3:0] soc_litedramcore_time1 = 4'd0;
+wire soc_litedramcore_go_to_refresh;
+reg soc_init_done_storage = 1'd0;
+reg soc_init_done_re = 1'd0;
+reg soc_init_error_storage = 1'd0;
+reg soc_init_error_re = 1'd0;
+wire [29:0] soc_wb_bus_adr;
+wire [31:0] soc_wb_bus_dat_w;
+wire [31:0] soc_wb_bus_dat_r;
+wire [3:0] soc_wb_bus_sel;
+wire soc_wb_bus_cyc;
+wire soc_wb_bus_stb;
+wire soc_wb_bus_ack;
+wire soc_wb_bus_we;
+wire [2:0] soc_wb_bus_cti;
+wire [1:0] soc_wb_bus_bte;
+wire soc_wb_bus_err;
+wire soc_user_port_cmd_valid;
+wire soc_user_port_cmd_ready;
+wire soc_user_port_cmd_payload_we;
+wire [24:0] soc_user_port_cmd_payload_addr;
+wire soc_user_port_wdata_valid;
+wire soc_user_port_wdata_ready;
+wire [127:0] soc_user_port_wdata_payload_data;
+wire [15:0] soc_user_port_wdata_payload_we;
+wire soc_user_port_rdata_valid;
+wire soc_user_port_rdata_ready;
+wire [127:0] soc_user_port_rdata_payload_data;
+reg vns_state = 1'd0;
+reg vns_next_state = 1'd0;
+wire vns_pll_fb;
+reg [1:0] vns_refresher_state = 2'd0;
+reg [1:0] vns_refresher_next_state = 2'd0;
+reg [3:0] vns_bankmachine0_state = 4'd0;
+reg [3:0] vns_bankmachine0_next_state = 4'd0;
+reg [3:0] vns_bankmachine1_state = 4'd0;
+reg [3:0] vns_bankmachine1_next_state = 4'd0;
+reg [3:0] vns_bankmachine2_state = 4'd0;
+reg [3:0] vns_bankmachine2_next_state = 4'd0;
+reg [3:0] vns_bankmachine3_state = 4'd0;
+reg [3:0] vns_bankmachine3_next_state = 4'd0;
+reg [3:0] vns_bankmachine4_state = 4'd0;
+reg [3:0] vns_bankmachine4_next_state = 4'd0;
+reg [3:0] vns_bankmachine5_state = 4'd0;
+reg [3:0] vns_bankmachine5_next_state = 4'd0;
+reg [3:0] vns_bankmachine6_state = 4'd0;
+reg [3:0] vns_bankmachine6_next_state = 4'd0;
+reg [3:0] vns_bankmachine7_state = 4'd0;
+reg [3:0] vns_bankmachine7_next_state = 4'd0;
+reg [3:0] vns_multiplexer_state = 4'd0;
+reg [3:0] vns_multiplexer_next_state = 4'd0;
+wire vns_roundrobin0_request;
+wire vns_roundrobin0_grant;
+wire vns_roundrobin0_ce;
+wire vns_roundrobin1_request;
+wire vns_roundrobin1_grant;
+wire vns_roundrobin1_ce;
+wire vns_roundrobin2_request;
+wire vns_roundrobin2_grant;
+wire vns_roundrobin2_ce;
+wire vns_roundrobin3_request;
+wire vns_roundrobin3_grant;
+wire vns_roundrobin3_ce;
+wire vns_roundrobin4_request;
+wire vns_roundrobin4_grant;
+wire vns_roundrobin4_ce;
+wire vns_roundrobin5_request;
+wire vns_roundrobin5_grant;
+wire vns_roundrobin5_ce;
+wire vns_roundrobin6_request;
+wire vns_roundrobin6_grant;
+wire vns_roundrobin6_ce;
+wire vns_roundrobin7_request;
+wire vns_roundrobin7_grant;
+wire vns_roundrobin7_ce;
+reg vns_locked0 = 1'd0;
+reg vns_locked1 = 1'd0;
+reg vns_locked2 = 1'd0;
+reg vns_locked3 = 1'd0;
+reg vns_locked4 = 1'd0;
+reg vns_locked5 = 1'd0;
+reg vns_locked6 = 1'd0;
+reg vns_locked7 = 1'd0;
+reg vns_new_master_wdata_ready0 = 1'd0;
+reg vns_new_master_wdata_ready1 = 1'd0;
+reg vns_new_master_wdata_ready2 = 1'd0;
+reg vns_new_master_rdata_valid0 = 1'd0;
+reg vns_new_master_rdata_valid1 = 1'd0;
+reg vns_new_master_rdata_valid2 = 1'd0;
+reg vns_new_master_rdata_valid3 = 1'd0;
+reg vns_new_master_rdata_valid4 = 1'd0;
+reg vns_new_master_rdata_valid5 = 1'd0;
+reg vns_new_master_rdata_valid6 = 1'd0;
+reg vns_new_master_rdata_valid7 = 1'd0;
+reg vns_new_master_rdata_valid8 = 1'd0;
+wire [13:0] vns_interface0_bank_bus_adr;
+wire vns_interface0_bank_bus_we;
+wire [31:0] vns_interface0_bank_bus_dat_w;
+reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0;
+wire vns_csrbank0_init_done0_re;
+wire vns_csrbank0_init_done0_r;
+wire vns_csrbank0_init_done0_we;
+wire vns_csrbank0_init_done0_w;
+wire vns_csrbank0_init_error0_re;
+wire vns_csrbank0_init_error0_r;
+wire vns_csrbank0_init_error0_we;
+wire vns_csrbank0_init_error0_w;
+wire vns_csrbank0_sel;
+wire [13:0] vns_interface1_bank_bus_adr;
+wire vns_interface1_bank_bus_we;
+wire [31:0] vns_interface1_bank_bus_dat_w;
+reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0;
+wire vns_csrbank1_half_sys8x_taps0_re;
+wire [4:0] vns_csrbank1_half_sys8x_taps0_r;
+wire vns_csrbank1_half_sys8x_taps0_we;
+wire [4:0] vns_csrbank1_half_sys8x_taps0_w;
+wire vns_csrbank1_wlevel_en0_re;
+wire vns_csrbank1_wlevel_en0_r;
+wire vns_csrbank1_wlevel_en0_we;
+wire vns_csrbank1_wlevel_en0_w;
+wire vns_csrbank1_dly_sel0_re;
+wire [1:0] vns_csrbank1_dly_sel0_r;
+wire vns_csrbank1_dly_sel0_we;
+wire [1:0] vns_csrbank1_dly_sel0_w;
+wire vns_csrbank1_sel;
+wire [13:0] vns_interface2_bank_bus_adr;
+wire vns_interface2_bank_bus_we;
+wire [31:0] vns_interface2_bank_bus_dat_w;
+reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0;
+wire vns_csrbank2_dfii_control0_re;
+wire [3:0] vns_csrbank2_dfii_control0_r;
+wire vns_csrbank2_dfii_control0_we;
+wire [3:0] vns_csrbank2_dfii_control0_w;
+wire vns_csrbank2_dfii_pi0_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi0_command0_r;
+wire vns_csrbank2_dfii_pi0_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi0_command0_w;
+wire vns_csrbank2_dfii_pi0_address0_re;
+wire [14:0] vns_csrbank2_dfii_pi0_address0_r;
+wire vns_csrbank2_dfii_pi0_address0_we;
+wire [14:0] vns_csrbank2_dfii_pi0_address0_w;
+wire vns_csrbank2_dfii_pi0_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r;
+wire vns_csrbank2_dfii_pi0_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w;
+wire vns_csrbank2_dfii_pi0_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r;
+wire vns_csrbank2_dfii_pi0_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w;
+wire vns_csrbank2_dfii_pi0_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi0_rddata_r;
+wire vns_csrbank2_dfii_pi0_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi0_rddata_w;
+wire vns_csrbank2_dfii_pi1_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi1_command0_r;
+wire vns_csrbank2_dfii_pi1_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi1_command0_w;
+wire vns_csrbank2_dfii_pi1_address0_re;
+wire [14:0] vns_csrbank2_dfii_pi1_address0_r;
+wire vns_csrbank2_dfii_pi1_address0_we;
+wire [14:0] vns_csrbank2_dfii_pi1_address0_w;
+wire vns_csrbank2_dfii_pi1_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r;
+wire vns_csrbank2_dfii_pi1_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w;
+wire vns_csrbank2_dfii_pi1_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r;
+wire vns_csrbank2_dfii_pi1_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w;
+wire vns_csrbank2_dfii_pi1_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi1_rddata_r;
+wire vns_csrbank2_dfii_pi1_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi1_rddata_w;
+wire vns_csrbank2_dfii_pi2_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi2_command0_r;
+wire vns_csrbank2_dfii_pi2_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi2_command0_w;
+wire vns_csrbank2_dfii_pi2_address0_re;
+wire [14:0] vns_csrbank2_dfii_pi2_address0_r;
+wire vns_csrbank2_dfii_pi2_address0_we;
+wire [14:0] vns_csrbank2_dfii_pi2_address0_w;
+wire vns_csrbank2_dfii_pi2_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r;
+wire vns_csrbank2_dfii_pi2_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w;
+wire vns_csrbank2_dfii_pi2_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r;
+wire vns_csrbank2_dfii_pi2_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w;
+wire vns_csrbank2_dfii_pi2_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi2_rddata_r;
+wire vns_csrbank2_dfii_pi2_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi2_rddata_w;
+wire vns_csrbank2_dfii_pi3_command0_re;
+wire [5:0] vns_csrbank2_dfii_pi3_command0_r;
+wire vns_csrbank2_dfii_pi3_command0_we;
+wire [5:0] vns_csrbank2_dfii_pi3_command0_w;
+wire vns_csrbank2_dfii_pi3_address0_re;
+wire [14:0] vns_csrbank2_dfii_pi3_address0_r;
+wire vns_csrbank2_dfii_pi3_address0_we;
+wire [14:0] vns_csrbank2_dfii_pi3_address0_w;
+wire vns_csrbank2_dfii_pi3_baddress0_re;
+wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r;
+wire vns_csrbank2_dfii_pi3_baddress0_we;
+wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w;
+wire vns_csrbank2_dfii_pi3_wrdata0_re;
+wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r;
+wire vns_csrbank2_dfii_pi3_wrdata0_we;
+wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w;
+wire vns_csrbank2_dfii_pi3_rddata_re;
+wire [31:0] vns_csrbank2_dfii_pi3_rddata_r;
+wire vns_csrbank2_dfii_pi3_rddata_we;
+wire [31:0] vns_csrbank2_dfii_pi3_rddata_w;
+wire vns_csrbank2_sel;
+wire [13:0] vns_adr;
+wire vns_we;
+wire [31:0] vns_dat_w;
+wire [31:0] vns_dat_r;
+reg vns_rhs_array_muxed0 = 1'd0;
+reg [14:0] vns_rhs_array_muxed1 = 15'd0;
+reg [2:0] vns_rhs_array_muxed2 = 3'd0;
+reg vns_rhs_array_muxed3 = 1'd0;
+reg vns_rhs_array_muxed4 = 1'd0;
+reg vns_rhs_array_muxed5 = 1'd0;
+reg vns_t_array_muxed0 = 1'd0;
+reg vns_t_array_muxed1 = 1'd0;
+reg vns_t_array_muxed2 = 1'd0;
+reg vns_rhs_array_muxed6 = 1'd0;
+reg [14:0] vns_rhs_array_muxed7 = 15'd0;
+reg [2:0] vns_rhs_array_muxed8 = 3'd0;
+reg vns_rhs_array_muxed9 = 1'd0;
+reg vns_rhs_array_muxed10 = 1'd0;
+reg vns_rhs_array_muxed11 = 1'd0;
+reg vns_t_array_muxed3 = 1'd0;
+reg vns_t_array_muxed4 = 1'd0;
+reg vns_t_array_muxed5 = 1'd0;
+reg [21:0] vns_rhs_array_muxed12 = 22'd0;
+reg vns_rhs_array_muxed13 = 1'd0;
+reg vns_rhs_array_muxed14 = 1'd0;
+reg [21:0] vns_rhs_array_muxed15 = 22'd0;
+reg vns_rhs_array_muxed16 = 1'd0;
+reg vns_rhs_array_muxed17 = 1'd0;
+reg [21:0] vns_rhs_array_muxed18 = 22'd0;
+reg vns_rhs_array_muxed19 = 1'd0;
+reg vns_rhs_array_muxed20 = 1'd0;
+reg [21:0] vns_rhs_array_muxed21 = 22'd0;
+reg vns_rhs_array_muxed22 = 1'd0;
+reg vns_rhs_array_muxed23 = 1'd0;
+reg [21:0] vns_rhs_array_muxed24 = 22'd0;
+reg vns_rhs_array_muxed25 = 1'd0;
+reg vns_rhs_array_muxed26 = 1'd0;
+reg [21:0] vns_rhs_array_muxed27 = 22'd0;
+reg vns_rhs_array_muxed28 = 1'd0;
+reg vns_rhs_array_muxed29 = 1'd0;
+reg [21:0] vns_rhs_array_muxed30 = 22'd0;
+reg vns_rhs_array_muxed31 = 1'd0;
+reg vns_rhs_array_muxed32 = 1'd0;
+reg [21:0] vns_rhs_array_muxed33 = 22'd0;
+reg vns_rhs_array_muxed34 = 1'd0;
+reg vns_rhs_array_muxed35 = 1'd0;
+reg [2:0] vns_array_muxed0 = 3'd0;
+reg [14:0] vns_array_muxed1 = 15'd0;
+reg vns_array_muxed2 = 1'd0;
+reg vns_array_muxed3 = 1'd0;
+reg vns_array_muxed4 = 1'd0;
+reg vns_array_muxed5 = 1'd0;
+reg vns_array_muxed6 = 1'd0;
+reg [2:0] vns_array_muxed7 = 3'd0;
+reg [14:0] vns_array_muxed8 = 15'd0;
+reg vns_array_muxed9 = 1'd0;
+reg vns_array_muxed10 = 1'd0;
+reg vns_array_muxed11 = 1'd0;
+reg vns_array_muxed12 = 1'd0;
+reg vns_array_muxed13 = 1'd0;
+reg [2:0] vns_array_muxed14 = 3'd0;
+reg [14:0] vns_array_muxed15 = 15'd0;
+reg vns_array_muxed16 = 1'd0;
+reg vns_array_muxed17 = 1'd0;
+reg vns_array_muxed18 = 1'd0;
+reg vns_array_muxed19 = 1'd0;
+reg vns_array_muxed20 = 1'd0;
+reg [2:0] vns_array_muxed21 = 3'd0;
+reg [14:0] vns_array_muxed22 = 15'd0;
+reg vns_array_muxed23 = 1'd0;
+reg vns_array_muxed24 = 1'd0;
+reg vns_array_muxed25 = 1'd0;
+reg vns_array_muxed26 = 1'd0;
+reg vns_array_muxed27 = 1'd0;
+wire vns_xilinxasyncresetsynchronizerimpl0;
+wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl1;
+wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl2;
+wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl2_expr;
+wire vns_xilinxasyncresetsynchronizerimpl3;
+wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl3_expr;
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
-assign init_done = init_done_storage;
-assign init_error = init_error_storage;
-assign wb_bus_adr = wb_ctrl_adr;
-assign wb_bus_dat_w = wb_ctrl_dat_w;
-assign wb_ctrl_dat_r = wb_bus_dat_r;
-assign wb_bus_sel = wb_ctrl_sel;
-assign wb_bus_cyc = wb_ctrl_cyc;
-assign wb_bus_stb = wb_ctrl_stb;
-assign wb_ctrl_ack = wb_bus_ack;
-assign wb_bus_we = wb_ctrl_we;
-assign wb_bus_cti = wb_ctrl_cti;
-assign wb_bus_bte = wb_ctrl_bte;
-assign wb_ctrl_err = wb_bus_err;
+assign init_done = soc_init_done_storage;
+assign init_error = soc_init_error_storage;
+assign soc_wb_bus_adr = wb_ctrl_adr;
+assign soc_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = soc_wb_bus_dat_r;
+assign soc_wb_bus_sel = wb_ctrl_sel;
+assign soc_wb_bus_cyc = wb_ctrl_cyc;
+assign soc_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = soc_wb_bus_ack;
+assign soc_wb_bus_we = wb_ctrl_we;
+assign soc_wb_bus_cti = wb_ctrl_cti;
+assign soc_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = soc_wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
-assign user_port_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = user_port_cmd_ready;
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = user_port_wdata_ready;
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = user_port_rdata_valid;
-assign user_port_rdata_ready = user_port_native_0_rdata_ready;
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
-assign litedramcore_dat_w = litedramcore_wishbone_dat_w;
-assign litedramcore_wishbone_dat_r = litedramcore_dat_r;
+assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready;
+assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready;
+assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid;
+assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data;
+assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w;
+assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r;
// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
- next_state <= 1'd0;
- next_state <= state;
- case (state)
+ vns_next_state <= 1'd0;
+ vns_next_state <= vns_state;
+ case (vns_state)
1'd1: begin
- next_state <= 1'd0;
+ vns_next_state <= 1'd0;
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- next_state <= 1'd1;
+ if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
+ vns_next_state <= 1'd1;
end
end
endcase
reg dummy_d_1;
// synthesis translate_on
always @(*) begin
- litedramcore_we <= 1'd0;
- case (state)
+ soc_litedramcore_adr <= 14'd0;
+ case (vns_state)
1'd1: begin
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
+ soc_litedramcore_adr <= soc_litedramcore_wishbone_adr;
end
end
endcase
reg dummy_d_2;
// synthesis translate_on
always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (state)
+ soc_litedramcore_we <= 1'd0;
+ case (vns_state)
1'd1: begin
- litedramcore_wishbone_ack <= 1'd1;
end
default: begin
+ if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
+ soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0));
+ end
end
endcase
// synthesis translate_off
reg dummy_d_3;
// synthesis translate_on
always @(*) begin
- litedramcore_adr <= 14'd0;
- case (state)
+ soc_litedramcore_wishbone_ack <= 1'd0;
+ case (vns_state)
1'd1: begin
+ soc_litedramcore_wishbone_ack <= 1'd1;
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr <= litedramcore_wishbone_adr;
- end
end
endcase
// synthesis translate_off
dummy_d_3 = dummy_s;
// synthesis translate_on
end
-assign sys_pll_reset = rst;
-assign pll_locked = sys_pll_locked;
-assign iodelay_pll_reset = rst;
-assign s7pll0_clkin = clk;
-assign sys_clk = s7pll0_clkout_buf0;
-assign sys4x_clk = s7pll0_clkout_buf1;
-assign sys4x_dqs_clk = s7pll0_clkout_buf2;
-assign s7pll1_clkin = clk;
-assign iodelay_clk = s7pll1_clkout_buf;
-assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0;
+assign soc_reset = rst;
+assign pll_locked = soc_locked;
+assign soc_clkin = clk;
+assign iodelay_clk = soc_clkout_buf0;
+assign sys_clk = soc_clkout_buf1;
+assign sys4x_clk = soc_clkout_buf2;
+assign sys4x_dqs_clk = soc_clkout_buf3;
+assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
// synthesis translate_off
reg dummy_d_4;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p0_rddata <= 32'd0;
- a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip0_o[0];
- a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip0_o[1];
- a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip1_o[0];
- a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip1_o[1];
- a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip2_o[0];
- a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip2_o[1];
- a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip3_o[0];
- a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip3_o[1];
- a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip4_o[0];
- a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip4_o[1];
- a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip5_o[0];
- a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip5_o[1];
- a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip6_o[0];
- a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip6_o[1];
- a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip7_o[0];
- a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip7_o[1];
- a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip8_o[0];
- a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip8_o[1];
- a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip9_o[0];
- a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip9_o[1];
- a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip10_o[0];
- a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip10_o[1];
- a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip11_o[0];
- a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip11_o[1];
- a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip12_o[0];
- a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip12_o[1];
- a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip13_o[0];
- a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip13_o[1];
- a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip14_o[0];
- a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip14_o[1];
- a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0];
- a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1];
+ soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
// synthesis translate_off
dummy_d_4 = dummy_s;
// synthesis translate_on
reg dummy_d_5;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p1_rddata <= 32'd0;
- a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip0_o[2];
- a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip0_o[3];
- a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip1_o[2];
- a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip1_o[3];
- a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip2_o[2];
- a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip2_o[3];
- a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip3_o[2];
- a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip3_o[3];
- a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip4_o[2];
- a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip4_o[3];
- a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip5_o[2];
- a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip5_o[3];
- a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip6_o[2];
- a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip6_o[3];
- a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip7_o[2];
- a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip7_o[3];
- a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip8_o[2];
- a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip8_o[3];
- a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip9_o[2];
- a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip9_o[3];
- a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip10_o[2];
- a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip10_o[3];
- a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip11_o[2];
- a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip11_o[3];
- a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip12_o[2];
- a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip12_o[3];
- a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip13_o[2];
- a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip13_o[3];
- a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip14_o[2];
- a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip14_o[3];
- a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2];
- a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3];
+ soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
// synthesis translate_off
dummy_d_5 = dummy_s;
// synthesis translate_on
reg dummy_d_6;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p2_rddata <= 32'd0;
- a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip0_o[4];
- a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip0_o[5];
- a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip1_o[4];
- a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip1_o[5];
- a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip2_o[4];
- a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip2_o[5];
- a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip3_o[4];
- a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip3_o[5];
- a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip4_o[4];
- a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip4_o[5];
- a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip5_o[4];
- a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip5_o[5];
- a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip6_o[4];
- a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip6_o[5];
- a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip7_o[4];
- a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip7_o[5];
- a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip8_o[4];
- a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip8_o[5];
- a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip9_o[4];
- a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip9_o[5];
- a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip10_o[4];
- a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip10_o[5];
- a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip11_o[4];
- a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip11_o[5];
- a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip12_o[4];
- a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip12_o[5];
- a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip13_o[4];
- a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip13_o[5];
- a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip14_o[4];
- a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip14_o[5];
- a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4];
- a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5];
+ soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
// synthesis translate_off
dummy_d_6 = dummy_s;
// synthesis translate_on
reg dummy_d_7;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dfi_p3_rddata <= 32'd0;
- a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip0_o[6];
- a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip0_o[7];
- a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip1_o[6];
- a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip1_o[7];
- a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip2_o[6];
- a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip2_o[7];
- a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip3_o[6];
- a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip3_o[7];
- a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip4_o[6];
- a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip4_o[7];
- a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip5_o[6];
- a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip5_o[7];
- a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip6_o[6];
- a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip6_o[7];
- a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip7_o[6];
- a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip7_o[7];
- a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip8_o[6];
- a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip8_o[7];
- a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip9_o[6];
- a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip9_o[7];
- a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip10_o[6];
- a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip10_o[7];
- a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip11_o[6];
- a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip11_o[7];
- a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip12_o[6];
- a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip12_o[7];
- a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip13_o[6];
- a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip13_o[7];
- a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip14_o[6];
- a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip14_o[7];
- a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6];
- a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7];
+ soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
// synthesis translate_off
dummy_d_7 = dummy_s;
// synthesis translate_on
end
-assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1;
-assign a7ddrphy_bitslip2_i = a7ddrphy_dq_i_data2;
-assign a7ddrphy_bitslip3_i = a7ddrphy_dq_i_data3;
-assign a7ddrphy_bitslip4_i = a7ddrphy_dq_i_data4;
-assign a7ddrphy_bitslip5_i = a7ddrphy_dq_i_data5;
-assign a7ddrphy_bitslip6_i = a7ddrphy_dq_i_data6;
-assign a7ddrphy_bitslip7_i = a7ddrphy_dq_i_data7;
-assign a7ddrphy_bitslip8_i = a7ddrphy_dq_i_data8;
-assign a7ddrphy_bitslip9_i = a7ddrphy_dq_i_data9;
-assign a7ddrphy_bitslip10_i = a7ddrphy_dq_i_data10;
-assign a7ddrphy_bitslip11_i = a7ddrphy_dq_i_data11;
-assign a7ddrphy_bitslip12_i = a7ddrphy_dq_i_data12;
-assign a7ddrphy_bitslip13_i = a7ddrphy_dq_i_data13;
-assign a7ddrphy_bitslip14_i = a7ddrphy_dq_i_data14;
-assign a7ddrphy_bitslip15_i = a7ddrphy_dq_i_data15;
-assign a7ddrphy_rddata_en = {a7ddrphy_rddata_en_last, a7ddrphy_dfi_p2_rddata_en};
-assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en};
-assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2];
+assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
+assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
+assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
+assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
+assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
+assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
+assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
+assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
+assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
+assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
+assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
+assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
+assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
+assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
+assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
+assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en};
+assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en};
+assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2];
// synthesis translate_off
reg dummy_d_8;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dqs_oe <= 1'd0;
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqs_oe <= 1'd1;
+ soc_a7ddrphy_dqs_oe <= 1'd0;
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqs_oe <= 1'd1;
end else begin
- a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+ soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe;
end
// synthesis translate_off
dummy_d_8 = dummy_s;
// synthesis translate_on
end
-assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2]));
-assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2]));
+assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2]));
+assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2]));
// synthesis translate_off
reg dummy_d_9;
// synthesis translate_on
always @(*) begin
- a7ddrphy_dqspattern_o0 <= 8'd0;
- a7ddrphy_dqspattern_o0 <= 7'd85;
- if (a7ddrphy_dqspattern0) begin
- a7ddrphy_dqspattern_o0 <= 5'd21;
+ soc_a7ddrphy_dqspattern_o0 <= 8'd0;
+ soc_a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (soc_a7ddrphy_dqspattern0) begin
+ soc_a7ddrphy_dqspattern_o0 <= 5'd21;
end
- if (a7ddrphy_dqspattern1) begin
- a7ddrphy_dqspattern_o0 <= 7'd84;
+ if (soc_a7ddrphy_dqspattern1) begin
+ soc_a7ddrphy_dqspattern_o0 <= 7'd84;
end
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqspattern_o0 <= 1'd0;
- if (a7ddrphy_wlevel_strobe_re) begin
- a7ddrphy_dqspattern_o0 <= 1'd1;
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (soc_a7ddrphy_wlevel_strobe_re) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd1;
end
end
// synthesis translate_off
reg dummy_d_10;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip0_o <= 8'd0;
- case (a7ddrphy_bitslip0_value)
+ soc_a7ddrphy_bitslip0_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip0_value)
1'd0: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[7:0];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[8:1];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[9:2];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[10:3];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[11:4];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[12:5];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[13:6];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15];
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_11;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip1_o <= 8'd0;
- case (a7ddrphy_bitslip1_value)
+ soc_a7ddrphy_bitslip1_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip1_value)
1'd0: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[7:0];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[8:1];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[9:2];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[10:3];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[11:4];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[12:5];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[13:6];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15];
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_12;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip2_o <= 8'd0;
- case (a7ddrphy_bitslip2_value)
+ soc_a7ddrphy_bitslip2_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip2_value)
1'd0: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[7:0];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[8:1];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[9:2];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[10:3];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[11:4];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[12:5];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[13:6];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15];
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_13;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip3_o <= 8'd0;
- case (a7ddrphy_bitslip3_value)
+ soc_a7ddrphy_bitslip3_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip3_value)
1'd0: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[7:0];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[8:1];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[9:2];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[10:3];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[11:4];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[12:5];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[13:6];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15];
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_14;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip4_o <= 8'd0;
- case (a7ddrphy_bitslip4_value)
+ soc_a7ddrphy_bitslip4_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip4_value)
1'd0: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[7:0];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[8:1];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[9:2];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[10:3];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[11:4];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[12:5];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[13:6];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15];
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_15;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip5_o <= 8'd0;
- case (a7ddrphy_bitslip5_value)
+ soc_a7ddrphy_bitslip5_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip5_value)
1'd0: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[7:0];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[8:1];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[9:2];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[10:3];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[11:4];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[12:5];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[13:6];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15];
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_16;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip6_o <= 8'd0;
- case (a7ddrphy_bitslip6_value)
+ soc_a7ddrphy_bitslip6_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip6_value)
1'd0: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[7:0];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[8:1];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[9:2];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[10:3];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[11:4];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[12:5];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[13:6];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15];
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_17;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip7_o <= 8'd0;
- case (a7ddrphy_bitslip7_value)
+ soc_a7ddrphy_bitslip7_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip7_value)
1'd0: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[7:0];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[8:1];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[9:2];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[10:3];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[11:4];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[12:5];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[13:6];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15];
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_18;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip8_o <= 8'd0;
- case (a7ddrphy_bitslip8_value)
+ soc_a7ddrphy_bitslip8_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip8_value)
1'd0: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[7:0];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[8:1];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[9:2];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[10:3];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[11:4];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[12:5];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[13:6];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15];
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_19;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip9_o <= 8'd0;
- case (a7ddrphy_bitslip9_value)
+ soc_a7ddrphy_bitslip9_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip9_value)
1'd0: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[7:0];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[8:1];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[9:2];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[10:3];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[11:4];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[12:5];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[13:6];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15];
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_20;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip10_o <= 8'd0;
- case (a7ddrphy_bitslip10_value)
+ soc_a7ddrphy_bitslip10_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip10_value)
1'd0: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[7:0];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[8:1];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[9:2];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[10:3];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[11:4];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[12:5];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[13:6];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15];
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_21;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip11_o <= 8'd0;
- case (a7ddrphy_bitslip11_value)
+ soc_a7ddrphy_bitslip11_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip11_value)
1'd0: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[7:0];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[8:1];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[9:2];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[10:3];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[11:4];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[12:5];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[13:6];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15];
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_22;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip12_o <= 8'd0;
- case (a7ddrphy_bitslip12_value)
+ soc_a7ddrphy_bitslip12_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip12_value)
1'd0: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[7:0];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[8:1];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[9:2];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[10:3];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[11:4];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[12:5];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[13:6];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15];
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_23;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip13_o <= 8'd0;
- case (a7ddrphy_bitslip13_value)
+ soc_a7ddrphy_bitslip13_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip13_value)
1'd0: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[7:0];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[8:1];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[9:2];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[10:3];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[11:4];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[12:5];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[13:6];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15];
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_24;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip14_o <= 8'd0;
- case (a7ddrphy_bitslip14_value)
+ soc_a7ddrphy_bitslip14_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip14_value)
1'd0: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[7:0];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[8:1];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[9:2];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[10:3];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[11:4];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[12:5];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[13:6];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15];
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[22:15];
end
endcase
// synthesis translate_off
reg dummy_d_25;
// synthesis translate_on
always @(*) begin
- a7ddrphy_bitslip15_o <= 8'd0;
- case (a7ddrphy_bitslip15_value)
+ soc_a7ddrphy_bitslip15_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip15_value)
1'd0: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[7:0];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
end
1'd1: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[8:1];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
end
2'd2: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[9:2];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
end
2'd3: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[10:3];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
end
3'd4: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[11:4];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
end
3'd5: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[12:5];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
end
3'd6: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[13:6];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
end
3'd7: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
end
4'd8: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[15:8];
end
4'd9: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[16:9];
end
4'd10: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[17:10];
end
4'd11: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[18:11];
end
4'd12: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[19:12];
end
4'd13: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[20:13];
end
4'd14: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[21:14];
end
4'd15: begin
- a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15];
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[22:15];
end
endcase
// synthesis translate_off
dummy_d_25 = dummy_s;
// synthesis translate_on
end
-assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
-assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
-assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
-assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
-assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
-assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
-assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
-assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
-assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
-assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
-assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
-assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
-assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
-assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
-assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
-assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
-assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
-assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
-assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
-assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
-assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
-assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
-assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
-assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
-assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
-assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
-assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
-assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
-assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
-assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
-assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
-assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
-assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
-assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
-assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
-assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
-assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
-assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
-assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
-assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
-assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
-assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
-assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
-assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
-assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
-assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
-assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
-assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
-assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
-assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
-assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
-assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
-assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
-assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
-assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
-assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
-assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
-assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
-assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
-assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
-assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
-assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
-assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
-assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
-assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
-assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
-assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
-assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
-assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
-assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
-assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
-assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
-assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
-assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
-assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
-assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
-assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
-assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
-assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
-assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
-assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
-assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
-assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
-assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
-assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
-assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
-assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
-assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
-assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
-assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
-assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
-assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
-assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
-assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
-assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
-assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
-assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
-assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
-assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
-assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
-assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
-assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
-assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
-assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
-assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
-assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
-assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
-assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
-assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
-assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
-assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
-assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
-assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
-assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
-assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
-assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
-assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
-assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
-assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
-assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
-assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
-assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
-assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
-assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
-assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
-assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
-assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+assign soc_a7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address;
+assign soc_a7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank;
+assign soc_a7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n;
+assign soc_a7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n;
+assign soc_a7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n;
+assign soc_a7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n;
+assign soc_a7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke;
+assign soc_a7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt;
+assign soc_a7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n;
+assign soc_a7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n;
+assign soc_a7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata;
+assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en;
+assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask;
+assign soc_a7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en;
+assign soc_litedramcore_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
+assign soc_litedramcore_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
+assign soc_a7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address;
+assign soc_a7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank;
+assign soc_a7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n;
+assign soc_a7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n;
+assign soc_a7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n;
+assign soc_a7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n;
+assign soc_a7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke;
+assign soc_a7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt;
+assign soc_a7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n;
+assign soc_a7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n;
+assign soc_a7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata;
+assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en;
+assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask;
+assign soc_a7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en;
+assign soc_litedramcore_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
+assign soc_litedramcore_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
+assign soc_a7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address;
+assign soc_a7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank;
+assign soc_a7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n;
+assign soc_a7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n;
+assign soc_a7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n;
+assign soc_a7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n;
+assign soc_a7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke;
+assign soc_a7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt;
+assign soc_a7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n;
+assign soc_a7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n;
+assign soc_a7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata;
+assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en;
+assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask;
+assign soc_a7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en;
+assign soc_litedramcore_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
+assign soc_litedramcore_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
+assign soc_a7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address;
+assign soc_a7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank;
+assign soc_a7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n;
+assign soc_a7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n;
+assign soc_a7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n;
+assign soc_a7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n;
+assign soc_a7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke;
+assign soc_a7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt;
+assign soc_a7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n;
+assign soc_a7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n;
+assign soc_a7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata;
+assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en;
+assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask;
+assign soc_a7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en;
+assign soc_litedramcore_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
+assign soc_litedramcore_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
+assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address;
+assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank;
+assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n;
+assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n;
+assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n;
+assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n;
+assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke;
+assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt;
+assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n;
+assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n;
+assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata;
+assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en;
+assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask;
+assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en;
+assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata;
+assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid;
+assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address;
+assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank;
+assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n;
+assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n;
+assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n;
+assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n;
+assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke;
+assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt;
+assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n;
+assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n;
+assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata;
+assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en;
+assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask;
+assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en;
+assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata;
+assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid;
+assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address;
+assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank;
+assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n;
+assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n;
+assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n;
+assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n;
+assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke;
+assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt;
+assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n;
+assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n;
+assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata;
+assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en;
+assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask;
+assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en;
+assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata;
+assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid;
+assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address;
+assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank;
+assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n;
+assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n;
+assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n;
+assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n;
+assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke;
+assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt;
+assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n;
+assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n;
+assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata;
+assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en;
+assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask;
+assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en;
+assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata;
+assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid;
// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_address <= 15'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ soc_litedramcore_master_p3_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
end else begin
- litedramcore_master_p2_address <= litedramcore_inti_p2_address;
+ soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n;
end
// synthesis translate_off
dummy_d_26 = dummy_s;
reg dummy_d_27;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
end else begin
- litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
end
// synthesis translate_off
dummy_d_27 = dummy_s;
reg dummy_d_28;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ soc_litedramcore_master_p3_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
end else begin
- litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
+ soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke;
end
// synthesis translate_off
dummy_d_28 = dummy_s;
reg dummy_d_29;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ soc_litedramcore_master_p3_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
end else begin
- litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
+ soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt;
end
// synthesis translate_off
dummy_d_29 = dummy_s;
reg dummy_d_30;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ soc_litedramcore_master_p3_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
end else begin
- litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
+ soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n;
end
// synthesis translate_off
dummy_d_30 = dummy_s;
reg dummy_d_31;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ soc_litedramcore_master_p3_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
end else begin
+ soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n;
end
// synthesis translate_off
dummy_d_31 = dummy_s;
reg dummy_d_32;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ soc_litedramcore_master_p3_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
end else begin
- litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
+ soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata;
end
// synthesis translate_off
dummy_d_32 = dummy_s;
reg dummy_d_33;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ soc_litedramcore_inti_p0_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
+ soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata;
end
// synthesis translate_off
dummy_d_33 = dummy_s;
reg dummy_d_34;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ soc_litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
end else begin
- litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
+ soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en;
end
// synthesis translate_off
dummy_d_34 = dummy_s;
reg dummy_d_35;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ soc_litedramcore_inti_p0_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
+ soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
end
// synthesis translate_off
dummy_d_35 = dummy_s;
reg dummy_d_36;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
end else begin
- litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
+ soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask;
end
// synthesis translate_off
dummy_d_36 = dummy_s;
reg dummy_d_37;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ soc_litedramcore_master_p3_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
end else begin
- litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
+ soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en;
end
// synthesis translate_off
dummy_d_37 = dummy_s;
reg dummy_d_38;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ soc_litedramcore_master_p0_address <= 15'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
end else begin
- litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
+ soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_38 = dummy_s;
reg dummy_d_39;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_slave_p3_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
end else begin
- litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_39 = dummy_s;
reg dummy_d_40;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ soc_litedramcore_master_p0_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
+ soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank;
end
// synthesis translate_off
dummy_d_40 = dummy_s;
reg dummy_d_41;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p0_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
end else begin
- litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_41 = dummy_s;
reg dummy_d_42;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ soc_litedramcore_master_p0_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
+ soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n;
end
// synthesis translate_off
dummy_d_42 = dummy_s;
reg dummy_d_43;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ soc_litedramcore_slave_p0_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
dummy_d_43 = dummy_s;
reg dummy_d_44;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_address <= 15'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ soc_litedramcore_master_p0_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
end else begin
- litedramcore_master_p3_address <= litedramcore_inti_p3_address;
+ soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n;
end
// synthesis translate_off
dummy_d_44 = dummy_s;
reg dummy_d_45;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ soc_litedramcore_master_p0_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
end else begin
- litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
+ soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n;
end
// synthesis translate_off
dummy_d_45 = dummy_s;
reg dummy_d_46;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
end else begin
- litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
dummy_d_46 = dummy_s;
reg dummy_d_47;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ soc_litedramcore_master_p0_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
end else begin
- litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
+ soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke;
end
// synthesis translate_off
dummy_d_47 = dummy_s;
reg dummy_d_48;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ soc_litedramcore_master_p0_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
end else begin
- litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
+ soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt;
end
// synthesis translate_off
dummy_d_48 = dummy_s;
reg dummy_d_49;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ soc_litedramcore_master_p0_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
end else begin
+ soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n;
end
// synthesis translate_off
dummy_d_49 = dummy_s;
reg dummy_d_50;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ soc_litedramcore_master_p0_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
end else begin
- litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
+ soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n;
end
// synthesis translate_off
dummy_d_50 = dummy_s;
reg dummy_d_51;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ soc_litedramcore_master_p0_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
end else begin
+ soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata;
end
// synthesis translate_off
dummy_d_51 = dummy_s;
reg dummy_d_52;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ soc_litedramcore_inti_p1_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
+ soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata;
end
// synthesis translate_off
dummy_d_52 = dummy_s;
reg dummy_d_53;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ soc_litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
end else begin
- litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
+ soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en;
end
// synthesis translate_off
dummy_d_53 = dummy_s;
reg dummy_d_54;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ soc_litedramcore_inti_p1_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
+ soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
end
// synthesis translate_off
dummy_d_54 = dummy_s;
reg dummy_d_55;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
end else begin
- litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
+ soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask;
end
// synthesis translate_off
dummy_d_55 = dummy_s;
reg dummy_d_56;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ soc_litedramcore_master_p0_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
end else begin
- litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
+ soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
dummy_d_56 = dummy_s;
reg dummy_d_57;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p1_address <= 15'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
end else begin
- litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
+ soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address;
end
// synthesis translate_off
dummy_d_57 = dummy_s;
reg dummy_d_58;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ soc_litedramcore_master_p1_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
+ soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank;
end
// synthesis translate_off
dummy_d_58 = dummy_s;
reg dummy_d_59;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p1_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
end else begin
- litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
dummy_d_59 = dummy_s;
reg dummy_d_60;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ soc_litedramcore_master_p1_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
+ soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
dummy_d_60 = dummy_s;
reg dummy_d_61;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ soc_litedramcore_master_p1_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
+ soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n;
end
// synthesis translate_off
dummy_d_61 = dummy_s;
reg dummy_d_62;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_address <= 15'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ soc_litedramcore_slave_p1_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
end else begin
- litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_62 = dummy_s;
reg dummy_d_63;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ soc_litedramcore_master_p1_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
end else begin
- litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+ soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n;
end
// synthesis translate_off
dummy_d_63 = dummy_s;
reg dummy_d_64;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
end else begin
- litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_64 = dummy_s;
reg dummy_d_65;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ soc_litedramcore_master_p1_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
end else begin
- litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+ soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke;
end
// synthesis translate_off
dummy_d_65 = dummy_s;
reg dummy_d_66;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ soc_litedramcore_master_p1_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
end else begin
- litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+ soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt;
end
// synthesis translate_off
dummy_d_66 = dummy_s;
reg dummy_d_67;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ soc_litedramcore_master_p1_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
end else begin
+ soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
dummy_d_67 = dummy_s;
reg dummy_d_68;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ soc_litedramcore_master_p1_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
end else begin
- litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+ soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n;
end
// synthesis translate_off
dummy_d_68 = dummy_s;
reg dummy_d_69;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ soc_litedramcore_master_p1_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
end else begin
+ soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata;
end
// synthesis translate_off
dummy_d_69 = dummy_s;
reg dummy_d_70;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ soc_litedramcore_inti_p2_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+ soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata;
end
// synthesis translate_off
dummy_d_70 = dummy_s;
reg dummy_d_71;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ soc_litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
end else begin
- litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
+ soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en;
end
// synthesis translate_off
dummy_d_71 = dummy_s;
reg dummy_d_72;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ soc_litedramcore_inti_p2_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+ soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
end
// synthesis translate_off
dummy_d_72 = dummy_s;
reg dummy_d_73;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ soc_litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
end else begin
- litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
+ soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask;
end
// synthesis translate_off
dummy_d_73 = dummy_s;
reg dummy_d_74;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ soc_litedramcore_master_p1_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+ soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en;
end
// synthesis translate_off
dummy_d_74 = dummy_s;
reg dummy_d_75;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p2_address <= 15'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
end else begin
- litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
+ soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address;
end
// synthesis translate_off
dummy_d_75 = dummy_s;
reg dummy_d_76;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ soc_litedramcore_master_p2_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
+ soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank;
end
// synthesis translate_off
dummy_d_76 = dummy_s;
reg dummy_d_77;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p2_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
end else begin
- litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n;
end
// synthesis translate_off
dummy_d_77 = dummy_s;
reg dummy_d_78;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ soc_litedramcore_master_p2_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
+ soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n;
end
// synthesis translate_off
dummy_d_78 = dummy_s;
reg dummy_d_79;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ soc_litedramcore_master_p2_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
+ soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n;
end
// synthesis translate_off
dummy_d_79 = dummy_s;
reg dummy_d_80;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_address <= 15'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ soc_litedramcore_slave_p2_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
end else begin
- litedramcore_master_p1_address <= litedramcore_inti_p1_address;
end
// synthesis translate_off
dummy_d_80 = dummy_s;
reg dummy_d_81;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ soc_litedramcore_master_p2_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
end else begin
- litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
+ soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n;
end
// synthesis translate_off
dummy_d_81 = dummy_s;
reg dummy_d_82;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
end else begin
- litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
dummy_d_82 = dummy_s;
reg dummy_d_83;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ soc_litedramcore_master_p2_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
end else begin
- litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
+ soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke;
end
// synthesis translate_off
dummy_d_83 = dummy_s;
reg dummy_d_84;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ soc_litedramcore_master_p2_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
end else begin
- litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
+ soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt;
end
// synthesis translate_off
dummy_d_84 = dummy_s;
reg dummy_d_85;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ soc_litedramcore_master_p2_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
end else begin
+ soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
dummy_d_85 = dummy_s;
reg dummy_d_86;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ soc_litedramcore_master_p2_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
end else begin
- litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
+ soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n;
end
// synthesis translate_off
dummy_d_86 = dummy_s;
reg dummy_d_87;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ soc_litedramcore_master_p2_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
end else begin
+ soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata;
end
// synthesis translate_off
dummy_d_87 = dummy_s;
reg dummy_d_88;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ soc_litedramcore_inti_p3_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
+ soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_88 = dummy_s;
reg dummy_d_89;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
end else begin
- litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
+ soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en;
end
// synthesis translate_off
dummy_d_89 = dummy_s;
reg dummy_d_90;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ soc_litedramcore_inti_p3_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
end else begin
- litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
+ soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
dummy_d_90 = dummy_s;
reg dummy_d_91;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
end else begin
- litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
+ soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask;
end
// synthesis translate_off
dummy_d_91 = dummy_s;
reg dummy_d_92;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ soc_litedramcore_master_p2_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
end else begin
- litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
+ soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
dummy_d_92 = dummy_s;
reg dummy_d_93;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ soc_litedramcore_master_p3_address <= 15'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
end else begin
- litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
+ soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address;
end
// synthesis translate_off
dummy_d_93 = dummy_s;
reg dummy_d_94;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ soc_litedramcore_master_p3_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+ soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank;
end
// synthesis translate_off
dummy_d_94 = dummy_s;
reg dummy_d_95;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
+ soc_litedramcore_master_p3_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
end else begin
- litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
dummy_d_95 = dummy_s;
reg dummy_d_96;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ soc_litedramcore_master_p3_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+ soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
dummy_d_96 = dummy_s;
reg dummy_d_97;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ soc_litedramcore_master_p3_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
+ soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n;
end
// synthesis translate_off
dummy_d_97 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p0_cke = litedramcore_storage[1];
-assign litedramcore_inti_p1_cke = litedramcore_storage[1];
-assign litedramcore_inti_p2_cke = litedramcore_storage[1];
-assign litedramcore_inti_p3_cke = litedramcore_storage[1];
-assign litedramcore_inti_p0_odt = litedramcore_storage[2];
-assign litedramcore_inti_p1_odt = litedramcore_storage[2];
-assign litedramcore_inti_p2_odt = litedramcore_storage[2];
-assign litedramcore_inti_p3_odt = litedramcore_storage[2];
-assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
+assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke;
+assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt;
+assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n;
+assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n;
// synthesis translate_off
reg dummy_d_98;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
+ soc_litedramcore_inti_p0_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]);
end else begin
- litedramcore_inti_p0_cas_n <= 1'd1;
+ soc_litedramcore_inti_p0_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_98 = dummy_s;
reg dummy_d_99;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+ soc_litedramcore_inti_p0_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]);
end else begin
- litedramcore_inti_p0_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p0_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_99 = dummy_s;
reg dummy_d_100;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
+ soc_litedramcore_inti_p0_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
end else begin
- litedramcore_inti_p0_ras_n <= 1'd1;
+ soc_litedramcore_inti_p0_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_100 = dummy_s;
reg dummy_d_101;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
+ soc_litedramcore_inti_p0_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]);
end else begin
- litedramcore_inti_p0_we_n <= 1'd1;
+ soc_litedramcore_inti_p0_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_101 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
-assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
-assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_inti_p0_wrdata_mask = 1'd0;
+assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage;
+assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
+assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]);
+assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]);
+assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
+assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0;
// synthesis translate_off
reg dummy_d_102;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
+ soc_litedramcore_inti_p1_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]);
end else begin
- litedramcore_inti_p1_cas_n <= 1'd1;
+ soc_litedramcore_inti_p1_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_102 = dummy_s;
reg dummy_d_103;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+ soc_litedramcore_inti_p1_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]);
end else begin
- litedramcore_inti_p1_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p1_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_103 = dummy_s;
reg dummy_d_104;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
+ soc_litedramcore_inti_p1_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
end else begin
- litedramcore_inti_p1_ras_n <= 1'd1;
+ soc_litedramcore_inti_p1_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_104 = dummy_s;
reg dummy_d_105;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
+ soc_litedramcore_inti_p1_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]);
end else begin
- litedramcore_inti_p1_we_n <= 1'd1;
+ soc_litedramcore_inti_p1_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_105 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
-assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
-assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_inti_p1_wrdata_mask = 1'd0;
+assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage;
+assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
+assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]);
+assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]);
+assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
+assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0;
// synthesis translate_off
reg dummy_d_106;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cas_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
+ soc_litedramcore_inti_p2_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]);
end else begin
- litedramcore_inti_p2_cas_n <= 1'd1;
+ soc_litedramcore_inti_p2_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_106 = dummy_s;
reg dummy_d_107;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
+ soc_litedramcore_inti_p2_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]);
end else begin
- litedramcore_inti_p2_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p2_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_107 = dummy_s;
reg dummy_d_108;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_ras_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
+ soc_litedramcore_inti_p2_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
end else begin
- litedramcore_inti_p2_ras_n <= 1'd1;
+ soc_litedramcore_inti_p2_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_108 = dummy_s;
reg dummy_d_109;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_we_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
+ soc_litedramcore_inti_p2_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]);
end else begin
- litedramcore_inti_p2_we_n <= 1'd1;
+ soc_litedramcore_inti_p2_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_109 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
-assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
-assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_inti_p2_wrdata_mask = 1'd0;
+assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage;
+assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
+assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]);
+assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]);
+assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
+assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0;
// synthesis translate_off
reg dummy_d_110;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cas_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
+ soc_litedramcore_inti_p3_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]);
end else begin
- litedramcore_inti_p3_cas_n <= 1'd1;
+ soc_litedramcore_inti_p3_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_110 = dummy_s;
reg dummy_d_111;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
+ soc_litedramcore_inti_p3_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]);
end else begin
- litedramcore_inti_p3_cs_n <= {1{1'd1}};
+ soc_litedramcore_inti_p3_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_111 = dummy_s;
reg dummy_d_112;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_ras_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
+ soc_litedramcore_inti_p3_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
end else begin
- litedramcore_inti_p3_ras_n <= 1'd1;
+ soc_litedramcore_inti_p3_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_112 = dummy_s;
reg dummy_d_113;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_we_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
+ soc_litedramcore_inti_p3_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]);
end else begin
- litedramcore_inti_p3_we_n <= 1'd1;
+ soc_litedramcore_inti_p3_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_113 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
-assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
-assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
-assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]);
-assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
-assign litedramcore_inti_p3_wrdata_mask = 1'd0;
-assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
-assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
-assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
-assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
-assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
-assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
-assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
-assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
-assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
-assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
-assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
-assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
-assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
-assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
-assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
-assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
-assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
-assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
-assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
-assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
-assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
-assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
-assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
-assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
-assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
-assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
-assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
-assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
-assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
-assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
-assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
-assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
-assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
-assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
-assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
-assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
-assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
-assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
-assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
-assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
-assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
-assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
-assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
-assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
-assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
-assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
-assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
-assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
-assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
-assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
-assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
-assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
-assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
-assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
-assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
-assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
-assign litedramcore_timer_wait = (~litedramcore_timer_done0);
-assign litedramcore_postponer_req_i = litedramcore_timer_done0;
-assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
-assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
-assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
-assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
-assign litedramcore_timer_done0 = litedramcore_timer_done1;
-assign litedramcore_timer_count0 = litedramcore_timer_count1;
-assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
-assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
-assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
-assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
-assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage;
+assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
+assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]);
+assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]);
+assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage;
+assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0;
+assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid;
+assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready;
+assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we;
+assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr;
+assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock;
+assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready;
+assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid;
+assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid;
+assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready;
+assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we;
+assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr;
+assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock;
+assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready;
+assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid;
+assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid;
+assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready;
+assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we;
+assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr;
+assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock;
+assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready;
+assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid;
+assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid;
+assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready;
+assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we;
+assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr;
+assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock;
+assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready;
+assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid;
+assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid;
+assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready;
+assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we;
+assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr;
+assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock;
+assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready;
+assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid;
+assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid;
+assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready;
+assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we;
+assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr;
+assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock;
+assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready;
+assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid;
+assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid;
+assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready;
+assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we;
+assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr;
+assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock;
+assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready;
+assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid;
+assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid;
+assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready;
+assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we;
+assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr;
+assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock;
+assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready;
+assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid;
+assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0);
+assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0;
+assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o;
+assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0;
+assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done);
+assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0);
+assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1;
+assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1;
+assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0));
+assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0));
+assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0);
+assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
+assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
// synthesis translate_off
reg dummy_d_114;
// synthesis translate_on
always @(*) begin
- refresher_next_state <= 2'd0;
- refresher_next_state <= refresher_state;
- case (refresher_state)
+ vns_refresher_next_state <= 2'd0;
+ vns_refresher_next_state <= vns_refresher_state;
+ case (vns_refresher_state)
1'd1: begin
- if (litedramcore_cmd_ready) begin
- refresher_next_state <= 2'd2;
+ if (soc_litedramcore_cmd_ready) begin
+ vns_refresher_next_state <= 2'd2;
end
end
2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- refresher_next_state <= 2'd3;
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ vns_refresher_next_state <= 2'd3;
end else begin
- refresher_next_state <= 1'd0;
+ vns_refresher_next_state <= 1'd0;
end
end
end
2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- refresher_next_state <= 1'd0;
+ if (soc_litedramcore_zqcs_executer_done) begin
+ vns_refresher_next_state <= 1'd0;
end
end
default: begin
if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- refresher_next_state <= 1'd1;
+ if (soc_litedramcore_wants_refresh) begin
+ vns_refresher_next_state <= 1'd1;
end
end
end
reg dummy_d_115;
// synthesis translate_on
always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_cmd_valid <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
+ soc_litedramcore_cmd_valid <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_cmd_valid <= 1'd1;
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ end else begin
+ soc_litedramcore_cmd_valid <= 1'd0;
+ end
+ end
end
2'd3: begin
+ soc_litedramcore_cmd_valid <= 1'd1;
+ if (soc_litedramcore_zqcs_executer_done) begin
+ soc_litedramcore_cmd_valid <= 1'd0;
+ end
end
default: begin
end
reg dummy_d_116;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_zqcs_executer_start <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
end
2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ soc_litedramcore_zqcs_executer_start <= 1'd1;
end else begin
- litedramcore_cmd_valid <= 1'd0;
end
end
end
2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
end
default: begin
end
reg dummy_d_117;
// synthesis translate_on
always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_cmd_last <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
end
2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
end else begin
+ soc_litedramcore_cmd_last <= 1'd1;
end
end
end
2'd3: begin
+ if (soc_litedramcore_zqcs_executer_done) begin
+ soc_litedramcore_cmd_last <= 1'd1;
+ end
end
default: begin
end
reg dummy_d_118;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (refresher_state)
+ soc_litedramcore_sequencer_start0 <= 1'd0;
+ case (vns_refresher_state)
1'd1: begin
+ if (soc_litedramcore_cmd_ready) begin
+ soc_litedramcore_sequencer_start0 <= 1'd1;
+ end
end
2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
end
2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
end
default: begin
end
dummy_d_118 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid;
+assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid);
+assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
// synthesis translate_off
reg dummy_d_119;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_119 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
-assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
-assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
+assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
// synthesis translate_off
reg dummy_d_120;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ soc_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_120 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_121;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_121 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_122;
// synthesis translate_on
always @(*) begin
- bankmachine0_next_state <= 4'd0;
- bankmachine0_next_state <= bankmachine0_state;
- case (bankmachine0_state)
+ vns_bankmachine0_next_state <= 4'd0;
+ vns_bankmachine0_next_state <= vns_bankmachine0_state;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- bankmachine0_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- bankmachine0_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ vns_bankmachine0_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- bankmachine0_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ if (soc_litedramcore_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- bankmachine0_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
+ vns_bankmachine0_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine0_next_state <= 3'd6;
+ vns_bankmachine0_next_state <= 3'd6;
end
3'd6: begin
- bankmachine0_next_state <= 2'd3;
+ vns_bankmachine0_next_state <= 2'd3;
end
3'd7: begin
- bankmachine0_next_state <= 4'd8;
+ vns_bankmachine0_next_state <= 4'd8;
end
4'd8: begin
- bankmachine0_next_state <= 1'd0;
+ vns_bankmachine0_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- bankmachine0_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ vns_bankmachine0_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- bankmachine0_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
+ vns_bankmachine0_next_state <= 2'd2;
end
end else begin
- bankmachine0_next_state <= 1'd1;
+ vns_bankmachine0_next_state <= 1'd1;
end
end else begin
- bankmachine0_next_state <= 2'd3;
+ vns_bankmachine0_next_state <= 2'd3;
end
end
end
reg dummy_d_123;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_124;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_125;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
+ soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_126;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_127;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_row_open <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_128;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_row_close <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_129;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_130;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_131;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
end else begin
end
end else begin
reg dummy_d_132;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_133;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_134;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
reg dummy_d_135;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (bankmachine0_state)
+ soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_135 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid;
+assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid);
+assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
// synthesis translate_off
reg dummy_d_136;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_136 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
-assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
-assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
+assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
// synthesis translate_off
reg dummy_d_137;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ soc_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_137 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_138;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_138 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_139;
// synthesis translate_on
always @(*) begin
- bankmachine1_next_state <= 4'd0;
- bankmachine1_next_state <= bankmachine1_state;
- case (bankmachine1_state)
+ vns_bankmachine1_next_state <= 4'd0;
+ vns_bankmachine1_next_state <= vns_bankmachine1_state;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- bankmachine1_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- bankmachine1_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ vns_bankmachine1_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- bankmachine1_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ if (soc_litedramcore_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- bankmachine1_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
+ vns_bankmachine1_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine1_next_state <= 3'd6;
+ vns_bankmachine1_next_state <= 3'd6;
end
3'd6: begin
- bankmachine1_next_state <= 2'd3;
+ vns_bankmachine1_next_state <= 2'd3;
end
3'd7: begin
- bankmachine1_next_state <= 4'd8;
+ vns_bankmachine1_next_state <= 4'd8;
end
4'd8: begin
- bankmachine1_next_state <= 1'd0;
+ vns_bankmachine1_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- bankmachine1_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ vns_bankmachine1_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- bankmachine1_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
+ vns_bankmachine1_next_state <= 2'd2;
end
end else begin
- bankmachine1_next_state <= 1'd1;
+ vns_bankmachine1_next_state <= 1'd1;
end
end else begin
- bankmachine1_next_state <= 2'd3;
+ vns_bankmachine1_next_state <= 2'd3;
end
end
end
reg dummy_d_140;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_141;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_142;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
reg dummy_d_143;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
+ soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_144;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_145;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_row_open <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_row_open <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_146;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_row_close <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_147;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_148;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_149;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
end
end else begin
end
reg dummy_d_150;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_151;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
reg dummy_d_152;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (bankmachine1_state)
+ soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_152 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid;
+assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
+assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
// synthesis translate_off
reg dummy_d_153;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_153 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
-assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
-assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
+assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
// synthesis translate_off
reg dummy_d_154;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ soc_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_154 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_155;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_155 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_156;
// synthesis translate_on
always @(*) begin
- bankmachine2_next_state <= 4'd0;
- bankmachine2_next_state <= bankmachine2_state;
- case (bankmachine2_state)
+ vns_bankmachine2_next_state <= 4'd0;
+ vns_bankmachine2_next_state <= vns_bankmachine2_state;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- bankmachine2_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- bankmachine2_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ vns_bankmachine2_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- bankmachine2_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ if (soc_litedramcore_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- bankmachine2_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
+ vns_bankmachine2_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine2_next_state <= 3'd6;
+ vns_bankmachine2_next_state <= 3'd6;
end
3'd6: begin
- bankmachine2_next_state <= 2'd3;
+ vns_bankmachine2_next_state <= 2'd3;
end
3'd7: begin
- bankmachine2_next_state <= 4'd8;
+ vns_bankmachine2_next_state <= 4'd8;
end
4'd8: begin
- bankmachine2_next_state <= 1'd0;
+ vns_bankmachine2_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- bankmachine2_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ vns_bankmachine2_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- bankmachine2_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
+ vns_bankmachine2_next_state <= 2'd2;
end
end else begin
- bankmachine2_next_state <= 1'd1;
+ vns_bankmachine2_next_state <= 1'd1;
end
end else begin
- bankmachine2_next_state <= 2'd3;
+ vns_bankmachine2_next_state <= 2'd3;
end
end
end
reg dummy_d_157;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_158;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_159;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
+ soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_160;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_161;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
reg dummy_d_162;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_row_open <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_row_open <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_163;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_row_close <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_164;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_165;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_166;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
end
end else begin
end
reg dummy_d_167;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_168;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
reg dummy_d_169;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (bankmachine2_state)
+ soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_169 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid;
+assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid);
+assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
// synthesis translate_off
reg dummy_d_170;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_170 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
-assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
-assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
+assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
// synthesis translate_off
reg dummy_d_171;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ soc_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_171 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_172;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_172 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_173;
// synthesis translate_on
always @(*) begin
- bankmachine3_next_state <= 4'd0;
- bankmachine3_next_state <= bankmachine3_state;
- case (bankmachine3_state)
+ vns_bankmachine3_next_state <= 4'd0;
+ vns_bankmachine3_next_state <= vns_bankmachine3_state;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- bankmachine3_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- bankmachine3_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ vns_bankmachine3_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- bankmachine3_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ if (soc_litedramcore_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- bankmachine3_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
+ vns_bankmachine3_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine3_next_state <= 3'd6;
+ vns_bankmachine3_next_state <= 3'd6;
end
3'd6: begin
- bankmachine3_next_state <= 2'd3;
+ vns_bankmachine3_next_state <= 2'd3;
end
3'd7: begin
- bankmachine3_next_state <= 4'd8;
+ vns_bankmachine3_next_state <= 4'd8;
end
4'd8: begin
- bankmachine3_next_state <= 1'd0;
+ vns_bankmachine3_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- bankmachine3_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ vns_bankmachine3_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- bankmachine3_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
+ vns_bankmachine3_next_state <= 2'd2;
end
end else begin
- bankmachine3_next_state <= 1'd1;
+ vns_bankmachine3_next_state <= 1'd1;
end
end else begin
- bankmachine3_next_state <= 2'd3;
+ vns_bankmachine3_next_state <= 2'd3;
end
end
end
reg dummy_d_174;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_175;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_176;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
+ soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_177;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_178;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_row_open <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_179;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_row_close <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_180;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_181;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_182;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_183;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
end
end else begin
end
reg dummy_d_184;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_185;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
reg dummy_d_186;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (bankmachine3_state)
+ soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_186 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid;
+assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
+assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
// synthesis translate_off
reg dummy_d_187;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_187 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
-assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
-assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
+assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
// synthesis translate_off
reg dummy_d_188;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ soc_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_188 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_189;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_189 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_190;
// synthesis translate_on
always @(*) begin
- bankmachine4_next_state <= 4'd0;
- bankmachine4_next_state <= bankmachine4_state;
- case (bankmachine4_state)
+ vns_bankmachine4_next_state <= 4'd0;
+ vns_bankmachine4_next_state <= vns_bankmachine4_state;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- bankmachine4_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- bankmachine4_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ vns_bankmachine4_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- bankmachine4_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ if (soc_litedramcore_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- bankmachine4_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
+ vns_bankmachine4_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine4_next_state <= 3'd6;
+ vns_bankmachine4_next_state <= 3'd6;
end
3'd6: begin
- bankmachine4_next_state <= 2'd3;
+ vns_bankmachine4_next_state <= 2'd3;
end
3'd7: begin
- bankmachine4_next_state <= 4'd8;
+ vns_bankmachine4_next_state <= 4'd8;
end
4'd8: begin
- bankmachine4_next_state <= 1'd0;
+ vns_bankmachine4_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- bankmachine4_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ vns_bankmachine4_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- bankmachine4_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
+ vns_bankmachine4_next_state <= 2'd2;
end
end else begin
- bankmachine4_next_state <= 1'd1;
+ vns_bankmachine4_next_state <= 1'd1;
end
end else begin
- bankmachine4_next_state <= 2'd3;
+ vns_bankmachine4_next_state <= 2'd3;
end
end
end
reg dummy_d_191;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_192;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_193;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
+ soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_194;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_195;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_row_open <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_196;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_row_close <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_197;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_198;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_199;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
end else begin
end
end else begin
reg dummy_d_200;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_201;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_202;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_203;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (bankmachine4_state)
+ soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_203 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid;
+assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid);
+assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
// synthesis translate_off
reg dummy_d_204;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_204 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
-assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
-assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
+assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
// synthesis translate_off
reg dummy_d_205;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ soc_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_205 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_206;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_206 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_207;
// synthesis translate_on
always @(*) begin
- bankmachine5_next_state <= 4'd0;
- bankmachine5_next_state <= bankmachine5_state;
- case (bankmachine5_state)
+ vns_bankmachine5_next_state <= 4'd0;
+ vns_bankmachine5_next_state <= vns_bankmachine5_state;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- bankmachine5_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- bankmachine5_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ vns_bankmachine5_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- bankmachine5_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ if (soc_litedramcore_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- bankmachine5_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
+ vns_bankmachine5_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine5_next_state <= 3'd6;
+ vns_bankmachine5_next_state <= 3'd6;
end
3'd6: begin
- bankmachine5_next_state <= 2'd3;
+ vns_bankmachine5_next_state <= 2'd3;
end
3'd7: begin
- bankmachine5_next_state <= 4'd8;
+ vns_bankmachine5_next_state <= 4'd8;
end
4'd8: begin
- bankmachine5_next_state <= 1'd0;
+ vns_bankmachine5_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- bankmachine5_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ vns_bankmachine5_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- bankmachine5_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
+ vns_bankmachine5_next_state <= 2'd2;
end
end else begin
- bankmachine5_next_state <= 1'd1;
+ vns_bankmachine5_next_state <= 1'd1;
end
end else begin
- bankmachine5_next_state <= 2'd3;
+ vns_bankmachine5_next_state <= 2'd3;
end
end
end
reg dummy_d_208;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_209;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_210;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
reg dummy_d_211;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
+ if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
+ soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_212;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_213;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_row_open <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_row_open <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_214;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_row_close <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_215;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_216;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_217;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
end
end else begin
end
reg dummy_d_218;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_219;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
reg dummy_d_220;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (bankmachine5_state)
+ soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_220 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid;
+assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
+assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
// synthesis translate_off
reg dummy_d_221;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_221 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
-assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
-assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
+assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
// synthesis translate_off
reg dummy_d_222;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ soc_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_222 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_223;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_223 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_224;
// synthesis translate_on
always @(*) begin
- bankmachine6_next_state <= 4'd0;
- bankmachine6_next_state <= bankmachine6_state;
- case (bankmachine6_state)
+ vns_bankmachine6_next_state <= 4'd0;
+ vns_bankmachine6_next_state <= vns_bankmachine6_state;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- bankmachine6_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- bankmachine6_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ vns_bankmachine6_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- bankmachine6_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ if (soc_litedramcore_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- bankmachine6_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
+ vns_bankmachine6_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine6_next_state <= 3'd6;
+ vns_bankmachine6_next_state <= 3'd6;
end
3'd6: begin
- bankmachine6_next_state <= 2'd3;
+ vns_bankmachine6_next_state <= 2'd3;
end
3'd7: begin
- bankmachine6_next_state <= 4'd8;
+ vns_bankmachine6_next_state <= 4'd8;
end
4'd8: begin
- bankmachine6_next_state <= 1'd0;
+ vns_bankmachine6_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- bankmachine6_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ vns_bankmachine6_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- bankmachine6_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
+ vns_bankmachine6_next_state <= 2'd2;
end
end else begin
- bankmachine6_next_state <= 1'd1;
+ vns_bankmachine6_next_state <= 1'd1;
end
end else begin
- bankmachine6_next_state <= 2'd3;
+ vns_bankmachine6_next_state <= 2'd3;
end
end
end
reg dummy_d_225;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_226;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_227;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
+ soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_228;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_229;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
reg dummy_d_230;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_row_open <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_row_open <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_231;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_row_close <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_232;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_233;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_234;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
end
end else begin
end
reg dummy_d_235;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_236;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
reg dummy_d_237;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (bankmachine6_state)
+ soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_237 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
-assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid;
+assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid);
+assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
// synthesis translate_off
reg dummy_d_238;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+ soc_litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+ if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
dummy_d_238 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
-assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
-assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write);
+assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
+assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
// synthesis translate_off
reg dummy_d_239;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ soc_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+ if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0);
end
end
// synthesis translate_off
dummy_d_239 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
reg dummy_d_240;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
dummy_d_240 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready);
// synthesis translate_off
reg dummy_d_241;
// synthesis translate_on
always @(*) begin
- bankmachine7_next_state <= 4'd0;
- bankmachine7_next_state <= bankmachine7_state;
- case (bankmachine7_state)
+ vns_bankmachine7_next_state <= 4'd0;
+ vns_bankmachine7_next_state <= vns_bankmachine7_state;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- bankmachine7_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd5;
end
end
end
2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- bankmachine7_next_state <= 3'd5;
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ vns_bankmachine7_next_state <= 3'd5;
end
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- bankmachine7_next_state <= 3'd7;
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ if (soc_litedramcore_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd7;
end
end
end
3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- bankmachine7_next_state <= 1'd0;
+ if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
+ vns_bankmachine7_next_state <= 1'd0;
end
end
3'd5: begin
- bankmachine7_next_state <= 3'd6;
+ vns_bankmachine7_next_state <= 3'd6;
end
3'd6: begin
- bankmachine7_next_state <= 2'd3;
+ vns_bankmachine7_next_state <= 2'd3;
end
3'd7: begin
- bankmachine7_next_state <= 4'd8;
+ vns_bankmachine7_next_state <= 4'd8;
end
4'd8: begin
- bankmachine7_next_state <= 1'd0;
+ vns_bankmachine7_next_state <= 1'd0;
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- bankmachine7_next_state <= 3'd4;
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ vns_bankmachine7_next_state <= 3'd4;
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- bankmachine7_next_state <= 2'd2;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
+ vns_bankmachine7_next_state <= 2'd2;
end
end else begin
- bankmachine7_next_state <= 1'd1;
+ vns_bankmachine7_next_state <= 1'd1;
end
end else begin
- bankmachine7_next_state <= 2'd3;
+ vns_bankmachine7_next_state <= 2'd3;
end
end
end
reg dummy_d_242;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_243;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_244;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
+ soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_245;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_246;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_row_open <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_247;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_row_close <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_248;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_249;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_250;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
end else begin
end
end else begin
reg dummy_d_251;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_252;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_253;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_254;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (bankmachine7_state)
+ soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
dummy_d_254 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
-assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
-assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
-assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
-assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
-assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
-assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
-assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
-assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
-assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
-assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
-assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
-assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
+assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
+assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready);
+assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read));
+assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready;
+assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read));
+assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write));
+assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0);
+assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0);
+assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid;
+assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt);
+assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata};
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
+assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
// synthesis translate_off
reg dummy_d_255;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids <= 8'd0;
+ soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
// synthesis translate_off
dummy_d_255 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids;
+assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
+assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
+assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
+assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
// synthesis translate_off
reg dummy_d_256;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
end
// synthesis translate_off
dummy_d_256 = dummy_s;
reg dummy_d_257;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
end
// synthesis translate_off
dummy_d_257 = dummy_s;
reg dummy_d_258;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
end
// synthesis translate_off
dummy_d_258 = dummy_s;
reg dummy_d_259;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_259 = dummy_s;
reg dummy_d_260;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_260 = dummy_s;
reg dummy_d_261;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_261 = dummy_s;
reg dummy_d_262;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_262 = dummy_s;
reg dummy_d_263;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_263 = dummy_s;
reg dummy_d_264;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_264 = dummy_s;
reg dummy_d_265;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_265 = dummy_s;
reg dummy_d_266;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
end
// synthesis translate_off
dummy_d_266 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid));
// synthesis translate_off
reg dummy_d_267;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids <= 8'd0;
+ soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
// synthesis translate_off
dummy_d_267 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids;
+assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6;
+assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
+assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
+assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
+assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
+assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
// synthesis translate_off
reg dummy_d_268;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
end
// synthesis translate_off
dummy_d_268 = dummy_s;
reg dummy_d_269;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
end
// synthesis translate_off
dummy_d_269 = dummy_s;
reg dummy_d_270;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ soc_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5;
end
// synthesis translate_off
dummy_d_270 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
-assign litedramcore_dfi_p0_reset_n = 1'd1;
-assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
-assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
-assign litedramcore_dfi_p1_reset_n = 1'd1;
-assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
-assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
-assign litedramcore_dfi_p2_reset_n = 1'd1;
-assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
-assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
-assign litedramcore_dfi_p3_reset_n = 1'd1;
-assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
-assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
-assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid));
+assign soc_litedramcore_dfi_p0_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}};
+assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}};
+assign soc_litedramcore_dfi_p1_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}};
+assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}};
+assign soc_litedramcore_dfi_p2_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}};
+assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}};
+assign soc_litedramcore_dfi_p3_reset_n = 1'd1;
+assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}};
+assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}};
+assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
// synthesis translate_off
reg dummy_d_271;
// synthesis translate_on
always @(*) begin
- multiplexer_next_state <= 4'd0;
- multiplexer_next_state <= multiplexer_state;
- case (multiplexer_state)
+ vns_multiplexer_next_state <= 4'd0;
+ vns_multiplexer_next_state <= vns_multiplexer_state;
+ case (vns_multiplexer_state)
1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- multiplexer_next_state <= 2'd3;
+ if (soc_litedramcore_read_available) begin
+ if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
+ vns_multiplexer_next_state <= 2'd3;
end
end
- if (litedramcore_go_to_refresh) begin
- multiplexer_next_state <= 2'd2;
+ if (soc_litedramcore_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
end
end
2'd2: begin
- if (litedramcore_cmd_last) begin
- multiplexer_next_state <= 1'd0;
+ if (soc_litedramcore_cmd_last) begin
+ vns_multiplexer_next_state <= 1'd0;
end
end
2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- multiplexer_next_state <= 1'd0;
+ if (soc_litedramcore_twtrcon_ready) begin
+ vns_multiplexer_next_state <= 1'd0;
end
end
3'd4: begin
- multiplexer_next_state <= 3'd5;
+ vns_multiplexer_next_state <= 3'd5;
end
3'd5: begin
- multiplexer_next_state <= 3'd6;
+ vns_multiplexer_next_state <= 3'd6;
end
3'd6: begin
- multiplexer_next_state <= 3'd7;
+ vns_multiplexer_next_state <= 3'd7;
end
3'd7: begin
- multiplexer_next_state <= 4'd8;
+ vns_multiplexer_next_state <= 4'd8;
end
4'd8: begin
- multiplexer_next_state <= 4'd9;
+ vns_multiplexer_next_state <= 4'd9;
end
4'd9: begin
- multiplexer_next_state <= 4'd10;
+ vns_multiplexer_next_state <= 4'd10;
end
4'd10: begin
- multiplexer_next_state <= 1'd1;
+ vns_multiplexer_next_state <= 1'd1;
end
default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- multiplexer_next_state <= 3'd4;
+ if (soc_litedramcore_write_available) begin
+ if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
+ vns_multiplexer_next_state <= 3'd4;
end
end
- if (litedramcore_go_to_refresh) begin
- multiplexer_next_state <= 2'd2;
+ if (soc_litedramcore_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
end
end
endcase
reg dummy_d_272;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+ end
end
2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+ end
end
endcase
// synthesis translate_off
reg dummy_d_273;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel3 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
+ soc_litedramcore_steerer_sel3 <= 2'd2;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel1 <= 1'd1;
+ soc_litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_274;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_en0 <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel2 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel2 <= 2'd2;
+ soc_litedramcore_en0 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_275;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
end
2'd2: begin
+ soc_litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
end
endcase
// synthesis translate_off
reg dummy_d_276;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel3 <= 2'd2;
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel3 <= 1'd0;
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+ end
end
endcase
// synthesis translate_off
reg dummy_d_277;
// synthesis translate_on
always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_req_want_reads <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
end
2'd2: begin
4'd10: begin
end
default: begin
- litedramcore_en0 <= 1'd1;
+ soc_litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_278;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_req_want_writes <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
+ soc_litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
reg dummy_d_279;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
if (1'd0) begin
+ soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
end
end
2'd2: begin
end
default: begin
if (1'd0) begin
+ soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
end
end
endcase
reg dummy_d_280;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_en1 <= 1'd0;
+ case (vns_multiplexer_state)
1'd1: begin
+ soc_litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_281;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel0 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
+ soc_litedramcore_steerer_sel0 <= 1'd0;
end
2'd2: begin
+ soc_litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
+ soc_litedramcore_steerer_sel0 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_282;
// synthesis translate_on
always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel1 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- litedramcore_en1 <= 1'd1;
+ soc_litedramcore_steerer_sel1 <= 1'd0;
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ soc_litedramcore_steerer_sel1 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_283;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (multiplexer_state)
+ soc_litedramcore_steerer_sel2 <= 2'd0;
+ case (vns_multiplexer_state)
1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
+ soc_litedramcore_steerer_sel2 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
+ soc_litedramcore_steerer_sel2 <= 2'd2;
end
endcase
// synthesis translate_off
dummy_d_283 = dummy_s;
// synthesis translate_on
end
-assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
-assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
-assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
-assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
-assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
-assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
-assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
-assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
-assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
-assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
-assign user_port_wdata_ready = new_master_wdata_ready2;
-assign user_port_rdata_valid = new_master_rdata_valid8;
+assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
+assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12;
+assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13;
+assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14;
+assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
+assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15;
+assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16;
+assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17;
+assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
+assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18;
+assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19;
+assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20;
+assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
+assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21;
+assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22;
+assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23;
+assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
+assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24;
+assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25;
+assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26;
+assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
+assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27;
+assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28;
+assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29;
+assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
+assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30;
+assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31;
+assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32;
+assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
+assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
+assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33;
+assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34;
+assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35;
+assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
+assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2;
+assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8;
// synthesis translate_off
reg dummy_d_284;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
- case ({new_master_wdata_ready2})
+ soc_litedramcore_interface_wdata <= 128'd0;
+ case ({vns_new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
end
default: begin
- litedramcore_interface_wdata_we <= 1'd0;
+ soc_litedramcore_interface_wdata <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_285;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
- case ({new_master_wdata_ready2})
+ soc_litedramcore_interface_wdata_we <= 16'd0;
+ case ({vns_new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
end
default: begin
- litedramcore_interface_wdata <= 1'd0;
+ soc_litedramcore_interface_wdata_we <= 1'd0;
end
endcase
// synthesis translate_off
dummy_d_285 = dummy_s;
// synthesis translate_on
end
-assign user_port_rdata_payload_data = litedramcore_interface_rdata;
-assign roundrobin0_grant = 1'd0;
-assign roundrobin1_grant = 1'd0;
-assign roundrobin2_grant = 1'd0;
-assign roundrobin3_grant = 1'd0;
-assign roundrobin4_grant = 1'd0;
-assign roundrobin5_grant = 1'd0;
-assign roundrobin6_grant = 1'd0;
-assign roundrobin7_grant = 1'd0;
-assign litedramcore_wishbone_adr = wb_bus_adr;
-assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
-assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
-assign litedramcore_wishbone_sel = wb_bus_sel;
-assign litedramcore_wishbone_cyc = wb_bus_cyc;
-assign litedramcore_wishbone_stb = wb_bus_stb;
-assign wb_bus_ack = litedramcore_wishbone_ack;
-assign litedramcore_wishbone_we = wb_bus_we;
-assign litedramcore_wishbone_cti = wb_bus_cti;
-assign litedramcore_wishbone_bte = wb_bus_bte;
-assign wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
-assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0));
-assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0));
-assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1));
-assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1));
-assign csrbank0_init_done0_w = init_done_storage;
-assign csrbank0_init_error0_w = init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
-assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
-assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0));
-assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0));
-assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
-assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1));
-assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1));
-assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2));
-assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2));
-assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3));
-assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3));
-assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4));
-assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4));
-assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
-assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5));
-assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5));
-assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6));
-assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6));
-assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7));
-assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7));
-assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9));
-assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9));
-assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
-assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
-assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1);
-assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
-assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0));
-assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0));
-assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1));
-assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1));
-assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2));
-assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3));
-assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3));
-assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4));
-assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4));
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5));
-assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5));
-assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6));
-assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6));
-assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7));
-assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7));
-assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8));
-assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9));
-assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9));
-assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10));
-assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10));
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11));
-assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11));
-assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12));
-assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12));
-assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13));
-assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13));
-assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14));
-assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15));
-assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15));
-assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16));
-assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16));
-assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17));
-assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17));
-assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18));
-assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18));
-assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19));
-assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19));
-assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20));
-assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21));
-assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21));
-assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22));
-assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22));
-assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23));
-assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23));
-assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24));
-assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24));
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
-assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we;
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
-assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we;
-assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0];
-assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
-assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we;
-assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0];
-assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
-assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
-assign adr = litedramcore_adr;
-assign we = litedramcore_we;
-assign dat_w = litedramcore_dat_w;
-assign litedramcore_dat_r = dat_r;
-assign interface0_bank_bus_adr = adr;
-assign interface1_bank_bus_adr = adr;
-assign interface2_bank_bus_adr = adr;
-assign interface0_bank_bus_we = we;
-assign interface1_bank_bus_we = we;
-assign interface2_bank_bus_we = we;
-assign interface0_bank_bus_dat_w = dat_w;
-assign interface1_bank_bus_dat_w = dat_w;
-assign interface2_bank_bus_dat_w = dat_w;
-assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata;
+assign vns_roundrobin0_grant = 1'd0;
+assign vns_roundrobin1_grant = 1'd0;
+assign vns_roundrobin2_grant = 1'd0;
+assign vns_roundrobin3_grant = 1'd0;
+assign vns_roundrobin4_grant = 1'd0;
+assign vns_roundrobin5_grant = 1'd0;
+assign vns_roundrobin6_grant = 1'd0;
+assign vns_roundrobin7_grant = 1'd0;
+assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr;
+assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
+assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r;
+assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel;
+assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc;
+assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb;
+assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack;
+assign soc_litedramcore_wishbone_we = soc_wb_bus_we;
+assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti;
+assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte;
+assign soc_wb_bus_err = soc_litedramcore_wishbone_err;
+assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2);
+assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0];
+assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0];
+assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank0_init_done0_w = soc_init_done_storage;
+assign vns_csrbank0_init_error0_w = soc_init_error_storage;
+assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0);
+assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0];
+assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0];
+assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1));
+assign soc_a7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4));
+assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[1:0];
+assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5));
+assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9));
+assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9));
+assign vns_csrbank1_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign vns_csrbank1_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage;
+assign vns_csrbank1_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
+assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1);
+assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0];
+assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd1));
+assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd1));
+assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd2));
+assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd2));
+assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[14:0];
+assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank2_dfii_pi0_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi0_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank2_dfii_pi0_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd7));
+assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd7));
+assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd8));
+assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd8));
+assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[14:0];
+assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank2_dfii_pi1_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi1_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank2_dfii_pi1_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd13));
+assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd13));
+assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd14));
+assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd14));
+assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[14:0];
+assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd15));
+assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd15));
+assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd17));
+assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd17));
+assign vns_csrbank2_dfii_pi2_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi2_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd18));
+assign vns_csrbank2_dfii_pi2_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd18));
+assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0];
+assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd19));
+assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd19));
+assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd20));
+assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd20));
+assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[14:0];
+assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd21));
+assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd21));
+assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0];
+assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd22));
+assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd22));
+assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd23));
+assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd23));
+assign vns_csrbank2_dfii_pi3_rddata_r = vns_interface2_bank_bus_dat_w[31:0];
+assign vns_csrbank2_dfii_pi3_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd24));
+assign vns_csrbank2_dfii_pi3_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd24));
+assign soc_litedramcore_sel = soc_litedramcore_storage[0];
+assign soc_litedramcore_cke = soc_litedramcore_storage[1];
+assign soc_litedramcore_odt = soc_litedramcore_storage[2];
+assign soc_litedramcore_reset_n = soc_litedramcore_storage[3];
+assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0];
+assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0];
+assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[14:0];
+assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_status[31:0];
+assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata_we;
+assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0];
+assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[14:0];
+assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_status[31:0];
+assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata_we;
+assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0];
+assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[14:0];
+assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_status[31:0];
+assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata_we;
+assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0];
+assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[14:0];
+assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign vns_csrbank2_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_status[31:0];
+assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata_we;
+assign vns_adr = soc_litedramcore_adr;
+assign vns_we = soc_litedramcore_we;
+assign vns_dat_w = soc_litedramcore_dat_w;
+assign soc_litedramcore_dat_r = vns_dat_r;
+assign vns_interface0_bank_bus_adr = vns_adr;
+assign vns_interface1_bank_bus_adr = vns_adr;
+assign vns_interface2_bank_bus_adr = vns_adr;
+assign vns_interface0_bank_bus_we = vns_we;
+assign vns_interface1_bank_bus_we = vns_we;
+assign vns_interface2_bank_bus_we = vns_we;
+assign vns_interface0_bank_bus_dat_w = vns_dat_w;
+assign vns_interface1_bank_bus_dat_w = vns_dat_w;
+assign vns_interface2_bank_bus_dat_w = vns_dat_w;
+assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r);
// synthesis translate_off
reg dummy_d_286;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed0 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0];
end
1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1];
end
2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2];
end
2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3];
end
3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4];
end
3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5];
end
3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6];
end
default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7];
end
endcase
// synthesis translate_off
reg dummy_d_287;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed1 <= 15'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed1 <= 15'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_288;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed2 <= 3'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
// synthesis translate_off
reg dummy_d_289;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
// synthesis translate_off
reg dummy_d_290;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
// synthesis translate_off
reg dummy_d_291;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_rhs_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
// synthesis translate_off
reg dummy_d_292;
// synthesis translate_on
always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_t_array_muxed0 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
// synthesis translate_off
reg dummy_d_293;
// synthesis translate_on
always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_t_array_muxed1 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
// synthesis translate_off
reg dummy_d_294;
// synthesis translate_on
always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
+ vns_t_array_muxed2 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_295;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed6 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0];
end
1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1];
end
2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2];
end
2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3];
end
3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4];
end
3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5];
end
3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6];
end
default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7];
end
endcase
// synthesis translate_off
reg dummy_d_296;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed7 <= 15'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed7 <= 15'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_297;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed8 <= 3'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
// synthesis translate_off
reg dummy_d_298;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed9 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
// synthesis translate_off
reg dummy_d_299;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed10 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
// synthesis translate_off
reg dummy_d_300;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_rhs_array_muxed11 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
// synthesis translate_off
reg dummy_d_301;
// synthesis translate_on
always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_t_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
// synthesis translate_off
reg dummy_d_302;
// synthesis translate_on
always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_t_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
// synthesis translate_off
reg dummy_d_303;
// synthesis translate_on
always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
+ vns_t_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_304;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed12 <= 22'd0;
- case (roundrobin0_grant)
+ vns_rhs_array_muxed12 <= 22'd0;
+ case (vns_roundrobin0_grant)
default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_305;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (roundrobin0_grant)
+ vns_rhs_array_muxed13 <= 1'd0;
+ case (vns_roundrobin0_grant)
default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_306;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (roundrobin0_grant)
+ vns_rhs_array_muxed14 <= 1'd0;
+ case (vns_roundrobin0_grant)
default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_307;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed15 <= 22'd0;
- case (roundrobin1_grant)
+ vns_rhs_array_muxed15 <= 22'd0;
+ case (vns_roundrobin1_grant)
default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_308;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (roundrobin1_grant)
+ vns_rhs_array_muxed16 <= 1'd0;
+ case (vns_roundrobin1_grant)
default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_309;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (roundrobin1_grant)
+ vns_rhs_array_muxed17 <= 1'd0;
+ case (vns_roundrobin1_grant)
default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_310;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed18 <= 22'd0;
- case (roundrobin2_grant)
+ vns_rhs_array_muxed18 <= 22'd0;
+ case (vns_roundrobin2_grant)
default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_311;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (roundrobin2_grant)
+ vns_rhs_array_muxed19 <= 1'd0;
+ case (vns_roundrobin2_grant)
default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_312;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (roundrobin2_grant)
+ vns_rhs_array_muxed20 <= 1'd0;
+ case (vns_roundrobin2_grant)
default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_313;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed21 <= 22'd0;
- case (roundrobin3_grant)
+ vns_rhs_array_muxed21 <= 22'd0;
+ case (vns_roundrobin3_grant)
default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_314;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (roundrobin3_grant)
+ vns_rhs_array_muxed22 <= 1'd0;
+ case (vns_roundrobin3_grant)
default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_315;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (roundrobin3_grant)
+ vns_rhs_array_muxed23 <= 1'd0;
+ case (vns_roundrobin3_grant)
default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_316;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed24 <= 22'd0;
- case (roundrobin4_grant)
+ vns_rhs_array_muxed24 <= 22'd0;
+ case (vns_roundrobin4_grant)
default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_317;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (roundrobin4_grant)
+ vns_rhs_array_muxed25 <= 1'd0;
+ case (vns_roundrobin4_grant)
default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_318;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (roundrobin4_grant)
+ vns_rhs_array_muxed26 <= 1'd0;
+ case (vns_roundrobin4_grant)
default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_319;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed27 <= 22'd0;
- case (roundrobin5_grant)
+ vns_rhs_array_muxed27 <= 22'd0;
+ case (vns_roundrobin5_grant)
default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_320;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (roundrobin5_grant)
+ vns_rhs_array_muxed28 <= 1'd0;
+ case (vns_roundrobin5_grant)
default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_321;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (roundrobin5_grant)
+ vns_rhs_array_muxed29 <= 1'd0;
+ case (vns_roundrobin5_grant)
default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_322;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed30 <= 22'd0;
- case (roundrobin6_grant)
+ vns_rhs_array_muxed30 <= 22'd0;
+ case (vns_roundrobin6_grant)
default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_323;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (roundrobin6_grant)
+ vns_rhs_array_muxed31 <= 1'd0;
+ case (vns_roundrobin6_grant)
default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_324;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (roundrobin6_grant)
+ vns_rhs_array_muxed32 <= 1'd0;
+ case (vns_roundrobin6_grant)
default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_325;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed33 <= 22'd0;
- case (roundrobin7_grant)
+ vns_rhs_array_muxed33 <= 22'd0;
+ case (vns_roundrobin7_grant)
default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[24:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
// synthesis translate_off
reg dummy_d_326;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (roundrobin7_grant)
+ vns_rhs_array_muxed34 <= 1'd0;
+ case (vns_roundrobin7_grant)
default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
+ vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we;
end
endcase
// synthesis translate_off
reg dummy_d_327;
// synthesis translate_on
always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (roundrobin7_grant)
+ vns_rhs_array_muxed35 <= 1'd0;
+ case (vns_roundrobin7_grant)
default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
// synthesis translate_off
reg dummy_d_328;
// synthesis translate_on
always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed0 <= 3'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_329;
// synthesis translate_on
always @(*) begin
- array_muxed1 <= 15'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed1 <= 15'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
+ vns_array_muxed1 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
+ vns_array_muxed1 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_330;
// synthesis translate_on
always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed2 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed2 <= 1'd0;
+ vns_array_muxed2 <= 1'd0;
end
1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_331;
// synthesis translate_on
always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed3 <= 1'd0;
+ vns_array_muxed3 <= 1'd0;
end
1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_332;
// synthesis translate_on
always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed4 <= 1'd0;
+ vns_array_muxed4 <= 1'd0;
end
1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_333;
// synthesis translate_on
always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed5 <= 1'd0;
+ vns_array_muxed5 <= 1'd0;
end
1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_334;
// synthesis translate_on
always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
+ vns_array_muxed6 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
1'd0: begin
- array_muxed6 <= 1'd0;
+ vns_array_muxed6 <= 1'd0;
end
1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
reg dummy_d_335;
// synthesis translate_on
always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed7 <= 3'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_336;
// synthesis translate_on
always @(*) begin
- array_muxed8 <= 15'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed8 <= 15'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
+ vns_array_muxed8 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
+ vns_array_muxed8 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_337;
// synthesis translate_on
always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed9 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed9 <= 1'd0;
+ vns_array_muxed9 <= 1'd0;
end
1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_338;
// synthesis translate_on
always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed10 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed10 <= 1'd0;
+ vns_array_muxed10 <= 1'd0;
end
1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_339;
// synthesis translate_on
always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed11 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed11 <= 1'd0;
+ vns_array_muxed11 <= 1'd0;
end
1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_340;
// synthesis translate_on
always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed12 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed12 <= 1'd0;
+ vns_array_muxed12 <= 1'd0;
end
1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_341;
// synthesis translate_on
always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
+ vns_array_muxed13 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
1'd0: begin
- array_muxed13 <= 1'd0;
+ vns_array_muxed13 <= 1'd0;
end
1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
reg dummy_d_342;
// synthesis translate_on
always @(*) begin
- array_muxed14 <= 3'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed14 <= 3'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed14 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_343;
// synthesis translate_on
always @(*) begin
- array_muxed15 <= 15'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed15 <= 15'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed15 <= litedramcore_nop_a;
+ vns_array_muxed15 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed15 <= litedramcore_cmd_payload_a;
+ vns_array_muxed15 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_344;
// synthesis translate_on
always @(*) begin
- array_muxed16 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed16 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed16 <= 1'd0;
+ vns_array_muxed16 <= 1'd0;
end
1'd1: begin
- array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_345;
// synthesis translate_on
always @(*) begin
- array_muxed17 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed17 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed17 <= 1'd0;
+ vns_array_muxed17 <= 1'd0;
end
1'd1: begin
- array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_346;
// synthesis translate_on
always @(*) begin
- array_muxed18 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed18 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed18 <= 1'd0;
+ vns_array_muxed18 <= 1'd0;
end
1'd1: begin
- array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_347;
// synthesis translate_on
always @(*) begin
- array_muxed19 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed19 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed19 <= 1'd0;
+ vns_array_muxed19 <= 1'd0;
end
1'd1: begin
- array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_348;
// synthesis translate_on
always @(*) begin
- array_muxed20 <= 1'd0;
- case (litedramcore_steerer_sel2)
+ vns_array_muxed20 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
1'd0: begin
- array_muxed20 <= 1'd0;
+ vns_array_muxed20 <= 1'd0;
end
1'd1: begin
- array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
reg dummy_d_349;
// synthesis translate_on
always @(*) begin
- array_muxed21 <= 3'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed21 <= 3'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed21 <= litedramcore_nop_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
- array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+ vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
// synthesis translate_off
reg dummy_d_350;
// synthesis translate_on
always @(*) begin
- array_muxed22 <= 15'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed22 <= 15'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed22 <= litedramcore_nop_a;
+ vns_array_muxed22 <= soc_litedramcore_nop_a;
end
1'd1: begin
- array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+ vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+ vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
- array_muxed22 <= litedramcore_cmd_payload_a;
+ vns_array_muxed22 <= soc_litedramcore_cmd_payload_a;
end
endcase
// synthesis translate_off
reg dummy_d_351;
// synthesis translate_on
always @(*) begin
- array_muxed23 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed23 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed23 <= 1'd0;
+ vns_array_muxed23 <= 1'd0;
end
1'd1: begin
- array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
// synthesis translate_off
reg dummy_d_352;
// synthesis translate_on
always @(*) begin
- array_muxed24 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed24 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed24 <= 1'd0;
+ vns_array_muxed24 <= 1'd0;
end
1'd1: begin
- array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
// synthesis translate_off
reg dummy_d_353;
// synthesis translate_on
always @(*) begin
- array_muxed25 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed25 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed25 <= 1'd0;
+ vns_array_muxed25 <= 1'd0;
end
1'd1: begin
- array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
- array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
// synthesis translate_off
reg dummy_d_354;
// synthesis translate_on
always @(*) begin
- array_muxed26 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed26 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed26 <= 1'd0;
+ vns_array_muxed26 <= 1'd0;
end
1'd1: begin
- array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
// synthesis translate_off
reg dummy_d_355;
// synthesis translate_on
always @(*) begin
- array_muxed27 <= 1'd0;
- case (litedramcore_steerer_sel3)
+ vns_array_muxed27 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
1'd0: begin
- array_muxed27 <= 1'd0;
+ vns_array_muxed27 <= 1'd0;
end
1'd1: begin
- array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
// synthesis translate_off
dummy_d_355 = dummy_s;
// synthesis translate_on
end
-assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
-assign xilinxasyncresetsynchronizerimpl1 = ((~sys_pll_locked) | sys_pll_reset);
-assign xilinxasyncresetsynchronizerimpl2 = ((~sys_pll_locked) | sys_pll_reset);
-assign xilinxasyncresetsynchronizerimpl3 = ((~iodelay_pll_locked) | iodelay_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset);
+assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset);
+assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset);
+assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset);
always @(posedge iodelay_clk) begin
- if ((reset_counter != 1'd0)) begin
- reset_counter <= (reset_counter - 1'd1);
+ if ((soc_reset_counter != 1'd0)) begin
+ soc_reset_counter <= (soc_reset_counter - 1'd1);
end else begin
- ic_reset <= 1'd0;
+ soc_ic_reset <= 1'd0;
end
if (iodelay_rst) begin
- reset_counter <= 4'd15;
- ic_reset <= 1'd1;
+ soc_reset_counter <= 4'd15;
+ soc_ic_reset <= 1'd1;
end
end
always @(posedge sys_clk) begin
- state <= next_state;
- a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1);
- a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1);
- a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en;
- a7ddrphy_dfi_p0_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_dfi_p1_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_dfi_p2_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_dfi_p3_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
- a7ddrphy_wrdata_en_last <= a7ddrphy_wrdata_en;
- a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value <= (a7ddrphy_bitslip0_value + 1'd1);
+ vns_state <= vns_next_state;
+ soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en;
+ soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip0_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip0_value <= 1'd0;
end
- a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1);
+ soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip1_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip1_value <= 1'd0;
end
- a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1);
+ soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip2_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip2_value <= 1'd0;
end
- a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1);
+ soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip3_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip3_value <= 1'd0;
end
- a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1);
+ soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip4_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip4_value <= 1'd0;
end
- a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1);
+ soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip5_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip5_value <= 1'd0;
end
- a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1);
+ soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip6_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip6_value <= 1'd0;
end
- a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1);
+ soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip7_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip7_value <= 1'd0;
end
- a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1);
+ soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip8_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip8_value <= 1'd0;
end
- a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1);
+ soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip9_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip9_value <= 1'd0;
end
- a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1);
+ soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip10_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip10_value <= 1'd0;
end
- a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1);
+ soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip11_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip11_value <= 1'd0;
end
- a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1);
+ soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip12_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip12_value <= 1'd0;
end
- a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1);
+ soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip13_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip13_value <= 1'd0;
end
- a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1);
+ soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip14_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip14_value <= 1'd0;
end
- a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1);
+ soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[23:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
end
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
- a7ddrphy_bitslip15_value <= 1'd0;
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip15_value <= 1'd0;
end
- a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]};
- if (litedramcore_inti_p0_rddata_valid) begin
- litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
+ soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[23:8]};
+ if (soc_litedramcore_inti_p0_rddata_valid) begin
+ soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata;
end
- if (litedramcore_inti_p1_rddata_valid) begin
- litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata;
+ if (soc_litedramcore_inti_p1_rddata_valid) begin
+ soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata;
end
- if (litedramcore_inti_p2_rddata_valid) begin
- litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata;
+ if (soc_litedramcore_inti_p2_rddata_valid) begin
+ soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata;
end
- if (litedramcore_inti_p3_rddata_valid) begin
- litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata;
+ if (soc_litedramcore_inti_p3_rddata_valid) begin
+ soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata;
end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin
+ soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1);
end else begin
- litedramcore_timer_count1 <= 10'd781;
+ soc_litedramcore_timer_count1 <= 10'd781;
end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
+ soc_litedramcore_postponer_req_o <= 1'd0;
+ if (soc_litedramcore_postponer_req_i) begin
+ soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1);
+ if ((soc_litedramcore_postponer_count == 1'd0)) begin
+ soc_litedramcore_postponer_count <= 1'd0;
+ soc_litedramcore_postponer_req_o <= 1'd1;
end
end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
+ if (soc_litedramcore_sequencer_start0) begin
+ soc_litedramcore_sequencer_count <= 1'd0;
end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 6'd55)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 6'd55)) begin
- litedramcore_sequencer_counter <= 1'd0;
+ if (soc_litedramcore_sequencer_done1) begin
+ if ((soc_litedramcore_sequencer_count != 1'd0)) begin
+ soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd0;
+ if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin
+ soc_litedramcore_cmd_payload_a <= 11'd1024;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_sequencer_counter == 2'd3)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd1;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((soc_litedramcore_sequencer_counter == 6'd55)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((soc_litedramcore_sequencer_counter == 6'd55)) begin
+ soc_litedramcore_sequencer_counter <= 1'd0;
end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ if ((soc_litedramcore_sequencer_counter != 1'd0)) begin
+ soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1);
end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
+ if (soc_litedramcore_sequencer_start1) begin
+ soc_litedramcore_sequencer_counter <= 1'd1;
end
end
end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin
+ soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1);
end else begin
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
+ soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ soc_litedramcore_zqcs_executer_done <= 1'd0;
+ if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin
+ soc_litedramcore_cmd_payload_a <= 11'd1024;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
+ soc_litedramcore_zqcs_executer_counter <= 1'd0;
end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin
+ soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1);
end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
+ if (soc_litedramcore_zqcs_executer_start) begin
+ soc_litedramcore_zqcs_executer_counter <= 1'd1;
end
end
end
- refresher_state <= refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
+ vns_refresher_state <= vns_refresher_next_state;
+ if (soc_litedramcore_bankmachine0_row_close) begin
+ soc_litedramcore_bankmachine0_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine0_row_open) begin
+ soc_litedramcore_bankmachine0_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine0_twtpcon_valid) begin
+ soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine0_trccon_valid) begin
+ soc_litedramcore_bankmachine0_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin
+ soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine0_trascon_valid) begin
+ soc_litedramcore_bankmachine0_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
end
end
end
- bankmachine0_state <= bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
+ vns_bankmachine0_state <= vns_bankmachine0_next_state;
+ if (soc_litedramcore_bankmachine1_row_close) begin
+ soc_litedramcore_bankmachine1_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine1_row_open) begin
+ soc_litedramcore_bankmachine1_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine1_twtpcon_valid) begin
+ soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine1_trccon_valid) begin
+ soc_litedramcore_bankmachine1_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin
+ soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine1_trascon_valid) begin
+ soc_litedramcore_bankmachine1_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
end
end
end
- bankmachine1_state <= bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
+ vns_bankmachine1_state <= vns_bankmachine1_next_state;
+ if (soc_litedramcore_bankmachine2_row_close) begin
+ soc_litedramcore_bankmachine2_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine2_row_open) begin
+ soc_litedramcore_bankmachine2_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine2_twtpcon_valid) begin
+ soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine2_trccon_valid) begin
+ soc_litedramcore_bankmachine2_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin
+ soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine2_trascon_valid) begin
+ soc_litedramcore_bankmachine2_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
end
end
end
- bankmachine2_state <= bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
+ vns_bankmachine2_state <= vns_bankmachine2_next_state;
+ if (soc_litedramcore_bankmachine3_row_close) begin
+ soc_litedramcore_bankmachine3_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine3_row_open) begin
+ soc_litedramcore_bankmachine3_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine3_twtpcon_valid) begin
+ soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine3_trccon_valid) begin
+ soc_litedramcore_bankmachine3_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin
+ soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine3_trascon_valid) begin
+ soc_litedramcore_bankmachine3_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
end
end
end
- bankmachine3_state <= bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
+ vns_bankmachine3_state <= vns_bankmachine3_next_state;
+ if (soc_litedramcore_bankmachine4_row_close) begin
+ soc_litedramcore_bankmachine4_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine4_row_open) begin
+ soc_litedramcore_bankmachine4_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine4_twtpcon_valid) begin
+ soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine4_trccon_valid) begin
+ soc_litedramcore_bankmachine4_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin
+ soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine4_trascon_valid) begin
+ soc_litedramcore_bankmachine4_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
end
end
end
- bankmachine4_state <= bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
+ vns_bankmachine4_state <= vns_bankmachine4_next_state;
+ if (soc_litedramcore_bankmachine5_row_close) begin
+ soc_litedramcore_bankmachine5_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine5_row_open) begin
+ soc_litedramcore_bankmachine5_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine5_twtpcon_valid) begin
+ soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine5_trccon_valid) begin
+ soc_litedramcore_bankmachine5_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin
+ soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine5_trascon_valid) begin
+ soc_litedramcore_bankmachine5_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
end
end
end
- bankmachine5_state <= bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
+ vns_bankmachine5_state <= vns_bankmachine5_next_state;
+ if (soc_litedramcore_bankmachine6_row_close) begin
+ soc_litedramcore_bankmachine6_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine6_row_open) begin
+ soc_litedramcore_bankmachine6_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine6_twtpcon_valid) begin
+ soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine6_trccon_valid) begin
+ soc_litedramcore_bankmachine6_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin
+ soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine6_trascon_valid) begin
+ soc_litedramcore_bankmachine6_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
end
end
end
- bankmachine6_state <= bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
+ vns_bankmachine6_state <= vns_bankmachine6_next_state;
+ if (soc_litedramcore_bankmachine7_row_close) begin
+ soc_litedramcore_bankmachine7_row_opened <= 1'd0;
end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+ if (soc_litedramcore_bankmachine7_row_open) begin
+ soc_litedramcore_bankmachine7_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
end
end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+ if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+ if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
end
end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+ if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine7_twtpcon_valid) begin
+ soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 3'd5;
+ if (soc_litedramcore_bankmachine7_trccon_valid) begin
+ soc_litedramcore_bankmachine7_trccon_count <= 3'd5;
if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin
+ soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
end
end
end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (soc_litedramcore_bankmachine7_trascon_valid) begin
+ soc_litedramcore_bankmachine7_trascon_count <= 3'd4;
if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
end
end
end
- bankmachine7_state <= bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
+ vns_bankmachine7_state <= vns_bankmachine7_next_state;
+ if ((~soc_litedramcore_en0)) begin
+ soc_litedramcore_time0 <= 5'd31;
end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ if ((~soc_litedramcore_max_time0)) begin
+ soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1);
end
end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
+ if ((~soc_litedramcore_en1)) begin
+ soc_litedramcore_time1 <= 4'd15;
end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ if ((~soc_litedramcore_max_time1)) begin
+ soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1);
end
end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
+ if (soc_litedramcore_choose_cmd_ce) begin
+ case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end
end
end
end
end
1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end
end
end
end
end
2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end
end
end
end
end
2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end
end
end
end
end
3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end
end
end
end
end
3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end
end
end
end
end
3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end
end
end
end
end
3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
end
end
end
end
endcase
end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
+ if (soc_litedramcore_choose_req_ce) begin
+ case (soc_litedramcore_choose_req_grant)
1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end
end
end
end
end
1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end
end
end
end
end
2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end
end
end
end
end
2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end
end
end
end
end
3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end
end
end
end
end
3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end
end
end
end
end
3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end
end
end
end
end
3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
end
end
end
end
endcase
end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= array_muxed14;
- litedramcore_dfi_p2_address <= array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- litedramcore_dfi_p2_we_n <= (~array_muxed18);
- litedramcore_dfi_p2_rddata_en <= array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= array_muxed21;
- litedramcore_dfi_p3_address <= array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- litedramcore_dfi_p3_we_n <= (~array_muxed25);
- litedramcore_dfi_p3_rddata_en <= array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
+ soc_litedramcore_dfi_p0_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p0_bank <= vns_array_muxed0;
+ soc_litedramcore_dfi_p0_address <= vns_array_muxed1;
+ soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2);
+ soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3);
+ soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4);
+ soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5;
+ soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6;
+ soc_litedramcore_dfi_p1_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p1_bank <= vns_array_muxed7;
+ soc_litedramcore_dfi_p1_address <= vns_array_muxed8;
+ soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9);
+ soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10);
+ soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11);
+ soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12;
+ soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13;
+ soc_litedramcore_dfi_p2_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p2_bank <= vns_array_muxed14;
+ soc_litedramcore_dfi_p2_address <= vns_array_muxed15;
+ soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16);
+ soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17);
+ soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18);
+ soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19;
+ soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20;
+ soc_litedramcore_dfi_p3_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p3_bank <= vns_array_muxed21;
+ soc_litedramcore_dfi_p3_address <= vns_array_muxed22;
+ soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23);
+ soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24);
+ soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25);
+ soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26;
+ soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27;
+ if (soc_litedramcore_trrdcon_valid) begin
+ soc_litedramcore_trrdcon_count <= 1'd1;
if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
+ soc_litedramcore_trrdcon_ready <= 1'd1;
end else begin
- litedramcore_trrdcon_ready <= 1'd0;
+ soc_litedramcore_trrdcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
+ if ((~soc_litedramcore_trrdcon_ready)) begin
+ soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1);
+ if ((soc_litedramcore_trrdcon_count == 1'd1)) begin
+ soc_litedramcore_trrdcon_ready <= 1'd1;
end
end
end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid};
+ if ((soc_litedramcore_tfawcon_count < 3'd4)) begin
+ if ((soc_litedramcore_tfawcon_count == 2'd3)) begin
+ soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid);
end else begin
- litedramcore_tfawcon_ready <= 1'd1;
+ soc_litedramcore_tfawcon_ready <= 1'd1;
end
end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd0;
+ if (soc_litedramcore_tccdcon_valid) begin
+ soc_litedramcore_tccdcon_count <= 1'd0;
if (1'd1) begin
- litedramcore_tccdcon_ready <= 1'd1;
+ soc_litedramcore_tccdcon_ready <= 1'd1;
end else begin
- litedramcore_tccdcon_ready <= 1'd0;
+ soc_litedramcore_tccdcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
+ if ((~soc_litedramcore_tccdcon_ready)) begin
+ soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1);
+ if ((soc_litedramcore_tccdcon_count == 1'd1)) begin
+ soc_litedramcore_tccdcon_ready <= 1'd1;
end
end
end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd4;
+ if (soc_litedramcore_twtrcon_valid) begin
+ soc_litedramcore_twtrcon_count <= 3'd4;
if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
+ soc_litedramcore_twtrcon_ready <= 1'd1;
end else begin
- litedramcore_twtrcon_ready <= 1'd0;
+ soc_litedramcore_twtrcon_ready <= 1'd0;
end
end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- multiplexer_state <= multiplexer_next_state;
- new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- new_master_wdata_ready1 <= new_master_wdata_ready0;
- new_master_wdata_ready2 <= new_master_wdata_ready1;
- new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- new_master_rdata_valid1 <= new_master_rdata_valid0;
- new_master_rdata_valid2 <= new_master_rdata_valid1;
- new_master_rdata_valid3 <= new_master_rdata_valid2;
- new_master_rdata_valid4 <= new_master_rdata_valid3;
- new_master_rdata_valid5 <= new_master_rdata_valid4;
- new_master_rdata_valid6 <= new_master_rdata_valid5;
- new_master_rdata_valid7 <= new_master_rdata_valid6;
- new_master_rdata_valid8 <= new_master_rdata_valid7;
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[0])
+ if ((~soc_litedramcore_twtrcon_ready)) begin
+ soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1);
+ if ((soc_litedramcore_twtrcon_count == 1'd1)) begin
+ soc_litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_multiplexer_state <= vns_multiplexer_next_state;
+ vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
+ vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
+ vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
+ vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
+ vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
+ vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
+ vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
+ vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
+ vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
+ vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
+ vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
+ vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
+ vns_interface0_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank0_sel) begin
+ case (vns_interface0_bank_bus_adr[0])
1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w;
end
1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w;
end
endcase
end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
+ if (vns_csrbank0_init_done0_re) begin
+ soc_init_done_storage <= vns_csrbank0_init_done0_r;
end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
+ soc_init_done_re <= vns_csrbank0_init_done0_re;
+ if (vns_csrbank0_init_error0_re) begin
+ soc_init_error_storage <= vns_csrbank0_init_error0_r;
end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[3:0])
+ soc_init_error_re <= vns_csrbank0_init_error0_re;
+ vns_interface1_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank1_sel) begin
+ case (vns_interface1_bank_bus_adr[3:0])
1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w;
end
1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w;
end
2'd2: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w;
end
2'd3: begin
- interface1_bank_bus_dat_r <= a7ddrphy_cdly_rst_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
end
3'd4: begin
- interface1_bank_bus_dat_r <= a7ddrphy_cdly_inc_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
end
3'd5: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w;
end
3'd6: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
end
3'd7: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
end
4'd8: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
end
4'd9: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+ vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
end
endcase
end
- if (csrbank1_half_sys8x_taps0_re) begin
- a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+ if (vns_csrbank1_half_sys8x_taps0_re) begin
+ soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r;
end
- a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
- if (csrbank1_wlevel_en0_re) begin
- a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+ soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re;
+ if (vns_csrbank1_wlevel_en0_re) begin
+ soc_a7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r;
end
- a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
- if (csrbank1_dly_sel0_re) begin
- a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+ soc_a7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re;
+ if (vns_csrbank1_dly_sel0_re) begin
+ soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank1_dly_sel0_r;
end
- a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[4:0])
+ soc_a7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re;
+ vns_interface2_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank2_sel) begin
+ case (vns_interface2_bank_bus_adr[4:0])
1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w;
end
1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w;
end
2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w;
end
2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w;
end
3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w;
end
3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w;
end
3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata_w;
end
3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w;
end
4'd8: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
end
4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w;
end
4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w;
end
4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w;
end
4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata_w;
end
4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w;
end
4'd14: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
end
4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w;
end
5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w;
end
5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w;
end
5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata_w;
end
5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w;
end
5'd20: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w;
end
5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w;
end
5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w;
end
5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w;
end
5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata_w;
end
endcase
end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ if (vns_csrbank2_dfii_control0_re) begin
+ soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r;
end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ soc_litedramcore_re <= vns_csrbank2_dfii_control0_re;
+ if (vns_csrbank2_dfii_pi0_command0_re) begin
+ soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r;
end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+ soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re;
+ if (vns_csrbank2_dfii_pi0_address0_re) begin
+ soc_litedramcore_phaseinjector0_address_storage[14:0] <= vns_csrbank2_dfii_pi0_address0_r;
end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re;
+ if (vns_csrbank2_dfii_pi0_baddress0_re) begin
+ soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r;
end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re;
+ if (vns_csrbank2_dfii_pi0_wrdata0_re) begin
+ soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r;
end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re;
+ if (vns_csrbank2_dfii_pi1_command0_re) begin
+ soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r;
end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+ soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re;
+ if (vns_csrbank2_dfii_pi1_address0_re) begin
+ soc_litedramcore_phaseinjector1_address_storage[14:0] <= vns_csrbank2_dfii_pi1_address0_r;
end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re;
+ if (vns_csrbank2_dfii_pi1_baddress0_re) begin
+ soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r;
end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re;
+ if (vns_csrbank2_dfii_pi1_wrdata0_re) begin
+ soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r;
end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- if (csrbank2_dfii_pi2_command0_re) begin
- litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+ soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re;
+ if (vns_csrbank2_dfii_pi2_command0_re) begin
+ soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r;
end
- litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
+ soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re;
+ if (vns_csrbank2_dfii_pi2_address0_re) begin
+ soc_litedramcore_phaseinjector2_address_storage[14:0] <= vns_csrbank2_dfii_pi2_address0_r;
end
- litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
- if (csrbank2_dfii_pi2_baddress0_re) begin
- litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+ soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re;
+ if (vns_csrbank2_dfii_pi2_baddress0_re) begin
+ soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r;
end
- litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re;
+ if (vns_csrbank2_dfii_pi2_wrdata0_re) begin
+ soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r;
end
- litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
- if (csrbank2_dfii_pi3_command0_re) begin
- litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+ soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re;
+ if (vns_csrbank2_dfii_pi3_command0_re) begin
+ soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r;
end
- litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
+ soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re;
+ if (vns_csrbank2_dfii_pi3_address0_re) begin
+ soc_litedramcore_phaseinjector3_address_storage[14:0] <= vns_csrbank2_dfii_pi3_address0_r;
end
- litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
- if (csrbank2_dfii_pi3_baddress0_re) begin
- litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+ soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re;
+ if (vns_csrbank2_dfii_pi3_baddress0_re) begin
+ soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r;
end
- litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re;
+ if (vns_csrbank2_dfii_pi3_wrdata0_re) begin
+ soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r;
end
- litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+ soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re;
if (sys_rst) begin
- a7ddrphy_half_sys8x_taps_storage <= 5'd8;
- a7ddrphy_half_sys8x_taps_re <= 1'd0;
- a7ddrphy_wlevel_en_storage <= 1'd0;
- a7ddrphy_wlevel_en_re <= 1'd0;
- a7ddrphy_dly_sel_storage <= 2'd0;
- a7ddrphy_dly_sel_re <= 1'd0;
- a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
- a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
- a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
- a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
- a7ddrphy_dqs_oe_delayed <= 1'd0;
- a7ddrphy_dqspattern_o1 <= 8'd0;
- a7ddrphy_dq_oe_delayed <= 1'd0;
- a7ddrphy_bitslip0_value <= 4'd0;
- a7ddrphy_bitslip1_value <= 4'd0;
- a7ddrphy_bitslip2_value <= 4'd0;
- a7ddrphy_bitslip3_value <= 4'd0;
- a7ddrphy_bitslip4_value <= 4'd0;
- a7ddrphy_bitslip5_value <= 4'd0;
- a7ddrphy_bitslip6_value <= 4'd0;
- a7ddrphy_bitslip7_value <= 4'd0;
- a7ddrphy_bitslip8_value <= 4'd0;
- a7ddrphy_bitslip9_value <= 4'd0;
- a7ddrphy_bitslip10_value <= 4'd0;
- a7ddrphy_bitslip11_value <= 4'd0;
- a7ddrphy_bitslip12_value <= 4'd0;
- a7ddrphy_bitslip13_value <= 4'd0;
- a7ddrphy_bitslip14_value <= 4'd0;
- a7ddrphy_bitslip15_value <= 4'd0;
- a7ddrphy_rddata_en_last <= 8'd0;
- a7ddrphy_wrdata_en_last <= 4'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_status <= 32'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_status <= 32'd0;
- litedramcore_phaseinjector2_command_storage <= 6'd0;
- litedramcore_phaseinjector2_command_re <= 1'd0;
- litedramcore_phaseinjector2_address_re <= 1'd0;
- litedramcore_phaseinjector2_baddress_re <= 1'd0;
- litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- litedramcore_phaseinjector2_status <= 32'd0;
- litedramcore_phaseinjector3_command_storage <= 6'd0;
- litedramcore_phaseinjector3_command_re <= 1'd0;
- litedramcore_phaseinjector3_address_re <= 1'd0;
- litedramcore_phaseinjector3_baddress_re <= 1'd0;
- litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- litedramcore_phaseinjector3_status <= 32'd0;
- litedramcore_dfi_p0_address <= 15'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 15'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_dfi_p2_address <= 15'd0;
- litedramcore_dfi_p2_bank <= 3'd0;
- litedramcore_dfi_p2_cas_n <= 1'd1;
- litedramcore_dfi_p2_cs_n <= 1'd1;
- litedramcore_dfi_p2_ras_n <= 1'd1;
- litedramcore_dfi_p2_we_n <= 1'd1;
- litedramcore_dfi_p2_wrdata_en <= 1'd0;
- litedramcore_dfi_p2_rddata_en <= 1'd0;
- litedramcore_dfi_p3_address <= 15'd0;
- litedramcore_dfi_p3_bank <= 3'd0;
- litedramcore_dfi_p3_cas_n <= 1'd1;
- litedramcore_dfi_p3_cs_n <= 1'd1;
- litedramcore_dfi_p3_ras_n <= 1'd1;
- litedramcore_dfi_p3_we_n <= 1'd1;
- litedramcore_dfi_p3_wrdata_en <= 1'd0;
- litedramcore_dfi_p3_rddata_en <= 1'd0;
- litedramcore_timer_count1 <= 10'd781;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 6'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_row <= 15'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 3'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_row <= 15'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 3'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_row <= 15'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 3'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_row <= 15'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 3'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_row <= 15'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 3'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_row <= 15'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 3'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_row <= 15'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 3'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_row <= 15'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 3'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- state <= 1'd0;
- refresher_state <= 2'd0;
- bankmachine0_state <= 4'd0;
- bankmachine1_state <= 4'd0;
- bankmachine2_state <= 4'd0;
- bankmachine3_state <= 4'd0;
- bankmachine4_state <= 4'd0;
- bankmachine5_state <= 4'd0;
- bankmachine6_state <= 4'd0;
- bankmachine7_state <= 4'd0;
- multiplexer_state <= 4'd0;
- new_master_wdata_ready0 <= 1'd0;
- new_master_wdata_ready1 <= 1'd0;
- new_master_wdata_ready2 <= 1'd0;
- new_master_rdata_valid0 <= 1'd0;
- new_master_rdata_valid1 <= 1'd0;
- new_master_rdata_valid2 <= 1'd0;
- new_master_rdata_valid3 <= 1'd0;
- new_master_rdata_valid4 <= 1'd0;
- new_master_rdata_valid5 <= 1'd0;
- new_master_rdata_valid6 <= 1'd0;
- new_master_rdata_valid7 <= 1'd0;
- new_master_rdata_valid8 <= 1'd0;
+ soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ soc_a7ddrphy_wlevel_en_storage <= 1'd0;
+ soc_a7ddrphy_wlevel_en_re <= 1'd0;
+ soc_a7ddrphy_dly_sel_storage <= 2'd0;
+ soc_a7ddrphy_dly_sel_re <= 1'd0;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dqs_oe_delayed <= 1'd0;
+ soc_a7ddrphy_dqspattern_o1 <= 8'd0;
+ soc_a7ddrphy_dq_oe_delayed <= 1'd0;
+ soc_a7ddrphy_bitslip0_value <= 4'd0;
+ soc_a7ddrphy_bitslip1_value <= 4'd0;
+ soc_a7ddrphy_bitslip2_value <= 4'd0;
+ soc_a7ddrphy_bitslip3_value <= 4'd0;
+ soc_a7ddrphy_bitslip4_value <= 4'd0;
+ soc_a7ddrphy_bitslip5_value <= 4'd0;
+ soc_a7ddrphy_bitslip6_value <= 4'd0;
+ soc_a7ddrphy_bitslip7_value <= 4'd0;
+ soc_a7ddrphy_bitslip8_value <= 4'd0;
+ soc_a7ddrphy_bitslip9_value <= 4'd0;
+ soc_a7ddrphy_bitslip10_value <= 4'd0;
+ soc_a7ddrphy_bitslip11_value <= 4'd0;
+ soc_a7ddrphy_bitslip12_value <= 4'd0;
+ soc_a7ddrphy_bitslip13_value <= 4'd0;
+ soc_a7ddrphy_bitslip14_value <= 4'd0;
+ soc_a7ddrphy_bitslip15_value <= 4'd0;
+ soc_a7ddrphy_rddata_en_last <= 8'd0;
+ soc_a7ddrphy_wrdata_en_last <= 4'd0;
+ soc_litedramcore_storage <= 4'd1;
+ soc_litedramcore_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector0_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_status <= 32'd0;
+ soc_litedramcore_phaseinjector1_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector1_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_status <= 32'd0;
+ soc_litedramcore_phaseinjector2_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector2_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_status <= 32'd0;
+ soc_litedramcore_phaseinjector3_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector3_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_status <= 32'd0;
+ soc_litedramcore_dfi_p0_address <= 15'd0;
+ soc_litedramcore_dfi_p0_bank <= 3'd0;
+ soc_litedramcore_dfi_p0_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p0_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p0_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p0_we_n <= 1'd1;
+ soc_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p0_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p1_address <= 15'd0;
+ soc_litedramcore_dfi_p1_bank <= 3'd0;
+ soc_litedramcore_dfi_p1_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p1_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p1_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p1_we_n <= 1'd1;
+ soc_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p1_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p2_address <= 15'd0;
+ soc_litedramcore_dfi_p2_bank <= 3'd0;
+ soc_litedramcore_dfi_p2_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p2_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p2_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p2_we_n <= 1'd1;
+ soc_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p2_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p3_address <= 15'd0;
+ soc_litedramcore_dfi_p3_bank <= 3'd0;
+ soc_litedramcore_dfi_p3_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p3_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p3_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p3_we_n <= 1'd1;
+ soc_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p3_rddata_en <= 1'd0;
+ soc_litedramcore_timer_count1 <= 10'd781;
+ soc_litedramcore_postponer_req_o <= 1'd0;
+ soc_litedramcore_postponer_count <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd0;
+ soc_litedramcore_sequencer_counter <= 6'd0;
+ soc_litedramcore_sequencer_count <= 1'd0;
+ soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ soc_litedramcore_zqcs_executer_done <= 1'd0;
+ soc_litedramcore_zqcs_executer_counter <= 5'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine0_row <= 15'd0;
+ soc_litedramcore_bankmachine0_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine1_row <= 15'd0;
+ soc_litedramcore_bankmachine1_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine2_row <= 15'd0;
+ soc_litedramcore_bankmachine2_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine3_row <= 15'd0;
+ soc_litedramcore_bankmachine3_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine4_row <= 15'd0;
+ soc_litedramcore_bankmachine4_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine5_row <= 15'd0;
+ soc_litedramcore_bankmachine5_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine6_row <= 15'd0;
+ soc_litedramcore_bankmachine6_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine7_row <= 15'd0;
+ soc_litedramcore_bankmachine7_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trascon_count <= 3'd0;
+ soc_litedramcore_choose_cmd_grant <= 3'd0;
+ soc_litedramcore_choose_req_grant <= 3'd0;
+ soc_litedramcore_trrdcon_ready <= 1'd0;
+ soc_litedramcore_trrdcon_count <= 1'd0;
+ soc_litedramcore_tfawcon_ready <= 1'd1;
+ soc_litedramcore_tfawcon_window <= 5'd0;
+ soc_litedramcore_tccdcon_ready <= 1'd0;
+ soc_litedramcore_tccdcon_count <= 1'd0;
+ soc_litedramcore_twtrcon_ready <= 1'd0;
+ soc_litedramcore_twtrcon_count <= 3'd0;
+ soc_litedramcore_time0 <= 5'd0;
+ soc_litedramcore_time1 <= 4'd0;
+ soc_init_done_storage <= 1'd0;
+ soc_init_done_re <= 1'd0;
+ soc_init_error_storage <= 1'd0;
+ soc_init_error_re <= 1'd0;
+ vns_state <= 1'd0;
+ vns_refresher_state <= 2'd0;
+ vns_bankmachine0_state <= 4'd0;
+ vns_bankmachine1_state <= 4'd0;
+ vns_bankmachine2_state <= 4'd0;
+ vns_bankmachine3_state <= 4'd0;
+ vns_bankmachine4_state <= 4'd0;
+ vns_bankmachine5_state <= 4'd0;
+ vns_bankmachine6_state <= 4'd0;
+ vns_bankmachine7_state <= 4'd0;
+ vns_multiplexer_state <= 4'd0;
+ vns_new_master_wdata_ready0 <= 1'd0;
+ vns_new_master_wdata_ready1 <= 1'd0;
+ vns_new_master_wdata_ready2 <= 1'd0;
+ vns_new_master_rdata_valid0 <= 1'd0;
+ vns_new_master_rdata_valid1 <= 1'd0;
+ vns_new_master_rdata_valid2 <= 1'd0;
+ vns_new_master_rdata_valid3 <= 1'd0;
+ vns_new_master_rdata_valid4 <= 1'd0;
+ vns_new_master_rdata_valid5 <= 1'd0;
+ vns_new_master_rdata_valid6 <= 1'd0;
+ vns_new_master_rdata_valid7 <= 1'd0;
+ vns_new_master_rdata_valid8 <= 1'd0;
end
end
BUFG BUFG(
- .I(s7pll0_clkout0),
- .O(s7pll0_clkout_buf0)
+ .I(soc_clkout0),
+ .O(soc_clkout_buf0)
);
BUFG BUFG_1(
- .I(s7pll0_clkout1),
- .O(s7pll0_clkout_buf1)
+ .I(soc_clkout1),
+ .O(soc_clkout_buf1)
);
BUFG BUFG_2(
- .I(s7pll0_clkout2),
- .O(s7pll0_clkout_buf2)
+ .I(soc_clkout2),
+ .O(soc_clkout_buf2)
);
BUFG BUFG_3(
- .I(s7pll1_clkout),
- .O(s7pll1_clkout_buf)
+ .I(soc_clkout3),
+ .O(soc_clkout_buf3)
);
IDELAYCTRL IDELAYCTRL(
.REFCLK(iodelay_clk),
- .RST(ic_reset)
+ .RST(soc_ic_reset)
);
OSERDESE2 #(
.D8(1'd1),
.OCE(1'd1),
.RST(sys_rst),
- .OQ(a7ddrphy_sd_clk_se_nodelay)
+ .OQ(soc_a7ddrphy_sd_clk_se_nodelay)
);
OBUFDS OBUFDS(
- .I(a7ddrphy_sd_clk_se_nodelay),
+ .I(soc_a7ddrphy_sd_clk_se_nodelay),
.O(ddram_clk_p),
.OB(ddram_clk_n)
);
) OSERDESE2_1 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[0]),
- .D2(a7ddrphy_dfi_p0_address[0]),
- .D3(a7ddrphy_dfi_p1_address[0]),
- .D4(a7ddrphy_dfi_p1_address[0]),
- .D5(a7ddrphy_dfi_p2_address[0]),
- .D6(a7ddrphy_dfi_p2_address[0]),
- .D7(a7ddrphy_dfi_p3_address[0]),
- .D8(a7ddrphy_dfi_p3_address[0]),
+ .D1(soc_a7ddrphy_dfi_p0_address[0]),
+ .D2(soc_a7ddrphy_dfi_p0_address[0]),
+ .D3(soc_a7ddrphy_dfi_p1_address[0]),
+ .D4(soc_a7ddrphy_dfi_p1_address[0]),
+ .D5(soc_a7ddrphy_dfi_p2_address[0]),
+ .D6(soc_a7ddrphy_dfi_p2_address[0]),
+ .D7(soc_a7ddrphy_dfi_p3_address[0]),
+ .D8(soc_a7ddrphy_dfi_p3_address[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[0])
) OSERDESE2_2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[1]),
- .D2(a7ddrphy_dfi_p0_address[1]),
- .D3(a7ddrphy_dfi_p1_address[1]),
- .D4(a7ddrphy_dfi_p1_address[1]),
- .D5(a7ddrphy_dfi_p2_address[1]),
- .D6(a7ddrphy_dfi_p2_address[1]),
- .D7(a7ddrphy_dfi_p3_address[1]),
- .D8(a7ddrphy_dfi_p3_address[1]),
+ .D1(soc_a7ddrphy_dfi_p0_address[1]),
+ .D2(soc_a7ddrphy_dfi_p0_address[1]),
+ .D3(soc_a7ddrphy_dfi_p1_address[1]),
+ .D4(soc_a7ddrphy_dfi_p1_address[1]),
+ .D5(soc_a7ddrphy_dfi_p2_address[1]),
+ .D6(soc_a7ddrphy_dfi_p2_address[1]),
+ .D7(soc_a7ddrphy_dfi_p3_address[1]),
+ .D8(soc_a7ddrphy_dfi_p3_address[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[1])
) OSERDESE2_3 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[2]),
- .D2(a7ddrphy_dfi_p0_address[2]),
- .D3(a7ddrphy_dfi_p1_address[2]),
- .D4(a7ddrphy_dfi_p1_address[2]),
- .D5(a7ddrphy_dfi_p2_address[2]),
- .D6(a7ddrphy_dfi_p2_address[2]),
- .D7(a7ddrphy_dfi_p3_address[2]),
- .D8(a7ddrphy_dfi_p3_address[2]),
+ .D1(soc_a7ddrphy_dfi_p0_address[2]),
+ .D2(soc_a7ddrphy_dfi_p0_address[2]),
+ .D3(soc_a7ddrphy_dfi_p1_address[2]),
+ .D4(soc_a7ddrphy_dfi_p1_address[2]),
+ .D5(soc_a7ddrphy_dfi_p2_address[2]),
+ .D6(soc_a7ddrphy_dfi_p2_address[2]),
+ .D7(soc_a7ddrphy_dfi_p3_address[2]),
+ .D8(soc_a7ddrphy_dfi_p3_address[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[2])
) OSERDESE2_4 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[3]),
- .D2(a7ddrphy_dfi_p0_address[3]),
- .D3(a7ddrphy_dfi_p1_address[3]),
- .D4(a7ddrphy_dfi_p1_address[3]),
- .D5(a7ddrphy_dfi_p2_address[3]),
- .D6(a7ddrphy_dfi_p2_address[3]),
- .D7(a7ddrphy_dfi_p3_address[3]),
- .D8(a7ddrphy_dfi_p3_address[3]),
+ .D1(soc_a7ddrphy_dfi_p0_address[3]),
+ .D2(soc_a7ddrphy_dfi_p0_address[3]),
+ .D3(soc_a7ddrphy_dfi_p1_address[3]),
+ .D4(soc_a7ddrphy_dfi_p1_address[3]),
+ .D5(soc_a7ddrphy_dfi_p2_address[3]),
+ .D6(soc_a7ddrphy_dfi_p2_address[3]),
+ .D7(soc_a7ddrphy_dfi_p3_address[3]),
+ .D8(soc_a7ddrphy_dfi_p3_address[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[3])
) OSERDESE2_5 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[4]),
- .D2(a7ddrphy_dfi_p0_address[4]),
- .D3(a7ddrphy_dfi_p1_address[4]),
- .D4(a7ddrphy_dfi_p1_address[4]),
- .D5(a7ddrphy_dfi_p2_address[4]),
- .D6(a7ddrphy_dfi_p2_address[4]),
- .D7(a7ddrphy_dfi_p3_address[4]),
- .D8(a7ddrphy_dfi_p3_address[4]),
+ .D1(soc_a7ddrphy_dfi_p0_address[4]),
+ .D2(soc_a7ddrphy_dfi_p0_address[4]),
+ .D3(soc_a7ddrphy_dfi_p1_address[4]),
+ .D4(soc_a7ddrphy_dfi_p1_address[4]),
+ .D5(soc_a7ddrphy_dfi_p2_address[4]),
+ .D6(soc_a7ddrphy_dfi_p2_address[4]),
+ .D7(soc_a7ddrphy_dfi_p3_address[4]),
+ .D8(soc_a7ddrphy_dfi_p3_address[4]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[4])
) OSERDESE2_6 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[5]),
- .D2(a7ddrphy_dfi_p0_address[5]),
- .D3(a7ddrphy_dfi_p1_address[5]),
- .D4(a7ddrphy_dfi_p1_address[5]),
- .D5(a7ddrphy_dfi_p2_address[5]),
- .D6(a7ddrphy_dfi_p2_address[5]),
- .D7(a7ddrphy_dfi_p3_address[5]),
- .D8(a7ddrphy_dfi_p3_address[5]),
+ .D1(soc_a7ddrphy_dfi_p0_address[5]),
+ .D2(soc_a7ddrphy_dfi_p0_address[5]),
+ .D3(soc_a7ddrphy_dfi_p1_address[5]),
+ .D4(soc_a7ddrphy_dfi_p1_address[5]),
+ .D5(soc_a7ddrphy_dfi_p2_address[5]),
+ .D6(soc_a7ddrphy_dfi_p2_address[5]),
+ .D7(soc_a7ddrphy_dfi_p3_address[5]),
+ .D8(soc_a7ddrphy_dfi_p3_address[5]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[5])
) OSERDESE2_7 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[6]),
- .D2(a7ddrphy_dfi_p0_address[6]),
- .D3(a7ddrphy_dfi_p1_address[6]),
- .D4(a7ddrphy_dfi_p1_address[6]),
- .D5(a7ddrphy_dfi_p2_address[6]),
- .D6(a7ddrphy_dfi_p2_address[6]),
- .D7(a7ddrphy_dfi_p3_address[6]),
- .D8(a7ddrphy_dfi_p3_address[6]),
+ .D1(soc_a7ddrphy_dfi_p0_address[6]),
+ .D2(soc_a7ddrphy_dfi_p0_address[6]),
+ .D3(soc_a7ddrphy_dfi_p1_address[6]),
+ .D4(soc_a7ddrphy_dfi_p1_address[6]),
+ .D5(soc_a7ddrphy_dfi_p2_address[6]),
+ .D6(soc_a7ddrphy_dfi_p2_address[6]),
+ .D7(soc_a7ddrphy_dfi_p3_address[6]),
+ .D8(soc_a7ddrphy_dfi_p3_address[6]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[6])
) OSERDESE2_8 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[7]),
- .D2(a7ddrphy_dfi_p0_address[7]),
- .D3(a7ddrphy_dfi_p1_address[7]),
- .D4(a7ddrphy_dfi_p1_address[7]),
- .D5(a7ddrphy_dfi_p2_address[7]),
- .D6(a7ddrphy_dfi_p2_address[7]),
- .D7(a7ddrphy_dfi_p3_address[7]),
- .D8(a7ddrphy_dfi_p3_address[7]),
+ .D1(soc_a7ddrphy_dfi_p0_address[7]),
+ .D2(soc_a7ddrphy_dfi_p0_address[7]),
+ .D3(soc_a7ddrphy_dfi_p1_address[7]),
+ .D4(soc_a7ddrphy_dfi_p1_address[7]),
+ .D5(soc_a7ddrphy_dfi_p2_address[7]),
+ .D6(soc_a7ddrphy_dfi_p2_address[7]),
+ .D7(soc_a7ddrphy_dfi_p3_address[7]),
+ .D8(soc_a7ddrphy_dfi_p3_address[7]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[7])
) OSERDESE2_9 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[8]),
- .D2(a7ddrphy_dfi_p0_address[8]),
- .D3(a7ddrphy_dfi_p1_address[8]),
- .D4(a7ddrphy_dfi_p1_address[8]),
- .D5(a7ddrphy_dfi_p2_address[8]),
- .D6(a7ddrphy_dfi_p2_address[8]),
- .D7(a7ddrphy_dfi_p3_address[8]),
- .D8(a7ddrphy_dfi_p3_address[8]),
+ .D1(soc_a7ddrphy_dfi_p0_address[8]),
+ .D2(soc_a7ddrphy_dfi_p0_address[8]),
+ .D3(soc_a7ddrphy_dfi_p1_address[8]),
+ .D4(soc_a7ddrphy_dfi_p1_address[8]),
+ .D5(soc_a7ddrphy_dfi_p2_address[8]),
+ .D6(soc_a7ddrphy_dfi_p2_address[8]),
+ .D7(soc_a7ddrphy_dfi_p3_address[8]),
+ .D8(soc_a7ddrphy_dfi_p3_address[8]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[8])
) OSERDESE2_10 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[9]),
- .D2(a7ddrphy_dfi_p0_address[9]),
- .D3(a7ddrphy_dfi_p1_address[9]),
- .D4(a7ddrphy_dfi_p1_address[9]),
- .D5(a7ddrphy_dfi_p2_address[9]),
- .D6(a7ddrphy_dfi_p2_address[9]),
- .D7(a7ddrphy_dfi_p3_address[9]),
- .D8(a7ddrphy_dfi_p3_address[9]),
+ .D1(soc_a7ddrphy_dfi_p0_address[9]),
+ .D2(soc_a7ddrphy_dfi_p0_address[9]),
+ .D3(soc_a7ddrphy_dfi_p1_address[9]),
+ .D4(soc_a7ddrphy_dfi_p1_address[9]),
+ .D5(soc_a7ddrphy_dfi_p2_address[9]),
+ .D6(soc_a7ddrphy_dfi_p2_address[9]),
+ .D7(soc_a7ddrphy_dfi_p3_address[9]),
+ .D8(soc_a7ddrphy_dfi_p3_address[9]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[9])
) OSERDESE2_11 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[10]),
- .D2(a7ddrphy_dfi_p0_address[10]),
- .D3(a7ddrphy_dfi_p1_address[10]),
- .D4(a7ddrphy_dfi_p1_address[10]),
- .D5(a7ddrphy_dfi_p2_address[10]),
- .D6(a7ddrphy_dfi_p2_address[10]),
- .D7(a7ddrphy_dfi_p3_address[10]),
- .D8(a7ddrphy_dfi_p3_address[10]),
+ .D1(soc_a7ddrphy_dfi_p0_address[10]),
+ .D2(soc_a7ddrphy_dfi_p0_address[10]),
+ .D3(soc_a7ddrphy_dfi_p1_address[10]),
+ .D4(soc_a7ddrphy_dfi_p1_address[10]),
+ .D5(soc_a7ddrphy_dfi_p2_address[10]),
+ .D6(soc_a7ddrphy_dfi_p2_address[10]),
+ .D7(soc_a7ddrphy_dfi_p3_address[10]),
+ .D8(soc_a7ddrphy_dfi_p3_address[10]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[10])
) OSERDESE2_12 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[11]),
- .D2(a7ddrphy_dfi_p0_address[11]),
- .D3(a7ddrphy_dfi_p1_address[11]),
- .D4(a7ddrphy_dfi_p1_address[11]),
- .D5(a7ddrphy_dfi_p2_address[11]),
- .D6(a7ddrphy_dfi_p2_address[11]),
- .D7(a7ddrphy_dfi_p3_address[11]),
- .D8(a7ddrphy_dfi_p3_address[11]),
+ .D1(soc_a7ddrphy_dfi_p0_address[11]),
+ .D2(soc_a7ddrphy_dfi_p0_address[11]),
+ .D3(soc_a7ddrphy_dfi_p1_address[11]),
+ .D4(soc_a7ddrphy_dfi_p1_address[11]),
+ .D5(soc_a7ddrphy_dfi_p2_address[11]),
+ .D6(soc_a7ddrphy_dfi_p2_address[11]),
+ .D7(soc_a7ddrphy_dfi_p3_address[11]),
+ .D8(soc_a7ddrphy_dfi_p3_address[11]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[11])
) OSERDESE2_13 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[12]),
- .D2(a7ddrphy_dfi_p0_address[12]),
- .D3(a7ddrphy_dfi_p1_address[12]),
- .D4(a7ddrphy_dfi_p1_address[12]),
- .D5(a7ddrphy_dfi_p2_address[12]),
- .D6(a7ddrphy_dfi_p2_address[12]),
- .D7(a7ddrphy_dfi_p3_address[12]),
- .D8(a7ddrphy_dfi_p3_address[12]),
+ .D1(soc_a7ddrphy_dfi_p0_address[12]),
+ .D2(soc_a7ddrphy_dfi_p0_address[12]),
+ .D3(soc_a7ddrphy_dfi_p1_address[12]),
+ .D4(soc_a7ddrphy_dfi_p1_address[12]),
+ .D5(soc_a7ddrphy_dfi_p2_address[12]),
+ .D6(soc_a7ddrphy_dfi_p2_address[12]),
+ .D7(soc_a7ddrphy_dfi_p3_address[12]),
+ .D8(soc_a7ddrphy_dfi_p3_address[12]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[12])
) OSERDESE2_14 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[13]),
- .D2(a7ddrphy_dfi_p0_address[13]),
- .D3(a7ddrphy_dfi_p1_address[13]),
- .D4(a7ddrphy_dfi_p1_address[13]),
- .D5(a7ddrphy_dfi_p2_address[13]),
- .D6(a7ddrphy_dfi_p2_address[13]),
- .D7(a7ddrphy_dfi_p3_address[13]),
- .D8(a7ddrphy_dfi_p3_address[13]),
+ .D1(soc_a7ddrphy_dfi_p0_address[13]),
+ .D2(soc_a7ddrphy_dfi_p0_address[13]),
+ .D3(soc_a7ddrphy_dfi_p1_address[13]),
+ .D4(soc_a7ddrphy_dfi_p1_address[13]),
+ .D5(soc_a7ddrphy_dfi_p2_address[13]),
+ .D6(soc_a7ddrphy_dfi_p2_address[13]),
+ .D7(soc_a7ddrphy_dfi_p3_address[13]),
+ .D8(soc_a7ddrphy_dfi_p3_address[13]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[13])
) OSERDESE2_15 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_address[14]),
- .D2(a7ddrphy_dfi_p0_address[14]),
- .D3(a7ddrphy_dfi_p1_address[14]),
- .D4(a7ddrphy_dfi_p1_address[14]),
- .D5(a7ddrphy_dfi_p2_address[14]),
- .D6(a7ddrphy_dfi_p2_address[14]),
- .D7(a7ddrphy_dfi_p3_address[14]),
- .D8(a7ddrphy_dfi_p3_address[14]),
+ .D1(soc_a7ddrphy_dfi_p0_address[14]),
+ .D2(soc_a7ddrphy_dfi_p0_address[14]),
+ .D3(soc_a7ddrphy_dfi_p1_address[14]),
+ .D4(soc_a7ddrphy_dfi_p1_address[14]),
+ .D5(soc_a7ddrphy_dfi_p2_address[14]),
+ .D6(soc_a7ddrphy_dfi_p2_address[14]),
+ .D7(soc_a7ddrphy_dfi_p3_address[14]),
+ .D8(soc_a7ddrphy_dfi_p3_address[14]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[14])
) OSERDESE2_16 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_bank[0]),
- .D2(a7ddrphy_dfi_p0_bank[0]),
- .D3(a7ddrphy_dfi_p1_bank[0]),
- .D4(a7ddrphy_dfi_p1_bank[0]),
- .D5(a7ddrphy_dfi_p2_bank[0]),
- .D6(a7ddrphy_dfi_p2_bank[0]),
- .D7(a7ddrphy_dfi_p3_bank[0]),
- .D8(a7ddrphy_dfi_p3_bank[0]),
+ .D1(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[0]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[0])
) OSERDESE2_17 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_bank[1]),
- .D2(a7ddrphy_dfi_p0_bank[1]),
- .D3(a7ddrphy_dfi_p1_bank[1]),
- .D4(a7ddrphy_dfi_p1_bank[1]),
- .D5(a7ddrphy_dfi_p2_bank[1]),
- .D6(a7ddrphy_dfi_p2_bank[1]),
- .D7(a7ddrphy_dfi_p3_bank[1]),
- .D8(a7ddrphy_dfi_p3_bank[1]),
+ .D1(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[1]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[1])
) OSERDESE2_18 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_bank[2]),
- .D2(a7ddrphy_dfi_p0_bank[2]),
- .D3(a7ddrphy_dfi_p1_bank[2]),
- .D4(a7ddrphy_dfi_p1_bank[2]),
- .D5(a7ddrphy_dfi_p2_bank[2]),
- .D6(a7ddrphy_dfi_p2_bank[2]),
- .D7(a7ddrphy_dfi_p3_bank[2]),
- .D8(a7ddrphy_dfi_p3_bank[2]),
+ .D1(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[2]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[2])
) OSERDESE2_19 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_ras_n),
- .D2(a7ddrphy_dfi_p0_ras_n),
- .D3(a7ddrphy_dfi_p1_ras_n),
- .D4(a7ddrphy_dfi_p1_ras_n),
- .D5(a7ddrphy_dfi_p2_ras_n),
- .D6(a7ddrphy_dfi_p2_ras_n),
- .D7(a7ddrphy_dfi_p3_ras_n),
- .D8(a7ddrphy_dfi_p3_ras_n),
+ .D1(soc_a7ddrphy_dfi_p0_ras_n),
+ .D2(soc_a7ddrphy_dfi_p0_ras_n),
+ .D3(soc_a7ddrphy_dfi_p1_ras_n),
+ .D4(soc_a7ddrphy_dfi_p1_ras_n),
+ .D5(soc_a7ddrphy_dfi_p2_ras_n),
+ .D6(soc_a7ddrphy_dfi_p2_ras_n),
+ .D7(soc_a7ddrphy_dfi_p3_ras_n),
+ .D8(soc_a7ddrphy_dfi_p3_ras_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ras_n)
) OSERDESE2_20 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_cas_n),
- .D2(a7ddrphy_dfi_p0_cas_n),
- .D3(a7ddrphy_dfi_p1_cas_n),
- .D4(a7ddrphy_dfi_p1_cas_n),
- .D5(a7ddrphy_dfi_p2_cas_n),
- .D6(a7ddrphy_dfi_p2_cas_n),
- .D7(a7ddrphy_dfi_p3_cas_n),
- .D8(a7ddrphy_dfi_p3_cas_n),
+ .D1(soc_a7ddrphy_dfi_p0_cas_n),
+ .D2(soc_a7ddrphy_dfi_p0_cas_n),
+ .D3(soc_a7ddrphy_dfi_p1_cas_n),
+ .D4(soc_a7ddrphy_dfi_p1_cas_n),
+ .D5(soc_a7ddrphy_dfi_p2_cas_n),
+ .D6(soc_a7ddrphy_dfi_p2_cas_n),
+ .D7(soc_a7ddrphy_dfi_p3_cas_n),
+ .D8(soc_a7ddrphy_dfi_p3_cas_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cas_n)
) OSERDESE2_21 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_we_n),
- .D2(a7ddrphy_dfi_p0_we_n),
- .D3(a7ddrphy_dfi_p1_we_n),
- .D4(a7ddrphy_dfi_p1_we_n),
- .D5(a7ddrphy_dfi_p2_we_n),
- .D6(a7ddrphy_dfi_p2_we_n),
- .D7(a7ddrphy_dfi_p3_we_n),
- .D8(a7ddrphy_dfi_p3_we_n),
+ .D1(soc_a7ddrphy_dfi_p0_we_n),
+ .D2(soc_a7ddrphy_dfi_p0_we_n),
+ .D3(soc_a7ddrphy_dfi_p1_we_n),
+ .D4(soc_a7ddrphy_dfi_p1_we_n),
+ .D5(soc_a7ddrphy_dfi_p2_we_n),
+ .D6(soc_a7ddrphy_dfi_p2_we_n),
+ .D7(soc_a7ddrphy_dfi_p3_we_n),
+ .D8(soc_a7ddrphy_dfi_p3_we_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_we_n)
) OSERDESE2_22 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_cke),
- .D2(a7ddrphy_dfi_p0_cke),
- .D3(a7ddrphy_dfi_p1_cke),
- .D4(a7ddrphy_dfi_p1_cke),
- .D5(a7ddrphy_dfi_p2_cke),
- .D6(a7ddrphy_dfi_p2_cke),
- .D7(a7ddrphy_dfi_p3_cke),
- .D8(a7ddrphy_dfi_p3_cke),
+ .D1(soc_a7ddrphy_dfi_p0_cke),
+ .D2(soc_a7ddrphy_dfi_p0_cke),
+ .D3(soc_a7ddrphy_dfi_p1_cke),
+ .D4(soc_a7ddrphy_dfi_p1_cke),
+ .D5(soc_a7ddrphy_dfi_p2_cke),
+ .D6(soc_a7ddrphy_dfi_p2_cke),
+ .D7(soc_a7ddrphy_dfi_p3_cke),
+ .D8(soc_a7ddrphy_dfi_p3_cke),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cke)
) OSERDESE2_23 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_odt),
- .D2(a7ddrphy_dfi_p0_odt),
- .D3(a7ddrphy_dfi_p1_odt),
- .D4(a7ddrphy_dfi_p1_odt),
- .D5(a7ddrphy_dfi_p2_odt),
- .D6(a7ddrphy_dfi_p2_odt),
- .D7(a7ddrphy_dfi_p3_odt),
- .D8(a7ddrphy_dfi_p3_odt),
+ .D1(soc_a7ddrphy_dfi_p0_odt),
+ .D2(soc_a7ddrphy_dfi_p0_odt),
+ .D3(soc_a7ddrphy_dfi_p1_odt),
+ .D4(soc_a7ddrphy_dfi_p1_odt),
+ .D5(soc_a7ddrphy_dfi_p2_odt),
+ .D6(soc_a7ddrphy_dfi_p2_odt),
+ .D7(soc_a7ddrphy_dfi_p3_odt),
+ .D8(soc_a7ddrphy_dfi_p3_odt),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_odt)
) OSERDESE2_24 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_reset_n),
- .D2(a7ddrphy_dfi_p0_reset_n),
- .D3(a7ddrphy_dfi_p1_reset_n),
- .D4(a7ddrphy_dfi_p1_reset_n),
- .D5(a7ddrphy_dfi_p2_reset_n),
- .D6(a7ddrphy_dfi_p2_reset_n),
- .D7(a7ddrphy_dfi_p3_reset_n),
- .D8(a7ddrphy_dfi_p3_reset_n),
+ .D1(soc_a7ddrphy_dfi_p0_reset_n),
+ .D2(soc_a7ddrphy_dfi_p0_reset_n),
+ .D3(soc_a7ddrphy_dfi_p1_reset_n),
+ .D4(soc_a7ddrphy_dfi_p1_reset_n),
+ .D5(soc_a7ddrphy_dfi_p2_reset_n),
+ .D6(soc_a7ddrphy_dfi_p2_reset_n),
+ .D7(soc_a7ddrphy_dfi_p3_reset_n),
+ .D8(soc_a7ddrphy_dfi_p3_reset_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_reset_n)
) OSERDESE2_25 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_cs_n),
- .D2(a7ddrphy_dfi_p0_cs_n),
- .D3(a7ddrphy_dfi_p1_cs_n),
- .D4(a7ddrphy_dfi_p1_cs_n),
- .D5(a7ddrphy_dfi_p2_cs_n),
- .D6(a7ddrphy_dfi_p2_cs_n),
- .D7(a7ddrphy_dfi_p3_cs_n),
- .D8(a7ddrphy_dfi_p3_cs_n),
+ .D1(soc_a7ddrphy_dfi_p0_cs_n),
+ .D2(soc_a7ddrphy_dfi_p0_cs_n),
+ .D3(soc_a7ddrphy_dfi_p1_cs_n),
+ .D4(soc_a7ddrphy_dfi_p1_cs_n),
+ .D5(soc_a7ddrphy_dfi_p2_cs_n),
+ .D6(soc_a7ddrphy_dfi_p2_cs_n),
+ .D7(soc_a7ddrphy_dfi_p3_cs_n),
+ .D8(soc_a7ddrphy_dfi_p3_cs_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cs_n)
) OSERDESE2_26 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata_mask[0]),
- .D2(a7ddrphy_dfi_p0_wrdata_mask[2]),
- .D3(a7ddrphy_dfi_p1_wrdata_mask[0]),
- .D4(a7ddrphy_dfi_p1_wrdata_mask[2]),
- .D5(a7ddrphy_dfi_p2_wrdata_mask[0]),
- .D6(a7ddrphy_dfi_p2_wrdata_mask[2]),
- .D7(a7ddrphy_dfi_p3_wrdata_mask[0]),
- .D8(a7ddrphy_dfi_p3_wrdata_mask[2]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm[0])
) OSERDESE2_27 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata_mask[1]),
- .D2(a7ddrphy_dfi_p0_wrdata_mask[3]),
- .D3(a7ddrphy_dfi_p1_wrdata_mask[1]),
- .D4(a7ddrphy_dfi_p1_wrdata_mask[3]),
- .D5(a7ddrphy_dfi_p2_wrdata_mask[1]),
- .D6(a7ddrphy_dfi_p2_wrdata_mask[3]),
- .D7(a7ddrphy_dfi_p3_wrdata_mask[1]),
- .D8(a7ddrphy_dfi_p3_wrdata_mask[3]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm[1])
) OSERDESE2_28 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dqspattern_o1[0]),
- .D2(a7ddrphy_dqspattern_o1[1]),
- .D3(a7ddrphy_dqspattern_o1[2]),
- .D4(a7ddrphy_dqspattern_o1[3]),
- .D5(a7ddrphy_dqspattern_o1[4]),
- .D6(a7ddrphy_dqspattern_o1[5]),
- .D7(a7ddrphy_dqspattern_o1[6]),
- .D8(a7ddrphy_dqspattern_o1[7]),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dqs_oe_delayed)),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
.TCE(1'd1),
- .OFB(a7ddrphy0),
- .OQ(a7ddrphy_dqs_o_no_delay0),
- .TQ(a7ddrphy_dqs_t0)
+ .OFB(soc_a7ddrphy0),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay0),
+ .TQ(soc_a7ddrphy_dqs_t0)
);
IDELAYE2 #(
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2 (
- .IDATAIN(a7ddrphy_dqs_i[0]),
- .DATAOUT(a7ddrphy_dqs_i_delayed[0])
+ .IDATAIN(soc_a7ddrphy_dqs_i[0]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0])
);
IOBUFDS IOBUFDS(
- .I(a7ddrphy_dqs_o_no_delay0),
- .T(a7ddrphy_dqs_t0),
+ .I(soc_a7ddrphy_dqs_o_no_delay0),
+ .T(soc_a7ddrphy_dqs_t0),
.IO(ddram_dqs_p[0]),
.IOB(ddram_dqs_n[0]),
- .O(a7ddrphy_dqs_i[0])
+ .O(soc_a7ddrphy_dqs_i[0])
);
OSERDESE2 #(
) OSERDESE2_29 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dqspattern_o1[0]),
- .D2(a7ddrphy_dqspattern_o1[1]),
- .D3(a7ddrphy_dqspattern_o1[2]),
- .D4(a7ddrphy_dqspattern_o1[3]),
- .D5(a7ddrphy_dqspattern_o1[4]),
- .D6(a7ddrphy_dqspattern_o1[5]),
- .D7(a7ddrphy_dqspattern_o1[6]),
- .D8(a7ddrphy_dqspattern_o1[7]),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dqs_oe_delayed)),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
.TCE(1'd1),
- .OFB(a7ddrphy1),
- .OQ(a7ddrphy_dqs_o_no_delay1),
- .TQ(a7ddrphy_dqs_t1)
+ .OFB(soc_a7ddrphy1),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay1),
+ .TQ(soc_a7ddrphy_dqs_t1)
);
IDELAYE2 #(
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_1 (
- .IDATAIN(a7ddrphy_dqs_i[1]),
- .DATAOUT(a7ddrphy_dqs_i_delayed[1])
+ .IDATAIN(soc_a7ddrphy_dqs_i[1]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1])
);
IOBUFDS IOBUFDS_1(
- .I(a7ddrphy_dqs_o_no_delay1),
- .T(a7ddrphy_dqs_t1),
+ .I(soc_a7ddrphy_dqs_o_no_delay1),
+ .T(soc_a7ddrphy_dqs_t1),
.IO(ddram_dqs_p[1]),
.IOB(ddram_dqs_n[1]),
- .O(a7ddrphy_dqs_i[1])
+ .O(soc_a7ddrphy_dqs_i[1])
);
OSERDESE2 #(
) OSERDESE2_30 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[0]),
- .D2(a7ddrphy_dfi_p0_wrdata[16]),
- .D3(a7ddrphy_dfi_p1_wrdata[0]),
- .D4(a7ddrphy_dfi_p1_wrdata[16]),
- .D5(a7ddrphy_dfi_p2_wrdata[0]),
- .D6(a7ddrphy_dfi_p2_wrdata[16]),
- .D7(a7ddrphy_dfi_p3_wrdata[0]),
- .D8(a7ddrphy_dfi_p3_wrdata[16]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay0),
- .TQ(a7ddrphy_dq_t0)
+ .OQ(soc_a7ddrphy_dq_o_nodelay0),
+ .TQ(soc_a7ddrphy_dq_t0)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed0),
+ .DDLY(soc_a7ddrphy_dq_i_delayed0),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data0[7]),
- .Q2(a7ddrphy_dq_i_data0[6]),
- .Q3(a7ddrphy_dq_i_data0[5]),
- .Q4(a7ddrphy_dq_i_data0[4]),
- .Q5(a7ddrphy_dq_i_data0[3]),
- .Q6(a7ddrphy_dq_i_data0[2]),
- .Q7(a7ddrphy_dq_i_data0[1]),
- .Q8(a7ddrphy_dq_i_data0[0])
+ .Q1(soc_a7ddrphy_dq_i_data0[7]),
+ .Q2(soc_a7ddrphy_dq_i_data0[6]),
+ .Q3(soc_a7ddrphy_dq_i_data0[5]),
+ .Q4(soc_a7ddrphy_dq_i_data0[4]),
+ .Q5(soc_a7ddrphy_dq_i_data0[3]),
+ .Q6(soc_a7ddrphy_dq_i_data0[2]),
+ .Q7(soc_a7ddrphy_dq_i_data0[1]),
+ .Q8(soc_a7ddrphy_dq_i_data0[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_2 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay0),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed0)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed0)
);
IOBUF IOBUF(
- .I(a7ddrphy_dq_o_nodelay0),
- .T(a7ddrphy_dq_t0),
+ .I(soc_a7ddrphy_dq_o_nodelay0),
+ .T(soc_a7ddrphy_dq_t0),
.IO(ddram_dq[0]),
- .O(a7ddrphy_dq_i_nodelay0)
+ .O(soc_a7ddrphy_dq_i_nodelay0)
);
OSERDESE2 #(
) OSERDESE2_31 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[1]),
- .D2(a7ddrphy_dfi_p0_wrdata[17]),
- .D3(a7ddrphy_dfi_p1_wrdata[1]),
- .D4(a7ddrphy_dfi_p1_wrdata[17]),
- .D5(a7ddrphy_dfi_p2_wrdata[1]),
- .D6(a7ddrphy_dfi_p2_wrdata[17]),
- .D7(a7ddrphy_dfi_p3_wrdata[1]),
- .D8(a7ddrphy_dfi_p3_wrdata[17]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay1),
- .TQ(a7ddrphy_dq_t1)
+ .OQ(soc_a7ddrphy_dq_o_nodelay1),
+ .TQ(soc_a7ddrphy_dq_t1)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed1),
+ .DDLY(soc_a7ddrphy_dq_i_delayed1),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data1[7]),
- .Q2(a7ddrphy_dq_i_data1[6]),
- .Q3(a7ddrphy_dq_i_data1[5]),
- .Q4(a7ddrphy_dq_i_data1[4]),
- .Q5(a7ddrphy_dq_i_data1[3]),
- .Q6(a7ddrphy_dq_i_data1[2]),
- .Q7(a7ddrphy_dq_i_data1[1]),
- .Q8(a7ddrphy_dq_i_data1[0])
+ .Q1(soc_a7ddrphy_dq_i_data1[7]),
+ .Q2(soc_a7ddrphy_dq_i_data1[6]),
+ .Q3(soc_a7ddrphy_dq_i_data1[5]),
+ .Q4(soc_a7ddrphy_dq_i_data1[4]),
+ .Q5(soc_a7ddrphy_dq_i_data1[3]),
+ .Q6(soc_a7ddrphy_dq_i_data1[2]),
+ .Q7(soc_a7ddrphy_dq_i_data1[1]),
+ .Q8(soc_a7ddrphy_dq_i_data1[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_3 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay1),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed1)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed1)
);
IOBUF IOBUF_1(
- .I(a7ddrphy_dq_o_nodelay1),
- .T(a7ddrphy_dq_t1),
+ .I(soc_a7ddrphy_dq_o_nodelay1),
+ .T(soc_a7ddrphy_dq_t1),
.IO(ddram_dq[1]),
- .O(a7ddrphy_dq_i_nodelay1)
+ .O(soc_a7ddrphy_dq_i_nodelay1)
);
OSERDESE2 #(
) OSERDESE2_32 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[2]),
- .D2(a7ddrphy_dfi_p0_wrdata[18]),
- .D3(a7ddrphy_dfi_p1_wrdata[2]),
- .D4(a7ddrphy_dfi_p1_wrdata[18]),
- .D5(a7ddrphy_dfi_p2_wrdata[2]),
- .D6(a7ddrphy_dfi_p2_wrdata[18]),
- .D7(a7ddrphy_dfi_p3_wrdata[2]),
- .D8(a7ddrphy_dfi_p3_wrdata[18]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay2),
- .TQ(a7ddrphy_dq_t2)
+ .OQ(soc_a7ddrphy_dq_o_nodelay2),
+ .TQ(soc_a7ddrphy_dq_t2)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed2),
+ .DDLY(soc_a7ddrphy_dq_i_delayed2),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data2[7]),
- .Q2(a7ddrphy_dq_i_data2[6]),
- .Q3(a7ddrphy_dq_i_data2[5]),
- .Q4(a7ddrphy_dq_i_data2[4]),
- .Q5(a7ddrphy_dq_i_data2[3]),
- .Q6(a7ddrphy_dq_i_data2[2]),
- .Q7(a7ddrphy_dq_i_data2[1]),
- .Q8(a7ddrphy_dq_i_data2[0])
+ .Q1(soc_a7ddrphy_dq_i_data2[7]),
+ .Q2(soc_a7ddrphy_dq_i_data2[6]),
+ .Q3(soc_a7ddrphy_dq_i_data2[5]),
+ .Q4(soc_a7ddrphy_dq_i_data2[4]),
+ .Q5(soc_a7ddrphy_dq_i_data2[3]),
+ .Q6(soc_a7ddrphy_dq_i_data2[2]),
+ .Q7(soc_a7ddrphy_dq_i_data2[1]),
+ .Q8(soc_a7ddrphy_dq_i_data2[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_4 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay2),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed2)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed2)
);
IOBUF IOBUF_2(
- .I(a7ddrphy_dq_o_nodelay2),
- .T(a7ddrphy_dq_t2),
+ .I(soc_a7ddrphy_dq_o_nodelay2),
+ .T(soc_a7ddrphy_dq_t2),
.IO(ddram_dq[2]),
- .O(a7ddrphy_dq_i_nodelay2)
+ .O(soc_a7ddrphy_dq_i_nodelay2)
);
OSERDESE2 #(
) OSERDESE2_33 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[3]),
- .D2(a7ddrphy_dfi_p0_wrdata[19]),
- .D3(a7ddrphy_dfi_p1_wrdata[3]),
- .D4(a7ddrphy_dfi_p1_wrdata[19]),
- .D5(a7ddrphy_dfi_p2_wrdata[3]),
- .D6(a7ddrphy_dfi_p2_wrdata[19]),
- .D7(a7ddrphy_dfi_p3_wrdata[3]),
- .D8(a7ddrphy_dfi_p3_wrdata[19]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay3),
- .TQ(a7ddrphy_dq_t3)
+ .OQ(soc_a7ddrphy_dq_o_nodelay3),
+ .TQ(soc_a7ddrphy_dq_t3)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed3),
+ .DDLY(soc_a7ddrphy_dq_i_delayed3),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data3[7]),
- .Q2(a7ddrphy_dq_i_data3[6]),
- .Q3(a7ddrphy_dq_i_data3[5]),
- .Q4(a7ddrphy_dq_i_data3[4]),
- .Q5(a7ddrphy_dq_i_data3[3]),
- .Q6(a7ddrphy_dq_i_data3[2]),
- .Q7(a7ddrphy_dq_i_data3[1]),
- .Q8(a7ddrphy_dq_i_data3[0])
+ .Q1(soc_a7ddrphy_dq_i_data3[7]),
+ .Q2(soc_a7ddrphy_dq_i_data3[6]),
+ .Q3(soc_a7ddrphy_dq_i_data3[5]),
+ .Q4(soc_a7ddrphy_dq_i_data3[4]),
+ .Q5(soc_a7ddrphy_dq_i_data3[3]),
+ .Q6(soc_a7ddrphy_dq_i_data3[2]),
+ .Q7(soc_a7ddrphy_dq_i_data3[1]),
+ .Q8(soc_a7ddrphy_dq_i_data3[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_5 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay3),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed3)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed3)
);
IOBUF IOBUF_3(
- .I(a7ddrphy_dq_o_nodelay3),
- .T(a7ddrphy_dq_t3),
+ .I(soc_a7ddrphy_dq_o_nodelay3),
+ .T(soc_a7ddrphy_dq_t3),
.IO(ddram_dq[3]),
- .O(a7ddrphy_dq_i_nodelay3)
+ .O(soc_a7ddrphy_dq_i_nodelay3)
);
OSERDESE2 #(
) OSERDESE2_34 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[4]),
- .D2(a7ddrphy_dfi_p0_wrdata[20]),
- .D3(a7ddrphy_dfi_p1_wrdata[4]),
- .D4(a7ddrphy_dfi_p1_wrdata[20]),
- .D5(a7ddrphy_dfi_p2_wrdata[4]),
- .D6(a7ddrphy_dfi_p2_wrdata[20]),
- .D7(a7ddrphy_dfi_p3_wrdata[4]),
- .D8(a7ddrphy_dfi_p3_wrdata[20]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay4),
- .TQ(a7ddrphy_dq_t4)
+ .OQ(soc_a7ddrphy_dq_o_nodelay4),
+ .TQ(soc_a7ddrphy_dq_t4)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed4),
+ .DDLY(soc_a7ddrphy_dq_i_delayed4),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data4[7]),
- .Q2(a7ddrphy_dq_i_data4[6]),
- .Q3(a7ddrphy_dq_i_data4[5]),
- .Q4(a7ddrphy_dq_i_data4[4]),
- .Q5(a7ddrphy_dq_i_data4[3]),
- .Q6(a7ddrphy_dq_i_data4[2]),
- .Q7(a7ddrphy_dq_i_data4[1]),
- .Q8(a7ddrphy_dq_i_data4[0])
+ .Q1(soc_a7ddrphy_dq_i_data4[7]),
+ .Q2(soc_a7ddrphy_dq_i_data4[6]),
+ .Q3(soc_a7ddrphy_dq_i_data4[5]),
+ .Q4(soc_a7ddrphy_dq_i_data4[4]),
+ .Q5(soc_a7ddrphy_dq_i_data4[3]),
+ .Q6(soc_a7ddrphy_dq_i_data4[2]),
+ .Q7(soc_a7ddrphy_dq_i_data4[1]),
+ .Q8(soc_a7ddrphy_dq_i_data4[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_6 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay4),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed4)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed4)
);
IOBUF IOBUF_4(
- .I(a7ddrphy_dq_o_nodelay4),
- .T(a7ddrphy_dq_t4),
+ .I(soc_a7ddrphy_dq_o_nodelay4),
+ .T(soc_a7ddrphy_dq_t4),
.IO(ddram_dq[4]),
- .O(a7ddrphy_dq_i_nodelay4)
+ .O(soc_a7ddrphy_dq_i_nodelay4)
);
OSERDESE2 #(
) OSERDESE2_35 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[5]),
- .D2(a7ddrphy_dfi_p0_wrdata[21]),
- .D3(a7ddrphy_dfi_p1_wrdata[5]),
- .D4(a7ddrphy_dfi_p1_wrdata[21]),
- .D5(a7ddrphy_dfi_p2_wrdata[5]),
- .D6(a7ddrphy_dfi_p2_wrdata[21]),
- .D7(a7ddrphy_dfi_p3_wrdata[5]),
- .D8(a7ddrphy_dfi_p3_wrdata[21]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay5),
- .TQ(a7ddrphy_dq_t5)
+ .OQ(soc_a7ddrphy_dq_o_nodelay5),
+ .TQ(soc_a7ddrphy_dq_t5)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed5),
+ .DDLY(soc_a7ddrphy_dq_i_delayed5),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data5[7]),
- .Q2(a7ddrphy_dq_i_data5[6]),
- .Q3(a7ddrphy_dq_i_data5[5]),
- .Q4(a7ddrphy_dq_i_data5[4]),
- .Q5(a7ddrphy_dq_i_data5[3]),
- .Q6(a7ddrphy_dq_i_data5[2]),
- .Q7(a7ddrphy_dq_i_data5[1]),
- .Q8(a7ddrphy_dq_i_data5[0])
+ .Q1(soc_a7ddrphy_dq_i_data5[7]),
+ .Q2(soc_a7ddrphy_dq_i_data5[6]),
+ .Q3(soc_a7ddrphy_dq_i_data5[5]),
+ .Q4(soc_a7ddrphy_dq_i_data5[4]),
+ .Q5(soc_a7ddrphy_dq_i_data5[3]),
+ .Q6(soc_a7ddrphy_dq_i_data5[2]),
+ .Q7(soc_a7ddrphy_dq_i_data5[1]),
+ .Q8(soc_a7ddrphy_dq_i_data5[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_7 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay5),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed5)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed5)
);
IOBUF IOBUF_5(
- .I(a7ddrphy_dq_o_nodelay5),
- .T(a7ddrphy_dq_t5),
+ .I(soc_a7ddrphy_dq_o_nodelay5),
+ .T(soc_a7ddrphy_dq_t5),
.IO(ddram_dq[5]),
- .O(a7ddrphy_dq_i_nodelay5)
+ .O(soc_a7ddrphy_dq_i_nodelay5)
);
OSERDESE2 #(
) OSERDESE2_36 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[6]),
- .D2(a7ddrphy_dfi_p0_wrdata[22]),
- .D3(a7ddrphy_dfi_p1_wrdata[6]),
- .D4(a7ddrphy_dfi_p1_wrdata[22]),
- .D5(a7ddrphy_dfi_p2_wrdata[6]),
- .D6(a7ddrphy_dfi_p2_wrdata[22]),
- .D7(a7ddrphy_dfi_p3_wrdata[6]),
- .D8(a7ddrphy_dfi_p3_wrdata[22]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay6),
- .TQ(a7ddrphy_dq_t6)
+ .OQ(soc_a7ddrphy_dq_o_nodelay6),
+ .TQ(soc_a7ddrphy_dq_t6)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed6),
+ .DDLY(soc_a7ddrphy_dq_i_delayed6),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data6[7]),
- .Q2(a7ddrphy_dq_i_data6[6]),
- .Q3(a7ddrphy_dq_i_data6[5]),
- .Q4(a7ddrphy_dq_i_data6[4]),
- .Q5(a7ddrphy_dq_i_data6[3]),
- .Q6(a7ddrphy_dq_i_data6[2]),
- .Q7(a7ddrphy_dq_i_data6[1]),
- .Q8(a7ddrphy_dq_i_data6[0])
+ .Q1(soc_a7ddrphy_dq_i_data6[7]),
+ .Q2(soc_a7ddrphy_dq_i_data6[6]),
+ .Q3(soc_a7ddrphy_dq_i_data6[5]),
+ .Q4(soc_a7ddrphy_dq_i_data6[4]),
+ .Q5(soc_a7ddrphy_dq_i_data6[3]),
+ .Q6(soc_a7ddrphy_dq_i_data6[2]),
+ .Q7(soc_a7ddrphy_dq_i_data6[1]),
+ .Q8(soc_a7ddrphy_dq_i_data6[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_8 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay6),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed6)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed6)
);
IOBUF IOBUF_6(
- .I(a7ddrphy_dq_o_nodelay6),
- .T(a7ddrphy_dq_t6),
+ .I(soc_a7ddrphy_dq_o_nodelay6),
+ .T(soc_a7ddrphy_dq_t6),
.IO(ddram_dq[6]),
- .O(a7ddrphy_dq_i_nodelay6)
+ .O(soc_a7ddrphy_dq_i_nodelay6)
);
OSERDESE2 #(
) OSERDESE2_37 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[7]),
- .D2(a7ddrphy_dfi_p0_wrdata[23]),
- .D3(a7ddrphy_dfi_p1_wrdata[7]),
- .D4(a7ddrphy_dfi_p1_wrdata[23]),
- .D5(a7ddrphy_dfi_p2_wrdata[7]),
- .D6(a7ddrphy_dfi_p2_wrdata[23]),
- .D7(a7ddrphy_dfi_p3_wrdata[7]),
- .D8(a7ddrphy_dfi_p3_wrdata[23]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay7),
- .TQ(a7ddrphy_dq_t7)
+ .OQ(soc_a7ddrphy_dq_o_nodelay7),
+ .TQ(soc_a7ddrphy_dq_t7)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed7),
+ .DDLY(soc_a7ddrphy_dq_i_delayed7),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data7[7]),
- .Q2(a7ddrphy_dq_i_data7[6]),
- .Q3(a7ddrphy_dq_i_data7[5]),
- .Q4(a7ddrphy_dq_i_data7[4]),
- .Q5(a7ddrphy_dq_i_data7[3]),
- .Q6(a7ddrphy_dq_i_data7[2]),
- .Q7(a7ddrphy_dq_i_data7[1]),
- .Q8(a7ddrphy_dq_i_data7[0])
+ .Q1(soc_a7ddrphy_dq_i_data7[7]),
+ .Q2(soc_a7ddrphy_dq_i_data7[6]),
+ .Q3(soc_a7ddrphy_dq_i_data7[5]),
+ .Q4(soc_a7ddrphy_dq_i_data7[4]),
+ .Q5(soc_a7ddrphy_dq_i_data7[3]),
+ .Q6(soc_a7ddrphy_dq_i_data7[2]),
+ .Q7(soc_a7ddrphy_dq_i_data7[1]),
+ .Q8(soc_a7ddrphy_dq_i_data7[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_9 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay7),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed7)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed7)
);
IOBUF IOBUF_7(
- .I(a7ddrphy_dq_o_nodelay7),
- .T(a7ddrphy_dq_t7),
+ .I(soc_a7ddrphy_dq_o_nodelay7),
+ .T(soc_a7ddrphy_dq_t7),
.IO(ddram_dq[7]),
- .O(a7ddrphy_dq_i_nodelay7)
+ .O(soc_a7ddrphy_dq_i_nodelay7)
);
OSERDESE2 #(
) OSERDESE2_38 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[8]),
- .D2(a7ddrphy_dfi_p0_wrdata[24]),
- .D3(a7ddrphy_dfi_p1_wrdata[8]),
- .D4(a7ddrphy_dfi_p1_wrdata[24]),
- .D5(a7ddrphy_dfi_p2_wrdata[8]),
- .D6(a7ddrphy_dfi_p2_wrdata[24]),
- .D7(a7ddrphy_dfi_p3_wrdata[8]),
- .D8(a7ddrphy_dfi_p3_wrdata[24]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay8),
- .TQ(a7ddrphy_dq_t8)
+ .OQ(soc_a7ddrphy_dq_o_nodelay8),
+ .TQ(soc_a7ddrphy_dq_t8)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed8),
+ .DDLY(soc_a7ddrphy_dq_i_delayed8),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data8[7]),
- .Q2(a7ddrphy_dq_i_data8[6]),
- .Q3(a7ddrphy_dq_i_data8[5]),
- .Q4(a7ddrphy_dq_i_data8[4]),
- .Q5(a7ddrphy_dq_i_data8[3]),
- .Q6(a7ddrphy_dq_i_data8[2]),
- .Q7(a7ddrphy_dq_i_data8[1]),
- .Q8(a7ddrphy_dq_i_data8[0])
+ .Q1(soc_a7ddrphy_dq_i_data8[7]),
+ .Q2(soc_a7ddrphy_dq_i_data8[6]),
+ .Q3(soc_a7ddrphy_dq_i_data8[5]),
+ .Q4(soc_a7ddrphy_dq_i_data8[4]),
+ .Q5(soc_a7ddrphy_dq_i_data8[3]),
+ .Q6(soc_a7ddrphy_dq_i_data8[2]),
+ .Q7(soc_a7ddrphy_dq_i_data8[1]),
+ .Q8(soc_a7ddrphy_dq_i_data8[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_10 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay8),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed8)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed8)
);
IOBUF IOBUF_8(
- .I(a7ddrphy_dq_o_nodelay8),
- .T(a7ddrphy_dq_t8),
+ .I(soc_a7ddrphy_dq_o_nodelay8),
+ .T(soc_a7ddrphy_dq_t8),
.IO(ddram_dq[8]),
- .O(a7ddrphy_dq_i_nodelay8)
+ .O(soc_a7ddrphy_dq_i_nodelay8)
);
OSERDESE2 #(
) OSERDESE2_39 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[9]),
- .D2(a7ddrphy_dfi_p0_wrdata[25]),
- .D3(a7ddrphy_dfi_p1_wrdata[9]),
- .D4(a7ddrphy_dfi_p1_wrdata[25]),
- .D5(a7ddrphy_dfi_p2_wrdata[9]),
- .D6(a7ddrphy_dfi_p2_wrdata[25]),
- .D7(a7ddrphy_dfi_p3_wrdata[9]),
- .D8(a7ddrphy_dfi_p3_wrdata[25]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay9),
- .TQ(a7ddrphy_dq_t9)
+ .OQ(soc_a7ddrphy_dq_o_nodelay9),
+ .TQ(soc_a7ddrphy_dq_t9)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed9),
+ .DDLY(soc_a7ddrphy_dq_i_delayed9),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data9[7]),
- .Q2(a7ddrphy_dq_i_data9[6]),
- .Q3(a7ddrphy_dq_i_data9[5]),
- .Q4(a7ddrphy_dq_i_data9[4]),
- .Q5(a7ddrphy_dq_i_data9[3]),
- .Q6(a7ddrphy_dq_i_data9[2]),
- .Q7(a7ddrphy_dq_i_data9[1]),
- .Q8(a7ddrphy_dq_i_data9[0])
+ .Q1(soc_a7ddrphy_dq_i_data9[7]),
+ .Q2(soc_a7ddrphy_dq_i_data9[6]),
+ .Q3(soc_a7ddrphy_dq_i_data9[5]),
+ .Q4(soc_a7ddrphy_dq_i_data9[4]),
+ .Q5(soc_a7ddrphy_dq_i_data9[3]),
+ .Q6(soc_a7ddrphy_dq_i_data9[2]),
+ .Q7(soc_a7ddrphy_dq_i_data9[1]),
+ .Q8(soc_a7ddrphy_dq_i_data9[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_11 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay9),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed9)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed9)
);
IOBUF IOBUF_9(
- .I(a7ddrphy_dq_o_nodelay9),
- .T(a7ddrphy_dq_t9),
+ .I(soc_a7ddrphy_dq_o_nodelay9),
+ .T(soc_a7ddrphy_dq_t9),
.IO(ddram_dq[9]),
- .O(a7ddrphy_dq_i_nodelay9)
+ .O(soc_a7ddrphy_dq_i_nodelay9)
);
OSERDESE2 #(
) OSERDESE2_40 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[10]),
- .D2(a7ddrphy_dfi_p0_wrdata[26]),
- .D3(a7ddrphy_dfi_p1_wrdata[10]),
- .D4(a7ddrphy_dfi_p1_wrdata[26]),
- .D5(a7ddrphy_dfi_p2_wrdata[10]),
- .D6(a7ddrphy_dfi_p2_wrdata[26]),
- .D7(a7ddrphy_dfi_p3_wrdata[10]),
- .D8(a7ddrphy_dfi_p3_wrdata[26]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay10),
- .TQ(a7ddrphy_dq_t10)
+ .OQ(soc_a7ddrphy_dq_o_nodelay10),
+ .TQ(soc_a7ddrphy_dq_t10)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed10),
+ .DDLY(soc_a7ddrphy_dq_i_delayed10),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data10[7]),
- .Q2(a7ddrphy_dq_i_data10[6]),
- .Q3(a7ddrphy_dq_i_data10[5]),
- .Q4(a7ddrphy_dq_i_data10[4]),
- .Q5(a7ddrphy_dq_i_data10[3]),
- .Q6(a7ddrphy_dq_i_data10[2]),
- .Q7(a7ddrphy_dq_i_data10[1]),
- .Q8(a7ddrphy_dq_i_data10[0])
+ .Q1(soc_a7ddrphy_dq_i_data10[7]),
+ .Q2(soc_a7ddrphy_dq_i_data10[6]),
+ .Q3(soc_a7ddrphy_dq_i_data10[5]),
+ .Q4(soc_a7ddrphy_dq_i_data10[4]),
+ .Q5(soc_a7ddrphy_dq_i_data10[3]),
+ .Q6(soc_a7ddrphy_dq_i_data10[2]),
+ .Q7(soc_a7ddrphy_dq_i_data10[1]),
+ .Q8(soc_a7ddrphy_dq_i_data10[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_12 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay10),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed10)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed10)
);
IOBUF IOBUF_10(
- .I(a7ddrphy_dq_o_nodelay10),
- .T(a7ddrphy_dq_t10),
+ .I(soc_a7ddrphy_dq_o_nodelay10),
+ .T(soc_a7ddrphy_dq_t10),
.IO(ddram_dq[10]),
- .O(a7ddrphy_dq_i_nodelay10)
+ .O(soc_a7ddrphy_dq_i_nodelay10)
);
OSERDESE2 #(
) OSERDESE2_41 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[11]),
- .D2(a7ddrphy_dfi_p0_wrdata[27]),
- .D3(a7ddrphy_dfi_p1_wrdata[11]),
- .D4(a7ddrphy_dfi_p1_wrdata[27]),
- .D5(a7ddrphy_dfi_p2_wrdata[11]),
- .D6(a7ddrphy_dfi_p2_wrdata[27]),
- .D7(a7ddrphy_dfi_p3_wrdata[11]),
- .D8(a7ddrphy_dfi_p3_wrdata[27]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay11),
- .TQ(a7ddrphy_dq_t11)
+ .OQ(soc_a7ddrphy_dq_o_nodelay11),
+ .TQ(soc_a7ddrphy_dq_t11)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed11),
+ .DDLY(soc_a7ddrphy_dq_i_delayed11),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data11[7]),
- .Q2(a7ddrphy_dq_i_data11[6]),
- .Q3(a7ddrphy_dq_i_data11[5]),
- .Q4(a7ddrphy_dq_i_data11[4]),
- .Q5(a7ddrphy_dq_i_data11[3]),
- .Q6(a7ddrphy_dq_i_data11[2]),
- .Q7(a7ddrphy_dq_i_data11[1]),
- .Q8(a7ddrphy_dq_i_data11[0])
+ .Q1(soc_a7ddrphy_dq_i_data11[7]),
+ .Q2(soc_a7ddrphy_dq_i_data11[6]),
+ .Q3(soc_a7ddrphy_dq_i_data11[5]),
+ .Q4(soc_a7ddrphy_dq_i_data11[4]),
+ .Q5(soc_a7ddrphy_dq_i_data11[3]),
+ .Q6(soc_a7ddrphy_dq_i_data11[2]),
+ .Q7(soc_a7ddrphy_dq_i_data11[1]),
+ .Q8(soc_a7ddrphy_dq_i_data11[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_13 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay11),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed11)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed11)
);
IOBUF IOBUF_11(
- .I(a7ddrphy_dq_o_nodelay11),
- .T(a7ddrphy_dq_t11),
+ .I(soc_a7ddrphy_dq_o_nodelay11),
+ .T(soc_a7ddrphy_dq_t11),
.IO(ddram_dq[11]),
- .O(a7ddrphy_dq_i_nodelay11)
+ .O(soc_a7ddrphy_dq_i_nodelay11)
);
OSERDESE2 #(
) OSERDESE2_42 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[12]),
- .D2(a7ddrphy_dfi_p0_wrdata[28]),
- .D3(a7ddrphy_dfi_p1_wrdata[12]),
- .D4(a7ddrphy_dfi_p1_wrdata[28]),
- .D5(a7ddrphy_dfi_p2_wrdata[12]),
- .D6(a7ddrphy_dfi_p2_wrdata[28]),
- .D7(a7ddrphy_dfi_p3_wrdata[12]),
- .D8(a7ddrphy_dfi_p3_wrdata[28]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay12),
- .TQ(a7ddrphy_dq_t12)
+ .OQ(soc_a7ddrphy_dq_o_nodelay12),
+ .TQ(soc_a7ddrphy_dq_t12)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed12),
+ .DDLY(soc_a7ddrphy_dq_i_delayed12),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data12[7]),
- .Q2(a7ddrphy_dq_i_data12[6]),
- .Q3(a7ddrphy_dq_i_data12[5]),
- .Q4(a7ddrphy_dq_i_data12[4]),
- .Q5(a7ddrphy_dq_i_data12[3]),
- .Q6(a7ddrphy_dq_i_data12[2]),
- .Q7(a7ddrphy_dq_i_data12[1]),
- .Q8(a7ddrphy_dq_i_data12[0])
+ .Q1(soc_a7ddrphy_dq_i_data12[7]),
+ .Q2(soc_a7ddrphy_dq_i_data12[6]),
+ .Q3(soc_a7ddrphy_dq_i_data12[5]),
+ .Q4(soc_a7ddrphy_dq_i_data12[4]),
+ .Q5(soc_a7ddrphy_dq_i_data12[3]),
+ .Q6(soc_a7ddrphy_dq_i_data12[2]),
+ .Q7(soc_a7ddrphy_dq_i_data12[1]),
+ .Q8(soc_a7ddrphy_dq_i_data12[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_14 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay12),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed12)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed12)
);
IOBUF IOBUF_12(
- .I(a7ddrphy_dq_o_nodelay12),
- .T(a7ddrphy_dq_t12),
+ .I(soc_a7ddrphy_dq_o_nodelay12),
+ .T(soc_a7ddrphy_dq_t12),
.IO(ddram_dq[12]),
- .O(a7ddrphy_dq_i_nodelay12)
+ .O(soc_a7ddrphy_dq_i_nodelay12)
);
OSERDESE2 #(
) OSERDESE2_43 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[13]),
- .D2(a7ddrphy_dfi_p0_wrdata[29]),
- .D3(a7ddrphy_dfi_p1_wrdata[13]),
- .D4(a7ddrphy_dfi_p1_wrdata[29]),
- .D5(a7ddrphy_dfi_p2_wrdata[13]),
- .D6(a7ddrphy_dfi_p2_wrdata[29]),
- .D7(a7ddrphy_dfi_p3_wrdata[13]),
- .D8(a7ddrphy_dfi_p3_wrdata[29]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay13),
- .TQ(a7ddrphy_dq_t13)
+ .OQ(soc_a7ddrphy_dq_o_nodelay13),
+ .TQ(soc_a7ddrphy_dq_t13)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed13),
+ .DDLY(soc_a7ddrphy_dq_i_delayed13),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data13[7]),
- .Q2(a7ddrphy_dq_i_data13[6]),
- .Q3(a7ddrphy_dq_i_data13[5]),
- .Q4(a7ddrphy_dq_i_data13[4]),
- .Q5(a7ddrphy_dq_i_data13[3]),
- .Q6(a7ddrphy_dq_i_data13[2]),
- .Q7(a7ddrphy_dq_i_data13[1]),
- .Q8(a7ddrphy_dq_i_data13[0])
+ .Q1(soc_a7ddrphy_dq_i_data13[7]),
+ .Q2(soc_a7ddrphy_dq_i_data13[6]),
+ .Q3(soc_a7ddrphy_dq_i_data13[5]),
+ .Q4(soc_a7ddrphy_dq_i_data13[4]),
+ .Q5(soc_a7ddrphy_dq_i_data13[3]),
+ .Q6(soc_a7ddrphy_dq_i_data13[2]),
+ .Q7(soc_a7ddrphy_dq_i_data13[1]),
+ .Q8(soc_a7ddrphy_dq_i_data13[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_15 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay13),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed13)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed13)
);
IOBUF IOBUF_13(
- .I(a7ddrphy_dq_o_nodelay13),
- .T(a7ddrphy_dq_t13),
+ .I(soc_a7ddrphy_dq_o_nodelay13),
+ .T(soc_a7ddrphy_dq_t13),
.IO(ddram_dq[13]),
- .O(a7ddrphy_dq_i_nodelay13)
+ .O(soc_a7ddrphy_dq_i_nodelay13)
);
OSERDESE2 #(
) OSERDESE2_44 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[14]),
- .D2(a7ddrphy_dfi_p0_wrdata[30]),
- .D3(a7ddrphy_dfi_p1_wrdata[14]),
- .D4(a7ddrphy_dfi_p1_wrdata[30]),
- .D5(a7ddrphy_dfi_p2_wrdata[14]),
- .D6(a7ddrphy_dfi_p2_wrdata[30]),
- .D7(a7ddrphy_dfi_p3_wrdata[14]),
- .D8(a7ddrphy_dfi_p3_wrdata[30]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay14),
- .TQ(a7ddrphy_dq_t14)
+ .OQ(soc_a7ddrphy_dq_o_nodelay14),
+ .TQ(soc_a7ddrphy_dq_t14)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed14),
+ .DDLY(soc_a7ddrphy_dq_i_delayed14),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data14[7]),
- .Q2(a7ddrphy_dq_i_data14[6]),
- .Q3(a7ddrphy_dq_i_data14[5]),
- .Q4(a7ddrphy_dq_i_data14[4]),
- .Q5(a7ddrphy_dq_i_data14[3]),
- .Q6(a7ddrphy_dq_i_data14[2]),
- .Q7(a7ddrphy_dq_i_data14[1]),
- .Q8(a7ddrphy_dq_i_data14[0])
+ .Q1(soc_a7ddrphy_dq_i_data14[7]),
+ .Q2(soc_a7ddrphy_dq_i_data14[6]),
+ .Q3(soc_a7ddrphy_dq_i_data14[5]),
+ .Q4(soc_a7ddrphy_dq_i_data14[4]),
+ .Q5(soc_a7ddrphy_dq_i_data14[3]),
+ .Q6(soc_a7ddrphy_dq_i_data14[2]),
+ .Q7(soc_a7ddrphy_dq_i_data14[1]),
+ .Q8(soc_a7ddrphy_dq_i_data14[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_16 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay14),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed14)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed14)
);
IOBUF IOBUF_14(
- .I(a7ddrphy_dq_o_nodelay14),
- .T(a7ddrphy_dq_t14),
+ .I(soc_a7ddrphy_dq_o_nodelay14),
+ .T(soc_a7ddrphy_dq_t14),
.IO(ddram_dq[14]),
- .O(a7ddrphy_dq_i_nodelay14)
+ .O(soc_a7ddrphy_dq_i_nodelay14)
);
OSERDESE2 #(
) OSERDESE2_45 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
- .D1(a7ddrphy_dfi_p0_wrdata[15]),
- .D2(a7ddrphy_dfi_p0_wrdata[31]),
- .D3(a7ddrphy_dfi_p1_wrdata[15]),
- .D4(a7ddrphy_dfi_p1_wrdata[31]),
- .D5(a7ddrphy_dfi_p2_wrdata[15]),
- .D6(a7ddrphy_dfi_p2_wrdata[31]),
- .D7(a7ddrphy_dfi_p3_wrdata[15]),
- .D8(a7ddrphy_dfi_p3_wrdata[31]),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
.OCE(1'd1),
.RST(sys_rst),
- .T1((~a7ddrphy_dq_oe_delayed)),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
.TCE(1'd1),
- .OQ(a7ddrphy_dq_o_nodelay15),
- .TQ(a7ddrphy_dq_t15)
+ .OQ(soc_a7ddrphy_dq_o_nodelay15),
+ .TQ(soc_a7ddrphy_dq_t15)
);
ISERDESE2 #(
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
- .DDLY(a7ddrphy_dq_i_delayed15),
+ .DDLY(soc_a7ddrphy_dq_i_delayed15),
.RST(sys_rst),
- .Q1(a7ddrphy_dq_i_data15[7]),
- .Q2(a7ddrphy_dq_i_data15[6]),
- .Q3(a7ddrphy_dq_i_data15[5]),
- .Q4(a7ddrphy_dq_i_data15[4]),
- .Q5(a7ddrphy_dq_i_data15[3]),
- .Q6(a7ddrphy_dq_i_data15[2]),
- .Q7(a7ddrphy_dq_i_data15[1]),
- .Q8(a7ddrphy_dq_i_data15[0])
+ .Q1(soc_a7ddrphy_dq_i_data15[7]),
+ .Q2(soc_a7ddrphy_dq_i_data15[6]),
+ .Q3(soc_a7ddrphy_dq_i_data15[5]),
+ .Q4(soc_a7ddrphy_dq_i_data15[4]),
+ .Q5(soc_a7ddrphy_dq_i_data15[3]),
+ .Q6(soc_a7ddrphy_dq_i_data15[2]),
+ .Q7(soc_a7ddrphy_dq_i_data15[1]),
+ .Q8(soc_a7ddrphy_dq_i_data15[0])
);
IDELAYE2 #(
.SIGNAL_PATTERN("DATA")
) IDELAYE2_17 (
.C(sys_clk),
- .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
- .IDATAIN(a7ddrphy_dq_i_nodelay15),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
.INC(1'd1),
- .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
- .DATAOUT(a7ddrphy_dq_i_delayed15)
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed15)
);
IOBUF IOBUF_15(
- .I(a7ddrphy_dq_o_nodelay15),
- .T(a7ddrphy_dq_t15),
+ .I(soc_a7ddrphy_dq_o_nodelay15),
+ .T(soc_a7ddrphy_dq_t15),
.IO(ddram_dq[15]),
- .O(a7ddrphy_dq_i_nodelay15)
+ .O(soc_a7ddrphy_dq_i_nodelay15)
);
reg [24:0] storage[0:15];
reg [24:0] memdat;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+ storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+ memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
reg [24:0] storage_1[0:15];
reg [24:0] memdat_1;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+ storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
reg [24:0] storage_2[0:15];
reg [24:0] memdat_2;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+ storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
reg [24:0] storage_3[0:15];
reg [24:0] memdat_3;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+ storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
reg [24:0] storage_4[0:15];
reg [24:0] memdat_4;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+ storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
reg [24:0] storage_5[0:15];
reg [24:0] memdat_5;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+ storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
reg [24:0] storage_6[0:15];
reg [24:0] memdat_6;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+ storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
reg [24:0] storage_7[0:15];
reg [24:0] memdat_7;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+ storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
PLLE2_ADV #(
.CLKFBOUT_MULT(5'd16),
.CLKIN1_PERIOD(10.0),
- .CLKOUT0_DIVIDE(5'd16),
+ .CLKOUT0_DIVIDE(4'd8),
.CLKOUT0_PHASE(1'd0),
- .CLKOUT1_DIVIDE(3'd4),
+ .CLKOUT1_DIVIDE(5'd16),
.CLKOUT1_PHASE(1'd0),
.CLKOUT2_DIVIDE(3'd4),
- .CLKOUT2_PHASE(7'd90),
+ .CLKOUT2_PHASE(1'd0),
+ .CLKOUT3_DIVIDE(3'd4),
+ .CLKOUT3_PHASE(7'd90),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
- .CLKFBIN(pll_fb0),
- .CLKIN1(s7pll0_clkin),
- .RST(sys_pll_reset),
- .CLKFBOUT(pll_fb0),
- .CLKOUT0(s7pll0_clkout0),
- .CLKOUT1(s7pll0_clkout1),
- .CLKOUT2(s7pll0_clkout2),
- .LOCKED(sys_pll_locked)
-);
-
-PLLE2_ADV #(
- .CLKFBOUT_MULT(5'd16),
- .CLKIN1_PERIOD(10.0),
- .CLKOUT0_DIVIDE(4'd8),
- .CLKOUT0_PHASE(1'd0),
- .DIVCLK_DIVIDE(1'd1),
- .REF_JITTER1(0.01),
- .STARTUP_WAIT("FALSE")
-) PLLE2_ADV_1 (
- .CLKFBIN(pll_fb1),
- .CLKIN1(s7pll1_clkin),
- .RST(iodelay_pll_reset),
- .CLKFBOUT(pll_fb1),
- .CLKOUT0(s7pll1_clkout),
- .LOCKED(iodelay_pll_locked)
+ .CLKFBIN(vns_pll_fb),
+ .CLKIN1(soc_clkin),
+ .RST(soc_reset),
+ .CLKFBOUT(vns_pll_fb),
+ .CLKOUT0(soc_clkout0),
+ .CLKOUT1(soc_clkout1),
+ .CLKOUT2(soc_clkout2),
+ .CLKOUT3(soc_clkout3),
+ .LOCKED(soc_locked)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE (
- .C(sys_clk),
+ .C(iodelay_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl0),
- .Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_1 (
- .C(sys_clk),
+ .C(iodelay_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl0_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl0),
- .Q(sys_rst)
+ .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(iodelay_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_2 (
- .C(sys4x_clk),
+ .C(sys_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl1),
- .Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_3 (
- .C(sys4x_clk),
+ .C(sys_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl1_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl1),
- .Q(xilinxasyncresetsynchronizerimpl1_expr)
+ .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(sys_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_4 (
- .C(sys4x_dqs_clk),
+ .C(sys4x_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl2),
- .Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_5 (
- .C(sys4x_dqs_clk),
+ .C(sys4x_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl2_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl2),
- .Q(xilinxasyncresetsynchronizerimpl2_expr)
+ .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_expr)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_6 (
- .C(iodelay_clk),
+ .C(sys4x_dqs_clk),
.CE(1'd1),
.D(1'd0),
- .PRE(xilinxasyncresetsynchronizerimpl3),
- .Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_7 (
- .C(iodelay_clk),
+ .C(sys4x_dqs_clk),
.CE(1'd1),
- .D(xilinxasyncresetsynchronizerimpl3_rst_meta),
- .PRE(xilinxasyncresetsynchronizerimpl3),
- .Q(iodelay_rst)
+ .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(vns_xilinxasyncresetsynchronizerimpl3_expr)
);
endmodule
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:54
+// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:06
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
reg litedramcore_master_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p3_rddata;
wire litedramcore_master_p3_rddata_valid;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
reg [3:0] litedramcore_storage = 4'd1;
reg litedramcore_re = 1'd0;
reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
endcase
end
always @(*) begin
- litedramcore_we = 1'd0;
+ litedramcore_adr = 14'd0;
case (state)
1'd1: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ litedramcore_adr = litedramcore_wishbone_adr;
end
end
endcase
end
always @(*) begin
- litedramcore_wishbone_ack = 1'd0;
+ litedramcore_we = 1'd0;
case (state)
1'd1: begin
- litedramcore_wishbone_ack = 1'd1;
end
default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
end
endcase
end
always @(*) begin
- litedramcore_adr = 14'd0;
+ litedramcore_wishbone_ack = 1'd0;
case (state)
1'd1: begin
+ litedramcore_wishbone_ack = 1'd1;
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr = litedramcore_wishbone_adr;
- end
end
endcase
end
ddrphy_writes0[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write_col0 = 10'd0;
+ ddrphy_bank_write0 = 1'd0;
case (ddrphy_writes0)
1'd1: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0);
end
2'd2: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0);
end
3'd4: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0);
end
4'd8: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0);
end
endcase
end
always @(*) begin
- ddrphy_bank_write0 = 1'd0;
+ ddrphy_bank_write_col0 = 10'd0;
case (ddrphy_writes0)
1'd1: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_activates1[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
- ddrphy_bankmodel1_activate = 1'd0;
+ ddrphy_bankmodel1_activate_row = 14'd0;
case (ddrphy_activates1)
1'd1: begin
- ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1);
+ ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1);
+ ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1);
+ ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1);
+ ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bankmodel1_activate_row = 14'd0;
+ ddrphy_bankmodel1_activate = 1'd0;
case (ddrphy_activates1)
1'd1: begin
- ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1);
end
2'd2: begin
- ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1);
end
3'd4: begin
- ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1);
end
4'd8: begin
- ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1);
end
endcase
end
ddrphy_writes1[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write1 = 1'd0;
+ ddrphy_bank_write_col1 = 10'd0;
case (ddrphy_writes1)
1'd1: begin
- ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1);
+ ddrphy_bank_write_col1 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1);
+ ddrphy_bank_write_col1 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1);
+ ddrphy_bank_write_col1 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1);
+ ddrphy_bank_write_col1 = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bank_write_col1 = 10'd0;
+ ddrphy_bank_write1 = 1'd0;
case (ddrphy_writes1)
1'd1: begin
- ddrphy_bank_write_col1 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1);
end
2'd2: begin
- ddrphy_bank_write_col1 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1);
end
3'd4: begin
- ddrphy_bank_write_col1 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1);
end
4'd8: begin
- ddrphy_bank_write_col1 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1);
end
endcase
end
ddrphy_reads2[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
- ddrphy_bankmodel2_read_col = 10'd0;
+ ddrphy_bankmodel2_read = 1'd0;
case (ddrphy_reads2)
1'd1: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2);
end
2'd2: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2);
end
3'd4: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2);
end
4'd8: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2);
end
endcase
end
always @(*) begin
- ddrphy_bankmodel2_read = 1'd0;
+ ddrphy_bankmodel2_read_col = 10'd0;
case (ddrphy_reads2)
1'd1: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_activates4[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
- ddrphy_bankmodel4_activate_row = 14'd0;
+ ddrphy_bankmodel4_activate = 1'd0;
case (ddrphy_activates4)
1'd1: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
always @(*) begin
- ddrphy_bankmodel4_activate = 1'd0;
+ ddrphy_bankmodel4_activate_row = 14'd0;
case (ddrphy_activates4)
1'd1: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_writes4[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write_col4 = 10'd0;
+ ddrphy_bank_write4 = 1'd0;
case (ddrphy_writes4)
1'd1: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
always @(*) begin
- ddrphy_bank_write4 = 1'd0;
+ ddrphy_bank_write_col4 = 10'd0;
case (ddrphy_writes4)
1'd1: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_reads4[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
- ddrphy_bankmodel4_read = 1'd0;
+ ddrphy_bankmodel4_read_col = 10'd0;
case (ddrphy_reads4)
1'd1: begin
- ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4);
+ ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4);
+ ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4);
+ ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4);
+ ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bankmodel4_read_col = 10'd0;
+ ddrphy_bankmodel4_read = 1'd0;
case (ddrphy_reads4)
1'd1: begin
- ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
- ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
- ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
- ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
ddrphy_writes5[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write5 = 1'd0;
+ ddrphy_bank_write_col5 = 10'd0;
case (ddrphy_writes5)
1'd1: begin
- ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5);
+ ddrphy_bank_write_col5 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5);
+ ddrphy_bank_write_col5 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5);
+ ddrphy_bank_write_col5 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5);
+ ddrphy_bank_write_col5 = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bank_write_col5 = 10'd0;
+ ddrphy_bank_write5 = 1'd0;
case (ddrphy_writes5)
1'd1: begin
- ddrphy_bank_write_col5 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5);
end
2'd2: begin
- ddrphy_bank_write_col5 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5);
end
3'd4: begin
- ddrphy_bank_write_col5 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5);
end
4'd8: begin
- ddrphy_bank_write_col5 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5);
end
endcase
end
ddrphy_reads5[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
- ddrphy_bankmodel5_read_col = 10'd0;
+ ddrphy_bankmodel5_read = 1'd0;
case (ddrphy_reads5)
1'd1: begin
- ddrphy_bankmodel5_read_col = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel5_read = (ddrphy_dfi_p0_bank == 3'd5);
end
2'd2: begin
- ddrphy_bankmodel5_read_col = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel5_read = (ddrphy_dfi_p1_bank == 3'd5);
end
3'd4: begin
- ddrphy_bankmodel5_read_col = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel5_read = (ddrphy_dfi_p2_bank == 3'd5);
end
4'd8: begin
- ddrphy_bankmodel5_read_col = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel5_read = (ddrphy_dfi_p3_bank == 3'd5);
end
endcase
end
always @(*) begin
- ddrphy_bankmodel5_read = 1'd0;
+ ddrphy_bankmodel5_read_col = 10'd0;
case (ddrphy_reads5)
1'd1: begin
- ddrphy_bankmodel5_read = (ddrphy_dfi_p0_bank == 3'd5);
+ ddrphy_bankmodel5_read_col = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel5_read = (ddrphy_dfi_p1_bank == 3'd5);
+ ddrphy_bankmodel5_read_col = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel5_read = (ddrphy_dfi_p2_bank == 3'd5);
+ ddrphy_bankmodel5_read_col = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel5_read = (ddrphy_dfi_p3_bank == 3'd5);
+ ddrphy_bankmodel5_read_col = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_activates6[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
- ddrphy_bankmodel6_activate = 1'd0;
+ ddrphy_bankmodel6_activate_row = 14'd0;
case (ddrphy_activates6)
1'd1: begin
- ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6);
+ ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6);
+ ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6);
+ ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6);
+ ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bankmodel6_activate_row = 14'd0;
+ ddrphy_bankmodel6_activate = 1'd0;
case (ddrphy_activates6)
1'd1: begin
- ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6);
end
2'd2: begin
- ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6);
end
3'd4: begin
- ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6);
end
4'd8: begin
- ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6);
end
endcase
end
ddrphy_activates7[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
- ddrphy_bankmodel7_activate_row = 14'd0;
+ ddrphy_bankmodel7_activate = 1'd0;
case (ddrphy_activates7)
1'd1: begin
- ddrphy_bankmodel7_activate_row = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel7_activate = (ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
- ddrphy_bankmodel7_activate_row = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel7_activate = (ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
- ddrphy_bankmodel7_activate_row = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel7_activate = (ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
- ddrphy_bankmodel7_activate_row = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel7_activate = (ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
always @(*) begin
- ddrphy_bankmodel7_activate = 1'd0;
+ ddrphy_bankmodel7_activate_row = 14'd0;
case (ddrphy_activates7)
1'd1: begin
- ddrphy_bankmodel7_activate = (ddrphy_dfi_p0_bank == 3'd7);
+ ddrphy_bankmodel7_activate_row = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel7_activate = (ddrphy_dfi_p1_bank == 3'd7);
+ ddrphy_bankmodel7_activate_row = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel7_activate = (ddrphy_dfi_p2_bank == 3'd7);
+ ddrphy_bankmodel7_activate_row = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel7_activate = (ddrphy_dfi_p3_bank == 3'd7);
+ ddrphy_bankmodel7_activate_row = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_reads7[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
- ddrphy_bankmodel7_read = 1'd0;
+ ddrphy_bankmodel7_read_col = 10'd0;
case (ddrphy_reads7)
1'd1: begin
- ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7);
+ ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7);
+ ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7);
+ ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7);
+ ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bankmodel7_read_col = 10'd0;
+ ddrphy_bankmodel7_read = 1'd0;
case (ddrphy_reads7)
1'd1: begin
- ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
- ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
- ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
- ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
end
end
always @(*) begin
- ddrphy_dfiphasemodel0_read = 1'd0;
+ ddrphy_dfiphasemodel0_write = 1'd0;
if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin
- ddrphy_dfiphasemodel0_read = ddrphy_dfi_p0_we_n;
+ ddrphy_dfiphasemodel0_write = (~ddrphy_dfi_p0_we_n);
end
end
always @(*) begin
- ddrphy_dfiphasemodel0_write = 1'd0;
+ ddrphy_dfiphasemodel0_read = 1'd0;
if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin
- ddrphy_dfiphasemodel0_write = (~ddrphy_dfi_p0_we_n);
+ ddrphy_dfiphasemodel0_read = ddrphy_dfi_p0_we_n;
end
end
always @(*) begin
- ddrphy_dfiphasemodel1_activate = 1'd0;
+ ddrphy_dfiphasemodel1_precharge = 1'd0;
if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin
- ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n;
+ ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n);
end
end
always @(*) begin
- ddrphy_dfiphasemodel1_precharge = 1'd0;
+ ddrphy_dfiphasemodel1_activate = 1'd0;
if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin
- ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n);
+ ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n;
end
end
always @(*) begin
end
end
always @(*) begin
- ddrphy_dfiphasemodel2_precharge = 1'd0;
+ ddrphy_dfiphasemodel2_activate = 1'd0;
if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin
- ddrphy_dfiphasemodel2_precharge = (~ddrphy_dfi_p2_we_n);
+ ddrphy_dfiphasemodel2_activate = ddrphy_dfi_p2_we_n;
end
end
always @(*) begin
- ddrphy_dfiphasemodel2_activate = 1'd0;
+ ddrphy_dfiphasemodel2_precharge = 1'd0;
if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin
- ddrphy_dfiphasemodel2_activate = ddrphy_dfi_p2_we_n;
+ ddrphy_dfiphasemodel2_precharge = (~ddrphy_dfi_p2_we_n);
end
end
always @(*) begin
end
end
always @(*) begin
- ddrphy_dfiphasemodel3_write = 1'd0;
+ ddrphy_dfiphasemodel3_read = 1'd0;
if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin
- ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n);
+ ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n;
end
end
always @(*) begin
- ddrphy_dfiphasemodel3_read = 1'd0;
+ ddrphy_dfiphasemodel3_write = 1'd0;
if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin
- ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n;
+ ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n);
end
end
assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
-always @(*) begin
- ddrphy_bankmodel0_read_data = 128'd0;
- if (ddrphy_bankmodel0_active) begin
- if (ddrphy_bankmodel0_read) begin
- ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r;
- end
- end
-end
-always @(*) begin
- ddrphy_bankmodel0_write_port_adr = 21'd0;
- if (ddrphy_bankmodel0_active) begin
- ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr;
- end
-end
always @(*) begin
ddrphy_bankmodel0_write_port_we = 16'd0;
if (ddrphy_bankmodel0_active) begin
end
end
end
-assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
-assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
always @(*) begin
- ddrphy_bankmodel1_write_port_adr = 21'd0;
- if (ddrphy_bankmodel1_active) begin
- ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr;
+ ddrphy_bankmodel0_read_data = 128'd0;
+ if (ddrphy_bankmodel0_active) begin
+ if (ddrphy_bankmodel0_read) begin
+ ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r;
+ end
end
end
always @(*) begin
- ddrphy_bankmodel1_write_port_we = 16'd0;
- if (ddrphy_bankmodel1_active) begin
- if (4'd8) begin
- ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask));
- end else begin
- ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write;
- end
+ ddrphy_bankmodel0_write_port_adr = 21'd0;
+ if (ddrphy_bankmodel0_active) begin
+ ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr;
end
end
+assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
+assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
always @(*) begin
ddrphy_bankmodel1_write_port_dat_w = 128'd0;
if (ddrphy_bankmodel1_active) begin
end
end
end
+always @(*) begin
+ ddrphy_bankmodel1_write_port_adr = 21'd0;
+ if (ddrphy_bankmodel1_active) begin
+ ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr;
+ end
+end
+always @(*) begin
+ ddrphy_bankmodel1_write_port_we = 16'd0;
+ if (ddrphy_bankmodel1_active) begin
+ if (4'd8) begin
+ ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask));
+ end else begin
+ ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write;
+ end
+ end
+end
assign ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
assign ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
+always @(*) begin
+ ddrphy_bankmodel2_read_data = 128'd0;
+ if (ddrphy_bankmodel2_active) begin
+ if (ddrphy_bankmodel2_read) begin
+ ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r;
+ end
+ end
+end
always @(*) begin
ddrphy_bankmodel2_write_port_adr = 21'd0;
if (ddrphy_bankmodel2_active) begin
end
end
end
+assign ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
+assign ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
always @(*) begin
- ddrphy_bankmodel2_read_data = 128'd0;
- if (ddrphy_bankmodel2_active) begin
- if (ddrphy_bankmodel2_read) begin
- ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r;
+ ddrphy_bankmodel3_read_data = 128'd0;
+ if (ddrphy_bankmodel3_active) begin
+ if (ddrphy_bankmodel3_read) begin
+ ddrphy_bankmodel3_read_data = ddrphy_bankmodel3_read_port_dat_r;
end
end
end
-assign ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
-assign ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
+always @(*) begin
+ ddrphy_bankmodel3_write_port_adr = 21'd0;
+ if (ddrphy_bankmodel3_active) begin
+ ddrphy_bankmodel3_write_port_adr = ddrphy_bankmodel3_wraddr;
+ end
+end
always @(*) begin
ddrphy_bankmodel3_write_port_we = 16'd0;
if (ddrphy_bankmodel3_active) begin
end
end
end
-always @(*) begin
- ddrphy_bankmodel3_read_data = 128'd0;
- if (ddrphy_bankmodel3_active) begin
- if (ddrphy_bankmodel3_read) begin
- ddrphy_bankmodel3_read_data = ddrphy_bankmodel3_read_port_dat_r;
- end
- end
-end
-always @(*) begin
- ddrphy_bankmodel3_write_port_adr = 21'd0;
- if (ddrphy_bankmodel3_active) begin
- ddrphy_bankmodel3_write_port_adr = ddrphy_bankmodel3_wraddr;
- end
-end
assign ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
assign ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
-always @(*) begin
- ddrphy_bankmodel4_read_port_adr = 21'd0;
- if (ddrphy_bankmodel4_active) begin
- if (ddrphy_bankmodel4_read) begin
- ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr;
- end
- end
-end
always @(*) begin
ddrphy_bankmodel4_read_data = 128'd0;
if (ddrphy_bankmodel4_active) begin
ddrphy_bankmodel4_write_port_dat_w = ddrphy_bankmodel4_write_data;
end
end
-assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
-assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
always @(*) begin
- ddrphy_bankmodel5_read_data = 128'd0;
- if (ddrphy_bankmodel5_active) begin
- if (ddrphy_bankmodel5_read) begin
- ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r;
+ ddrphy_bankmodel4_read_port_adr = 21'd0;
+ if (ddrphy_bankmodel4_active) begin
+ if (ddrphy_bankmodel4_read) begin
+ ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr;
end
end
end
+assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
+assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
always @(*) begin
ddrphy_bankmodel5_write_port_adr = 21'd0;
if (ddrphy_bankmodel5_active) begin
end
end
end
-assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
-assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
always @(*) begin
- ddrphy_bankmodel6_read_data = 128'd0;
- if (ddrphy_bankmodel6_active) begin
- if (ddrphy_bankmodel6_read) begin
- ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r;
+ ddrphy_bankmodel5_read_data = 128'd0;
+ if (ddrphy_bankmodel5_active) begin
+ if (ddrphy_bankmodel5_read) begin
+ ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r;
end
end
end
+assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
+assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
always @(*) begin
ddrphy_bankmodel6_write_port_adr = 21'd0;
if (ddrphy_bankmodel6_active) begin
end
end
end
-assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
-assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
always @(*) begin
- ddrphy_bankmodel7_read_data = 128'd0;
- if (ddrphy_bankmodel7_active) begin
- if (ddrphy_bankmodel7_read) begin
- ddrphy_bankmodel7_read_data = ddrphy_bankmodel7_read_port_dat_r;
+ ddrphy_bankmodel6_read_data = 128'd0;
+ if (ddrphy_bankmodel6_active) begin
+ if (ddrphy_bankmodel6_read) begin
+ ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r;
end
end
end
-always @(*) begin
- ddrphy_bankmodel7_write_port_adr = 21'd0;
- if (ddrphy_bankmodel7_active) begin
- ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr;
- end
-end
+assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
+assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
always @(*) begin
ddrphy_bankmodel7_write_port_we = 16'd0;
if (ddrphy_bankmodel7_active) begin
end
end
end
+always @(*) begin
+ ddrphy_bankmodel7_read_data = 128'd0;
+ if (ddrphy_bankmodel7_active) begin
+ if (ddrphy_bankmodel7_read) begin
+ ddrphy_bankmodel7_read_data = ddrphy_bankmodel7_read_port_dat_r;
+ end
+ end
+end
+always @(*) begin
+ ddrphy_bankmodel7_write_port_adr = 21'd0;
+ if (ddrphy_bankmodel7_active) begin
+ ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr;
+ end
+end
assign ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
- litedramcore_master_p1_cs_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n;
+ litedramcore_master_p3_wrdata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata;
end else begin
- litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n;
+ litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata;
end
end
always @(*) begin
- litedramcore_master_p1_ras_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n;
+ litedramcore_inti_p0_rddata = 32'd0;
+ if (litedramcore_sel) begin
end else begin
- litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n;
+ litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata;
end
end
always @(*) begin
- litedramcore_slave_p1_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata;
+ litedramcore_master_p3_wrdata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en;
end else begin
+ litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en;
end
end
always @(*) begin
- litedramcore_master_p1_we_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n;
+ litedramcore_inti_p0_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
end else begin
- litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n;
+ litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
end
end
always @(*) begin
- litedramcore_slave_p1_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
+ litedramcore_master_p3_wrdata_mask = 4'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask;
end else begin
+ litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask;
end
end
always @(*) begin
- litedramcore_master_p1_cke = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cke = litedramcore_slave_p1_cke;
+ litedramcore_master_p3_rddata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en;
end else begin
- litedramcore_master_p1_cke = litedramcore_inti_p1_cke;
+ litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en;
end
end
always @(*) begin
- litedramcore_master_p1_odt = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_odt = litedramcore_slave_p1_odt;
+ litedramcore_master_p0_address = 14'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_address = litedramcore_slave_p0_address;
end else begin
- litedramcore_master_p1_odt = litedramcore_inti_p1_odt;
+ litedramcore_master_p0_address = litedramcore_inti_p0_address;
end
end
always @(*) begin
- litedramcore_master_p1_reset_n = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n;
+ litedramcore_master_p0_bank = 3'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_bank = litedramcore_slave_p0_bank;
end else begin
- litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n;
+ litedramcore_master_p0_bank = litedramcore_inti_p0_bank;
end
end
always @(*) begin
- litedramcore_master_p1_act_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n;
+ litedramcore_master_p0_cas_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n;
end else begin
- litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n;
+ litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n;
end
end
always @(*) begin
- litedramcore_master_p1_wrdata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata;
+ litedramcore_master_p0_cs_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n;
end else begin
- litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata;
+ litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n;
end
end
always @(*) begin
- litedramcore_inti_p2_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_master_p0_ras_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n;
end else begin
- litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata;
+ litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n;
end
end
always @(*) begin
- litedramcore_master_p1_wrdata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en;
+ litedramcore_slave_p0_rddata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata;
end else begin
- litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en;
end
end
always @(*) begin
- litedramcore_inti_p2_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_master_p0_we_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n;
end else begin
- litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n;
end
end
always @(*) begin
- litedramcore_master_p1_wrdata_mask = 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask;
+ litedramcore_slave_p0_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
end else begin
- litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask;
end
end
always @(*) begin
- litedramcore_master_p1_rddata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en;
+ litedramcore_master_p0_cke = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_cke = litedramcore_slave_p0_cke;
end else begin
- litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en;
+ litedramcore_master_p0_cke = litedramcore_inti_p0_cke;
end
end
always @(*) begin
- litedramcore_master_p2_address = 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_address = litedramcore_slave_p2_address;
+ litedramcore_master_p0_odt = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_odt = litedramcore_slave_p0_odt;
end else begin
- litedramcore_master_p2_address = litedramcore_inti_p2_address;
+ litedramcore_master_p0_odt = litedramcore_inti_p0_odt;
end
end
always @(*) begin
- litedramcore_master_p2_bank = 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_bank = litedramcore_slave_p2_bank;
+ litedramcore_master_p0_reset_n = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n;
end else begin
- litedramcore_master_p2_bank = litedramcore_inti_p2_bank;
+ litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n;
end
end
always @(*) begin
- litedramcore_master_p2_cas_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n;
+ litedramcore_master_p0_act_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n;
end else begin
- litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n;
+ litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n;
end
end
always @(*) begin
- litedramcore_master_p2_cs_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n;
+ litedramcore_master_p0_wrdata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata;
end else begin
- litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n;
+ litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata;
end
end
always @(*) begin
- litedramcore_master_p2_ras_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n;
+ litedramcore_inti_p1_rddata = 32'd0;
+ if (litedramcore_sel) begin
end else begin
- litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n;
+ litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata;
end
end
always @(*) begin
- litedramcore_slave_p2_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata;
+ litedramcore_master_p0_wrdata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en;
end else begin
+ litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en;
end
end
always @(*) begin
- litedramcore_master_p2_we_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n;
+ litedramcore_inti_p1_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
end else begin
- litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n;
+ litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
end
end
always @(*) begin
- litedramcore_slave_p2_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p0_wrdata_mask = 4'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask;
end else begin
+ litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask;
end
end
always @(*) begin
- litedramcore_master_p2_cke = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cke = litedramcore_slave_p2_cke;
+ litedramcore_master_p0_rddata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en;
end else begin
- litedramcore_master_p2_cke = litedramcore_inti_p2_cke;
+ litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en;
end
end
always @(*) begin
- litedramcore_master_p2_odt = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_odt = litedramcore_slave_p2_odt;
+ litedramcore_master_p1_address = 14'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_address = litedramcore_slave_p1_address;
end else begin
- litedramcore_master_p2_odt = litedramcore_inti_p2_odt;
+ litedramcore_master_p1_address = litedramcore_inti_p1_address;
end
end
always @(*) begin
- litedramcore_master_p2_reset_n = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n;
+ litedramcore_master_p1_bank = 3'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_bank = litedramcore_slave_p1_bank;
end else begin
- litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n;
+ litedramcore_master_p1_bank = litedramcore_inti_p1_bank;
end
end
always @(*) begin
- litedramcore_master_p2_act_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n;
+ litedramcore_master_p1_cas_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n;
end else begin
- litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n;
+ litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n;
end
end
always @(*) begin
- litedramcore_master_p2_wrdata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata;
+ litedramcore_master_p1_cs_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n;
end else begin
- litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata;
+ litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n;
end
end
always @(*) begin
- litedramcore_inti_p3_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_ras_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n;
end else begin
- litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata;
+ litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n;
end
end
always @(*) begin
- litedramcore_master_p2_wrdata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en;
+ litedramcore_slave_p1_rddata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata;
end else begin
- litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en;
end
end
always @(*) begin
- litedramcore_inti_p3_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_we_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n;
end else begin
- litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
+ litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n;
end
end
always @(*) begin
- litedramcore_master_p2_wrdata_mask = 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask;
+ litedramcore_slave_p1_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
end else begin
- litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask;
end
end
always @(*) begin
- litedramcore_master_p2_rddata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en;
+ litedramcore_master_p1_cke = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_cke = litedramcore_slave_p1_cke;
end else begin
- litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en;
+ litedramcore_master_p1_cke = litedramcore_inti_p1_cke;
end
end
always @(*) begin
- litedramcore_master_p3_address = 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_address = litedramcore_slave_p3_address;
+ litedramcore_master_p1_odt = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_odt = litedramcore_slave_p1_odt;
end else begin
- litedramcore_master_p3_address = litedramcore_inti_p3_address;
+ litedramcore_master_p1_odt = litedramcore_inti_p1_odt;
end
end
always @(*) begin
- litedramcore_master_p3_bank = 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_bank = litedramcore_slave_p3_bank;
+ litedramcore_master_p1_reset_n = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n;
end else begin
- litedramcore_master_p3_bank = litedramcore_inti_p3_bank;
+ litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n;
end
end
always @(*) begin
- litedramcore_master_p3_cas_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n;
+ litedramcore_master_p1_act_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n;
end else begin
- litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n;
+ litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n;
end
end
always @(*) begin
- litedramcore_master_p3_cs_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n;
+ litedramcore_master_p1_wrdata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata;
end else begin
- litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n;
+ litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata;
end
end
always @(*) begin
- litedramcore_master_p3_ras_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n;
+ litedramcore_inti_p2_rddata = 32'd0;
+ if (litedramcore_sel) begin
end else begin
- litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n;
+ litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata;
end
end
always @(*) begin
- litedramcore_slave_p3_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata;
+ litedramcore_master_p1_wrdata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en;
end else begin
+ litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en;
end
end
always @(*) begin
- litedramcore_master_p3_we_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n;
+ litedramcore_inti_p2_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
end else begin
- litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n;
+ litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
end
end
always @(*) begin
- litedramcore_slave_p3_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
+ litedramcore_master_p1_wrdata_mask = 4'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask;
end else begin
+ litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask;
end
end
always @(*) begin
- litedramcore_master_p3_cke = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cke = litedramcore_slave_p3_cke;
+ litedramcore_master_p1_rddata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p3_cke = litedramcore_inti_p3_cke;
+ litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en;
end
end
always @(*) begin
- litedramcore_master_p3_odt = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_odt = litedramcore_slave_p3_odt;
+ litedramcore_master_p2_address = 14'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_address = litedramcore_slave_p2_address;
end else begin
- litedramcore_master_p3_odt = litedramcore_inti_p3_odt;
+ litedramcore_master_p2_address = litedramcore_inti_p2_address;
end
end
always @(*) begin
- litedramcore_master_p3_reset_n = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n;
+ litedramcore_master_p2_bank = 3'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_bank = litedramcore_slave_p2_bank;
end else begin
- litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n;
+ litedramcore_master_p2_bank = litedramcore_inti_p2_bank;
end
end
always @(*) begin
- litedramcore_master_p3_act_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n;
+ litedramcore_master_p2_cas_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n;
end else begin
- litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n;
+ litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n;
end
end
always @(*) begin
- litedramcore_master_p3_wrdata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata;
+ litedramcore_master_p2_cs_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n;
end else begin
- litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata;
+ litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n;
end
end
always @(*) begin
- litedramcore_inti_p0_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_ras_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n;
end else begin
- litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata;
+ litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n;
end
end
always @(*) begin
- litedramcore_master_p3_wrdata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en;
+ litedramcore_slave_p2_rddata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata;
end else begin
- litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en;
end
end
always @(*) begin
- litedramcore_inti_p0_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_we_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n;
end else begin
- litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
+ litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n;
end
end
always @(*) begin
- litedramcore_master_p3_wrdata_mask = 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask;
+ litedramcore_slave_p2_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cke = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_cke = litedramcore_slave_p2_cke;
end else begin
- litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask;
+ litedramcore_master_p2_cke = litedramcore_inti_p2_cke;
end
end
always @(*) begin
- litedramcore_master_p3_rddata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en;
+ litedramcore_master_p2_odt = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_odt = litedramcore_slave_p2_odt;
end else begin
- litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en;
+ litedramcore_master_p2_odt = litedramcore_inti_p2_odt;
end
end
always @(*) begin
- litedramcore_master_p0_address = 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_address = litedramcore_slave_p0_address;
+ litedramcore_master_p2_reset_n = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n;
end else begin
- litedramcore_master_p0_address = litedramcore_inti_p0_address;
+ litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n;
end
end
always @(*) begin
- litedramcore_master_p0_bank = 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_bank = litedramcore_slave_p0_bank;
+ litedramcore_master_p2_act_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n;
end else begin
- litedramcore_master_p0_bank = litedramcore_inti_p0_bank;
+ litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n;
end
end
always @(*) begin
- litedramcore_master_p0_cas_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n;
+ litedramcore_master_p2_wrdata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata;
end else begin
- litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n;
+ litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata;
end
end
always @(*) begin
- litedramcore_master_p0_cs_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n;
+ litedramcore_inti_p3_rddata = 32'd0;
+ if (litedramcore_sel) begin
end else begin
- litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n;
+ litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata;
end
end
always @(*) begin
- litedramcore_master_p0_ras_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n;
+ litedramcore_master_p2_wrdata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en;
end else begin
- litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n;
+ litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en;
end
end
always @(*) begin
- litedramcore_slave_p0_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata;
+ litedramcore_inti_p3_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
end else begin
+ litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
end
end
always @(*) begin
- litedramcore_master_p0_we_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n;
+ litedramcore_master_p2_wrdata_mask = 4'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask;
end else begin
- litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n;
+ litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask;
end
end
always @(*) begin
- litedramcore_slave_p0_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
+ litedramcore_master_p2_rddata_en = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en;
end else begin
+ litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en;
end
end
always @(*) begin
- litedramcore_master_p0_cke = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cke = litedramcore_slave_p0_cke;
+ litedramcore_master_p3_address = 14'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_address = litedramcore_slave_p3_address;
end else begin
- litedramcore_master_p0_cke = litedramcore_inti_p0_cke;
+ litedramcore_master_p3_address = litedramcore_inti_p3_address;
end
end
always @(*) begin
- litedramcore_master_p0_odt = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_odt = litedramcore_slave_p0_odt;
+ litedramcore_master_p3_bank = 3'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_bank = litedramcore_slave_p3_bank;
end else begin
- litedramcore_master_p0_odt = litedramcore_inti_p0_odt;
+ litedramcore_master_p3_bank = litedramcore_inti_p3_bank;
end
end
always @(*) begin
- litedramcore_master_p0_reset_n = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n;
+ litedramcore_master_p3_cas_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n;
end else begin
- litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n;
+ litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n;
end
end
always @(*) begin
- litedramcore_master_p0_act_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n;
+ litedramcore_master_p3_cs_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n;
end else begin
- litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n;
+ litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n;
end
end
always @(*) begin
- litedramcore_master_p0_wrdata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata;
+ litedramcore_master_p3_ras_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n;
end else begin
- litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata;
+ litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n;
end
end
always @(*) begin
- litedramcore_inti_p1_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_slave_p3_rddata = 32'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata;
end else begin
- litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata;
end
end
always @(*) begin
- litedramcore_master_p0_wrdata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en;
+ litedramcore_master_p3_we_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n;
end else begin
- litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en;
+ litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n;
end
end
always @(*) begin
- litedramcore_inti_p1_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
+ litedramcore_slave_p3_rddata_valid = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
end else begin
- litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
end
end
always @(*) begin
- litedramcore_master_p0_wrdata_mask = 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask;
+ litedramcore_master_p3_cke = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_cke = litedramcore_slave_p3_cke;
end else begin
- litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask;
+ litedramcore_master_p3_cke = litedramcore_inti_p3_cke;
end
end
always @(*) begin
- litedramcore_master_p0_rddata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en;
+ litedramcore_master_p3_odt = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_odt = litedramcore_slave_p3_odt;
end else begin
- litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en;
+ litedramcore_master_p3_odt = litedramcore_inti_p3_odt;
end
end
always @(*) begin
- litedramcore_master_p1_address = 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_address = litedramcore_slave_p1_address;
+ litedramcore_master_p3_reset_n = 1'd0;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n;
end else begin
- litedramcore_master_p1_address = litedramcore_inti_p1_address;
+ litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n;
end
end
always @(*) begin
- litedramcore_master_p1_bank = 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_bank = litedramcore_slave_p1_bank;
+ litedramcore_master_p3_act_n = 1'd1;
+ if (litedramcore_sel) begin
+ litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n;
end else begin
- litedramcore_master_p1_bank = litedramcore_inti_p1_bank;
+ litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n;
end
end
+assign litedramcore_inti_p0_cke = litedramcore_cke;
+assign litedramcore_inti_p1_cke = litedramcore_cke;
+assign litedramcore_inti_p2_cke = litedramcore_cke;
+assign litedramcore_inti_p3_cke = litedramcore_cke;
+assign litedramcore_inti_p0_odt = litedramcore_odt;
+assign litedramcore_inti_p1_odt = litedramcore_odt;
+assign litedramcore_inti_p2_odt = litedramcore_odt;
+assign litedramcore_inti_p3_odt = litedramcore_odt;
+assign litedramcore_inti_p0_reset_n = litedramcore_reset_n;
+assign litedramcore_inti_p1_reset_n = litedramcore_reset_n;
+assign litedramcore_inti_p2_reset_n = litedramcore_reset_n;
+assign litedramcore_inti_p3_reset_n = litedramcore_reset_n;
always @(*) begin
- litedramcore_master_p1_cas_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n;
+ litedramcore_inti_p0_cas_n = 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]);
end else begin
- litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n;
+ litedramcore_inti_p0_cas_n = 1'd1;
end
end
-assign litedramcore_inti_p0_cke = litedramcore_storage[1];
-assign litedramcore_inti_p1_cke = litedramcore_storage[1];
-assign litedramcore_inti_p2_cke = litedramcore_storage[1];
-assign litedramcore_inti_p3_cke = litedramcore_storage[1];
-assign litedramcore_inti_p0_odt = litedramcore_storage[2];
-assign litedramcore_inti_p1_odt = litedramcore_storage[2];
-assign litedramcore_inti_p2_odt = litedramcore_storage[2];
-assign litedramcore_inti_p3_odt = litedramcore_storage[2];
-assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
always @(*) begin
litedramcore_inti_p0_cs_n = 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
litedramcore_inti_p0_we_n = 1'd1;
end
end
-always @(*) begin
- litedramcore_inti_p0_cas_n = 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]);
- end else begin
- litedramcore_inti_p0_cas_n = 1'd1;
- end
-end
assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_inti_p0_wrdata_mask = 1'd0;
+always @(*) begin
+ litedramcore_inti_p1_cas_n = 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]);
+ end else begin
+ litedramcore_inti_p1_cas_n = 1'd1;
+ end
+end
always @(*) begin
litedramcore_inti_p1_cs_n = 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
litedramcore_inti_p1_we_n = 1'd1;
end
end
-always @(*) begin
- litedramcore_inti_p1_cas_n = 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]);
- end else begin
- litedramcore_inti_p1_cas_n = 1'd1;
- end
-end
assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_inti_p1_wrdata_mask = 1'd0;
+always @(*) begin
+ litedramcore_inti_p2_cas_n = 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_inti_p2_cas_n = (~litedramcore_phaseinjector2_command_storage[2]);
+ end else begin
+ litedramcore_inti_p2_cas_n = 1'd1;
+ end
+end
always @(*) begin
litedramcore_inti_p2_cs_n = 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
litedramcore_inti_p2_we_n = 1'd1;
end
end
-always @(*) begin
- litedramcore_inti_p2_cas_n = 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cas_n = (~litedramcore_phaseinjector2_command_storage[2]);
- end else begin
- litedramcore_inti_p2_cas_n = 1'd1;
- end
-end
assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_inti_p2_wrdata_mask = 1'd0;
+always @(*) begin
+ litedramcore_inti_p3_cas_n = 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_inti_p3_cas_n = (~litedramcore_phaseinjector3_command_storage[2]);
+ end else begin
+ litedramcore_inti_p3_cas_n = 1'd1;
+ end
+end
always @(*) begin
litedramcore_inti_p3_cs_n = 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
litedramcore_inti_p3_we_n = 1'd1;
end
end
-always @(*) begin
- litedramcore_inti_p3_cas_n = 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cas_n = (~litedramcore_phaseinjector3_command_storage[2]);
- end else begin
- litedramcore_inti_p3_cas_n = 1'd1;
- end
-end
assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
end
endcase
end
+always @(*) begin
+ litedramcore_sequencer_start0 = 1'd0;
+ case (refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 = 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
always @(*) begin
litedramcore_cmd_valid = 1'd0;
case (refresher_state)
end
endcase
end
-always @(*) begin
- litedramcore_sequencer_start0 = 1'd0;
- case (refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 = 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
endcase
end
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine0_row_open = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+ litedramcore_bankmachine0_row_close = 1'd0;
+ case (bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close = 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close = 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close = 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write = 1'd1;
- end else begin
- end
+ litedramcore_bankmachine0_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine0_cmd_payload_we = 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we = 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we = 1'd1;
end else begin
- litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_refresh_gnt = 1'd0;
+ litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
+ litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_cmd_valid = 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid = 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid = 1'd1;
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read = 1'd1;
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine0_row_open = 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_row_close = 1'd0;
+ litedramcore_bankmachine0_req_wdata_ready = 1'd0;
case (bankmachine0_state)
1'd1: begin
- litedramcore_bankmachine0_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine0_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine0_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine0_req_rdata_valid = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready;
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine0_refresh_gnt = 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt = 1'd1;
+ end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine0_cmd_valid = 1'd0;
case (bankmachine0_state)
1'd1: begin
if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we = 1'd1;
+ litedramcore_bankmachine0_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid = 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we = 1'd1;
- end else begin
- end
+ litedramcore_bankmachine0_cmd_valid = 1'd1;
end else begin
end
end else begin
end
endcase
end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
- case (bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
endcase
end
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine1_row_open = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open = 1'd1;
end
end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
- case (bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
3'd4: begin
end
3'd5: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write = 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine1_row_close = 1'd0;
case (bankmachine1_state)
1'd1: begin
+ litedramcore_bankmachine1_row_close = 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine1_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine1_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready;
- end
+ litedramcore_bankmachine1_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine1_refresh_gnt = 1'd0;
+ litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine1_cmd_valid = 1'd0;
+ litedramcore_bankmachine1_cmd_payload_we = 1'd0;
case (bankmachine1_state)
1'd1: begin
if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid = 1'd1;
+ litedramcore_bankmachine1_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid = 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid = 1'd1;
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine1_row_open = 1'd0;
+ litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open = 1'd1;
+ litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
endcase
end
always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
+ litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine1_row_close = 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
case (bankmachine1_state)
1'd1: begin
- litedramcore_bankmachine1_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine1_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine1_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read = 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine1_req_wdata_ready = 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine1_req_rdata_valid = 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we = 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we = 1'd1;
end else begin
+ litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+ litedramcore_bankmachine1_refresh_gnt = 1'd0;
+ case (bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt = 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid = 1'd0;
case (bankmachine1_state)
1'd1: begin
if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine1_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine1_cmd_valid = 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine2_row_open = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+ litedramcore_bankmachine2_row_close = 1'd0;
case (bankmachine2_state)
1'd1: begin
+ litedramcore_bankmachine2_row_close = 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine2_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine2_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write = 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
+ litedramcore_bankmachine2_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_refresh_gnt = 1'd0;
+ litedramcore_bankmachine2_cmd_payload_we = 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_cmd_valid = 1'd0;
+ litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid = 1'd1;
+ litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid = 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_row_open = 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open = 1'd1;
+ litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_row_close = 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
case (bankmachine2_state)
1'd1: begin
- litedramcore_bankmachine2_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine2_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine2_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read = 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine2_req_wdata_ready = 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine2_req_rdata_valid = 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we = 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we = 1'd1;
end else begin
+ litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine2_refresh_gnt = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt = 1'd1;
+ end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+ litedramcore_bankmachine2_cmd_valid = 1'd0;
case (bankmachine2_state)
1'd1: begin
if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine2_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine2_cmd_valid = 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine3_row_open = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open = 1'd1;
end
end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
- case (bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
3'd4: begin
end
3'd5: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write = 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine3_row_close = 1'd0;
case (bankmachine3_state)
1'd1: begin
+ litedramcore_bankmachine3_row_close = 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine3_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine3_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready;
- end
+ litedramcore_bankmachine3_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
+ litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
endcase
end
always @(*) begin
- litedramcore_bankmachine3_refresh_gnt = 1'd0;
+ litedramcore_bankmachine3_cmd_payload_we = 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_cmd_valid = 1'd0;
+ litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid = 1'd1;
+ litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid = 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_row_open = 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open = 1'd1;
+ litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_row_close = 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
case (bankmachine3_state)
1'd1: begin
- litedramcore_bankmachine3_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine3_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine3_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read = 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine3_req_wdata_ready = 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine3_req_rdata_valid = 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we = 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we = 1'd1;
end else begin
+ litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+ litedramcore_bankmachine3_refresh_gnt = 1'd0;
+ case (bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt = 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid = 1'd0;
case (bankmachine3_state)
1'd1: begin
if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine3_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine3_cmd_valid = 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine4_row_open = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open = 1'd1;
end
end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
- case (bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
3'd4: begin
end
3'd5: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write = 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine4_row_close = 1'd0;
case (bankmachine4_state)
1'd1: begin
+ litedramcore_bankmachine4_row_close = 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine4_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine4_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready;
- end
+ litedramcore_bankmachine4_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine4_refresh_gnt = 1'd0;
+ litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_cmd_valid = 1'd0;
+ litedramcore_bankmachine4_cmd_payload_we = 1'd0;
case (bankmachine4_state)
1'd1: begin
if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid = 1'd1;
+ litedramcore_bankmachine4_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid = 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid = 1'd1;
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine4_row_open = 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open = 1'd1;
+ litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_row_close = 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
case (bankmachine4_state)
1'd1: begin
- litedramcore_bankmachine4_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine4_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine4_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read = 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine4_req_wdata_ready = 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine4_req_rdata_valid = 1'd0;
case (bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we = 1'd1;
- end
+ 1'd1: begin
end
2'd2: begin
end
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we = 1'd1;
end else begin
+ litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+ litedramcore_bankmachine4_refresh_gnt = 1'd0;
+ case (bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt = 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid = 1'd0;
case (bankmachine4_state)
1'd1: begin
if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine4_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine4_cmd_valid = 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine5_row_open = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open = 1'd1;
end
end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
- case (bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
3'd4: begin
end
3'd5: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write = 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine5_row_close = 1'd0;
case (bankmachine5_state)
1'd1: begin
+ litedramcore_bankmachine5_row_close = 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine5_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine5_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready;
- end
+ litedramcore_bankmachine5_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt = 1'd0;
+ litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_cmd_valid = 1'd0;
+ litedramcore_bankmachine5_cmd_payload_we = 1'd0;
case (bankmachine5_state)
1'd1: begin
if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid = 1'd1;
+ litedramcore_bankmachine5_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid = 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid = 1'd1;
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine5_row_open = 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open = 1'd1;
+ litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_row_close = 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
case (bankmachine5_state)
1'd1: begin
- litedramcore_bankmachine5_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine5_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine5_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read = 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine5_req_wdata_ready = 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine5_req_rdata_valid = 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we = 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we = 1'd1;
end else begin
+ litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+ litedramcore_bankmachine5_refresh_gnt = 1'd0;
+ case (bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt = 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid = 1'd0;
case (bankmachine5_state)
1'd1: begin
if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine5_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine5_cmd_valid = 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine6_row_open = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine6_row_close = 1'd0;
case (bankmachine6_state)
1'd1: begin
+ litedramcore_bankmachine6_row_close = 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine6_row_close = 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
- end
end
3'd4: begin
+ litedramcore_bankmachine6_row_close = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+ litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
- end else begin
- end
+ litedramcore_bankmachine6_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine6_cmd_payload_we = 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we = 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we = 1'd1;
end else begin
- litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_refresh_gnt = 1'd0;
+ litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_valid = 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
case (bankmachine6_state)
1'd1: begin
if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid = 1'd1;
+ litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid = 1'd1;
+ litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid = 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_row_open = 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read = 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_row_close = 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
case (bankmachine6_state)
1'd1: begin
- litedramcore_bankmachine6_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine6_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine6_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine6_req_wdata_ready = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine6_req_rdata_valid = 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine6_refresh_gnt = 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt = 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we = 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+ litedramcore_bankmachine6_cmd_valid = 1'd0;
case (bankmachine6_state)
1'd1: begin
if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine6_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
+ litedramcore_bankmachine6_cmd_valid = 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+ litedramcore_bankmachine7_row_open = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read = 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+ litedramcore_bankmachine7_row_close = 1'd0;
+ case (bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close = 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close = 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close = 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write = 1'd1;
- end else begin
- end
+ litedramcore_bankmachine7_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+ litedramcore_bankmachine7_cmd_payload_we = 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we = 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we = 1'd1;
end else begin
- litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready;
end
end else begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_refresh_gnt = 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt = 1'd1;
- end
+ litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_cmd_valid = 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid = 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid = 1'd1;
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read = 1'd1;
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine7_row_open = 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open = 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_row_close = 1'd0;
+ litedramcore_bankmachine7_req_wdata_ready = 1'd0;
case (bankmachine7_state)
1'd1: begin
- litedramcore_bankmachine7_row_close = 1'd1;
end
2'd2: begin
- litedramcore_bankmachine7_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine7_row_close = 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+ litedramcore_bankmachine7_req_rdata_valid = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas = 1'd1;
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready;
+ end
end else begin
end
end else begin
endcase
end
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+ litedramcore_bankmachine7_refresh_gnt = 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt = 1'd1;
+ end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+ litedramcore_bankmachine7_cmd_valid = 1'd0;
case (bankmachine7_state)
1'd1: begin
if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we = 1'd1;
+ litedramcore_bankmachine7_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid = 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we = 1'd1;
- end else begin
- end
+ litedramcore_bankmachine7_cmd_valid = 1'd1;
end else begin
end
end else begin
end
endcase
end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
- case (bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
endcase
end
always @(*) begin
- litedramcore_steerer_sel1 = 2'd0;
+ litedramcore_choose_req_cmd_ready = 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel1 = 1'd0;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
+ end
end
2'd2: begin
end
4'd11: begin
end
default: begin
- litedramcore_steerer_sel1 = 1'd1;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
+ end
end
endcase
end
always @(*) begin
- litedramcore_steerer_sel2 = 2'd0;
+ litedramcore_en1 = 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel2 = 1'd1;
+ litedramcore_en1 = 1'd1;
end
2'd2: begin
end
4'd11: begin
end
default: begin
- litedramcore_steerer_sel2 = 2'd2;
end
endcase
end
always @(*) begin
- litedramcore_choose_cmd_want_activates = 1'd0;
+ litedramcore_steerer_sel0 = 2'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
- end
+ litedramcore_steerer_sel0 = 1'd0;
end
2'd2: begin
+ litedramcore_steerer_sel0 = 2'd3;
end
2'd3: begin
end
4'd11: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
- end
+ litedramcore_steerer_sel0 = 1'd0;
end
endcase
end
always @(*) begin
- litedramcore_steerer_sel3 = 2'd0;
+ litedramcore_steerer_sel1 = 2'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel3 = 2'd2;
+ litedramcore_steerer_sel1 = 1'd0;
end
2'd2: begin
end
4'd11: begin
end
default: begin
- litedramcore_steerer_sel3 = 1'd0;
+ litedramcore_steerer_sel1 = 1'd1;
end
endcase
end
always @(*) begin
- litedramcore_en0 = 1'd0;
+ litedramcore_steerer_sel2 = 2'd0;
case (multiplexer_state)
1'd1: begin
+ litedramcore_steerer_sel2 = 1'd1;
end
2'd2: begin
end
4'd11: begin
end
default: begin
- litedramcore_en0 = 1'd1;
+ litedramcore_steerer_sel2 = 2'd2;
end
endcase
end
always @(*) begin
- litedramcore_cmd_ready = 1'd0;
+ litedramcore_choose_cmd_want_activates = 1'd0;
case (multiplexer_state)
1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
+ end
end
2'd2: begin
- litedramcore_cmd_ready = 1'd1;
end
2'd3: begin
end
4'd11: begin
end
default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
+ end
end
endcase
end
always @(*) begin
- litedramcore_choose_cmd_cmd_ready = 1'd0;
+ litedramcore_steerer_sel3 = 2'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
+ litedramcore_steerer_sel3 = 2'd2;
end
2'd2: begin
end
4'd11: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
+ litedramcore_steerer_sel3 = 1'd0;
end
endcase
end
always @(*) begin
- litedramcore_choose_req_want_reads = 1'd0;
+ litedramcore_en0 = 1'd0;
case (multiplexer_state)
1'd1: begin
end
4'd11: begin
end
default: begin
- litedramcore_choose_req_want_reads = 1'd1;
+ litedramcore_en0 = 1'd1;
end
endcase
end
always @(*) begin
- litedramcore_choose_req_want_writes = 1'd0;
+ litedramcore_cmd_ready = 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_choose_req_want_writes = 1'd1;
end
2'd2: begin
+ litedramcore_cmd_ready = 1'd1;
end
2'd3: begin
end
endcase
end
always @(*) begin
- litedramcore_choose_req_cmd_ready = 1'd0;
+ litedramcore_choose_cmd_cmd_ready = 1'd0;
case (multiplexer_state)
1'd1: begin
if (1'd0) begin
- litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
end else begin
- litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
+ litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
end
end
2'd2: begin
end
default: begin
if (1'd0) begin
- litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
end else begin
- litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
+ litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
end
end
endcase
end
always @(*) begin
- litedramcore_en1 = 1'd0;
+ litedramcore_choose_req_want_reads = 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_en1 = 1'd1;
end
2'd2: begin
end
4'd11: begin
end
default: begin
+ litedramcore_choose_req_want_reads = 1'd1;
end
endcase
end
always @(*) begin
- litedramcore_steerer_sel0 = 2'd0;
+ litedramcore_choose_req_want_writes = 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel0 = 1'd0;
+ litedramcore_choose_req_want_writes = 1'd1;
end
2'd2: begin
- litedramcore_steerer_sel0 = 2'd3;
end
2'd3: begin
end
4'd11: begin
end
default: begin
- litedramcore_steerer_sel0 = 1'd0;
end
endcase
end
assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24));
assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24));
+assign litedramcore_sel = litedramcore_storage[0];
+assign litedramcore_cke = litedramcore_storage[1];
+assign litedramcore_odt = litedramcore_storage[2];
+assign litedramcore_reset_n = litedramcore_storage[3];
assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
projects / microwatt.git / commitdiff