emit_simple_arith(p, inst, A0_ADD, 2, fs);
break;
+ case TGSI_OPCODE_CEIL:
+ src0 = src_vector(p, &inst->Src[0], fs);
+ tmp = i915_get_utemp(p);
+ flags = get_result_flags(inst);
+ i915_emit_arith(p,
+ A0_FLR,
+ tmp,
+ flags & A0_DEST_CHANNEL_ALL, 0,
+ negate(src0, 1, 1, 1, 1), 0, 0);
+ i915_emit_arith(p,
+ A0_MOV,
+ get_result_vector(p, &inst->Dst[0]),
+ flags, 0,
+ negate(tmp, 1, 1, 1, 1), 0, 0);
+ break;
+
case TGSI_OPCODE_CMP:
src0 = src_vector(p, &inst->Src[0], fs);
src1 = src_vector(p, &inst->Src[1], fs);
case TGSI_OPCODE_ADD:
nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
break;
+ case TGSI_OPCODE_CEIL:
+ tmp = nvfx_src(temp(fpc));
+ nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, neg(src[0]), none, none));
+ nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, neg(tmp), none, none));
+ break;
case TGSI_OPCODE_CMP:
insn = arith(0, MOV, none.reg, mask, src[0], none, none);
insn.cc_update = 1;
case TGSI_OPCODE_ARL:
nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none));
break;
+ case TGSI_OPCODE_CEIL:
+ tmp = nvfx_src(temp(vpc));
+ nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, neg(src[0]), none, none));
+ nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none));
+ break;
case TGSI_OPCODE_CMP:
insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none);
insn.cc_update = 1;
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE: