i386.c (expand_vec_perm_1): Fix expand_vec_perm_palignr case.

	* config/i386/i386.c (expand_vec_perm_1): Fix
	expand_vec_perm_palignr case.
	* config/i386/sse.md (<ssse3_avx2>_palignr<mode>_mask): Use
	VI1_AVX512.

From-SVN: r216504

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f7dedb56edfd518bf2d1950ea066e1256bf9a77d..87a4102038d0a3b5c3dd36393b3ac4e54ebd7d7c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2014-10-21  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/i386/i386.c (expand_vec_perm_1): Fix
+       expand_vec_perm_palignr case.
+       * config/i386/sse.md (<ssse3_avx2>_palignr<mode>_mask): Use
+       VI1_AVX512.
+
 2014-10-21  Zhenqiang Chen  <zhenqiang.chen@arm.com>
 
        * cfgloopanal.c (seq_cost): Delete.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 33b21f442e8e63d881adb4067f2420b87f310ccb..34273ca12de0fd4deb77c1a43791679ed333b5ec 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -43552,6 +43552,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
 
   /* Try the AVX2 vpalignr instruction.  */
   if (expand_vec_perm_palignr (d, true))
+    return true;
 
   /* Try the AVX512F vpermi2 instructions.  */
   if (ix86_expand_vec_perm_vpermi2 (NULL_RTX, NULL_RTX, NULL_RTX, NULL_RTX, d))

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 81570459eb7a3d619b8873533fc6dad2617a9dde..a3f336fa15f2778e17f6eabfefe5a7ba39fce41d 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13716,14 +13716,14 @@
    (set_attr "mode" "DI")])
 
 (define_insn "<ssse3_avx2>_palignr<mode>_mask"
-  [(set (match_operand:VI1_AVX2 0 "register_operand" "=v")
-        (vec_merge:VI1_AVX2
-         (unspec:VI1_AVX2
-           [(match_operand:VI1_AVX2 1 "register_operand" "v")
-            (match_operand:VI1_AVX2 2 "nonimmediate_operand" "vm")
+  [(set (match_operand:VI1_AVX512 0 "register_operand" "=v")
+        (vec_merge:VI1_AVX512
+         (unspec:VI1_AVX512
+           [(match_operand:VI1_AVX512 1 "register_operand" "v")
+            (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm")
             (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
            UNSPEC_PALIGNR)
-       (match_operand:VI1_AVX2 4 "vector_move_operand" "0C")
+       (match_operand:VI1_AVX512 4 "vector_move_operand" "0C")
        (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)"
 {