etherbone_magic = 0x4e6f
etherbone_version = 1
etherbone_header_len = 8
-etherbone_header = [
+etherbone_header = {
"magic": HField( 0, 0, 16),
"portsize": HField( 2, 0, 4),
"addrsize": HField( 2, 4, 4),
"rcount": HField( 6, 0, 8),
"wcount": HField( 7, 0, 8)
-]
+}
+
def reverse_bytes(v):
n = math.ceil(flen(v)/8)
self.source = source = Source(source_description)
self.header = Signal(header_length*8)
###
+ dw = flen(sink.data)
+
shift = Signal()
- counter = Counter(max=header_length)
+ counter = Counter(max=header_length//(dw//8))
self.submodules += counter
self.sync += \
If(shift,
- self.header.eq(Cat(self.header[8:], sink.data))
+ self.header.eq(Cat(self.header[dw:], sink.data))
)
fsm = FSM(reset_state="IDLE")
If(sink.stb,
counter.ce.eq(1),
shift.eq(1),
- If(counter.value == header_length-2,
+ If(counter.value == header_length//(dw//8)-2,
NextState("COPY")
)
)
self.source = source = Source(source_description)
self.header = Signal(header_length*8)
###
+ dw = flen(self.sink.data)
+
header_reg = Signal(header_length*8)
load = Signal()
shift = Signal()
- counter = Counter(max=header_length)
+ counter = Counter(max=header_length//(dw//8))
self.submodules += counter
self.comb += _encode_header(header_type, self.header, sink)
If(load,
header_reg.eq(self.header)
).Elif(shift,
- header_reg.eq(Cat(header_reg[8:], Signal(8)))
+ header_reg.eq(Cat(header_reg[dw:], Signal(dw)))
)
]
source.stb.eq(1),
source.sop.eq(1),
source.eop.eq(0),
- source.data.eq(self.header[:8]),
+ source.data.eq(self.header[:dw]),
If(source.stb & source.ack,
load.eq(1),
NextState("SEND_HEADER"),
fsm.act("SEND_HEADER",
source.stb.eq(1),
source.sop.eq(0),
- source.eop.eq(sink.eop & (counter.value == header_length-2)),
- source.data.eq(header_reg[8:16]),
+ source.eop.eq(sink.eop & (counter.value == header_length//(dw//8)-2)),
+ source.data.eq(header_reg[dw:2*dw]),
If(source.stb & source.ack,
shift.eq(1),
counter.ce.eq(1),
- If(counter.value == header_length-2,
+ If(counter.value == header_length//(dw//8)-2,
NextState("COPY")
)
)