read/write seems OK with CommandGenerator

diff --git a/targets/test.py b/targets/test.py
index e32de9033aec9b1a2d9a5ede53e86a302818c5b6..8c7798ff7e0bb9cf8d601502885e85b7cc136303 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -215,6 +215,13 @@ class CommandGenerator(Module, AutoCSR):
                                NextState("WAIT_WRITE_ACK")
                        )
                )
+               self.sync += [
+                       If(fsm.ongoing("IDLE"),
+                               cnt.eq(0)
+                       ).Elif(sata_con.sink.stb & sata_con.sink.stb,
+                               cnt.eq(cnt+1)
+                       )
+               ]
                fsm.act("WAIT_WRITE_ACK",
                        # XXX: add check of success / failed
                        If(sata_con.source.stb & sata_con.source.eop,
@@ -312,16 +319,16 @@ class TestDesign(UART2WB, AutoCSR):
                        self.sata_con.sink.read,
                        self.sata_con.sink.identify,
 
-                       #self.sata_con.source.stb,
-                       #self.sata_con.source.sop,
-                       #self.sata_con.source.eop,
-                       #self.sata_con.source.ack,
-                       #self.sata_con.source.write,
-                       #self.sata_con.source.read,
-                       #self.sata_con.source.identify,
-                       #self.sata_con.source.success,
-                       #self.sata_con.source.failed,
-                       #self.sata_con.source.data,
+                       self.sata_con.source.stb,
+                       self.sata_con.source.sop,
+                       self.sata_con.source.eop,
+                       self.sata_con.source.ack,
+                       self.sata_con.source.write,
+                       self.sata_con.source.read,
+                       self.sata_con.source.identify,
+                       self.sata_con.source.success,
+                       self.sata_con.source.failed,
+                       self.sata_con.source.data,
 
                        #self.sata_con.link.source.stb,
                        #self.sata_con.link.source.sop,
@@ -337,19 +344,19 @@ class TestDesign(UART2WB, AutoCSR):
                        #self.sata_con.link.rx.scrambler.sink.d,
                        #self.sata_con.link.rx.scrambler.sink.error,
 
-                       self.sata_con.link.rx.scrambler.sink.stb,
-                       self.sata_con.link.rx.scrambler.sink.sop,
-                       self.sata_con.link.rx.scrambler.sink.eop,
-                       self.sata_con.link.rx.scrambler.sink.ack,
-                       self.sata_con.link.rx.scrambler.sink.d,
-                       self.sata_con.link.rx.scrambler.sink.error,
-
-                       self.sata_con.link.rx.scrambler.source.stb,
-                       self.sata_con.link.rx.scrambler.source.sop,
-                       self.sata_con.link.rx.scrambler.source.eop,
-                       self.sata_con.link.rx.scrambler.source.ack,
-                       self.sata_con.link.rx.scrambler.source.d,
-                       self.sata_con.link.rx.scrambler.source.error,
+                       #self.sata_con.link.rx.crc.sink.stb,
+                       #self.sata_con.link.rx.crc.sink.sop,
+                       #self.sata_con.link.rx.crc.sink.eop,
+                       #self.sata_con.link.rx.crc.sink.ack,
+                       #self.sata_con.link.rx.crc.sink.d,
+                       #self.sata_con.link.rx.crc.sink.error,
+
+                       self.sata_con.link.rx.crc.source.stb,
+                       self.sata_con.link.rx.crc.source.sop,
+                       self.sata_con.link.rx.crc.source.eop,
+                       self.sata_con.link.rx.crc.source.ack,
+                       self.sata_con.link.rx.crc.source.d,
+                       self.sata_con.link.rx.crc.source.error,
 
                        self.command_tx_fsm_state,
                        self.transport_tx_fsm_state,

diff --git a/test/test_identify.py b/test/test_identify.py
index 24f1a4de4c5ae4dc1f61800c87d5e184a2a35957..3fcba0b36aaaba951c84c9ba1a2bb09c5ba15c92 100644 (file)
--- a/test/test_identify.py
+++ b/test/test_identify.py
@@ -8,16 +8,19 @@ wb.open()
 regs = wb.regs
 ###
 
-#trigger0 = mila.sata_con_sink_payload_identify_o*1
-#mask0 = mila.sata_con_sink_payload_identify_m
+cond = {
+       #"sata_phy_source_source_payload_data"          : primitives["R_RDY"],
+       #"sata_phy_source_source_payload_data"          : primitives["R_OK"],
+       "sata_phy_source_source_payload_data"           : primitives["X_RDY"],
+}
 
-#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
-#mask0 = mila.sata_phy_source_source_payload_data_m
+trigger = 0
+mask = 0
+for k, v in cond.items():
+       trigger |= getattr(mila, k+"_o")*v
+       mask |= getattr(mila, k+"_m")
 
-trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"]
-mask0 = mila.sata_phy_source_source_payload_data_m
-
-mila.prog_term(port=0, trigger=trigger0, mask=mask0)
+mila.prog_term(port=0, trigger=trigger, mask=mask)
 mila.prog_sum("term")
 
 # Trigger / wait / receive

diff --git a/test/test_read.py b/test/test_read.py
index 155c5487ddbda2030ee200362c47eefe2e3a2be1..632469ee69a989a11dc9ec661774238338e14bd5 100644 (file)
--- a/test/test_read.py
+++ b/test/test_read.py
@@ -8,16 +8,20 @@ wb.open()
 regs = wb.regs
 ###
 
-#trigger0 = mila.sata_con_sink_payload_read_o*1
-#mask0 = mila.sata_con_sink_payload_read_m
+cond = {
+       #"sata_phy_source_source_payload_data"          : primitives["R_RDY"],
+       #"sata_phy_source_source_payload_data"          : primitives["R_OK"],
+       #"sata_phy_source_source_payload_data"          : primitives["X_RDY"],
+       "sata_con_source_source_stb"                            : 1,
+}
 
-#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
-#mask0 = mila.sata_phy_source_source_payload_data_m
+trigger = 0
+mask = 0
+for k, v in cond.items():
+       trigger |= getattr(mila, k+"_o")*v
+       mask |= getattr(mila, k+"_m")
 
-trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"]
-mask0 = mila.sata_phy_source_source_payload_data_m
-
-mila.prog_term(port=0, trigger=trigger0, mask=mask0)
+mila.prog_term(port=0, trigger=trigger, mask=mask)
 mila.prog_sum("term")
 
 # Trigger / wait / receive

diff --git a/test/test_write.py b/test/test_write.py
index 8c760d51857274f32c89e683d7442603c12a19a9..ccc3e354ba891fa1c1529d9f3a87c7b47ad39662 100644 (file)
--- a/test/test_write.py
+++ b/test/test_write.py
@@ -8,16 +8,20 @@ wb.open()
 regs = wb.regs
 ###
 
-#trigger0 = mila.sata_con_sink_payload_write_o*1
-#mask0 = mila.sata_con_sink_payload_write_m
+cond = {
+       #"sata_phy_source_source_payload_data"          : primitives["R_RDY"],
+       #"sata_phy_source_source_payload_data"          : primitives["R_OK"],
+       #"sata_phy_source_source_payload_data"          : primitives["X_RDY"],
+       "sata_con_source_source_stb"                            : 1,
+}
 
-#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_RDY"]
-#mask0 = mila.sata_phy_source_source_payload_data_m
+trigger = 0
+mask = 0
+for k, v in cond.items():
+       trigger |= getattr(mila, k+"_o")*v
+       mask |= getattr(mila, k+"_m")
 
-trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
-mask0 = mila.sata_phy_source_source_payload_data_m
-
-mila.prog_term(port=0, trigger=trigger0, mask=mask0)
+mila.prog_term(port=0, trigger=trigger, mask=mask)
 mila.prog_sum("term")
 
 # Trigger / wait / receive