sequential buckets, and warn if the user does so.
+2000-06-27 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (write_2_short): Do not allow opcodes with
+ the EITHER_BUT_PREFER_MU attribute to be combined into a reverse
+ sequential order, and emit warning messages if the input source
+ code contains constructs like that, or parallel constructs
+ containing such opcodes.
+
2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl>
* config/tc-avr.c (mcu_types): Rename avr4 to avr5, add avr4.
write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
- else if (opcode1->op->unit == IU
- || (opcode1->op->unit == EITHER
- && opcode2->op->unit == EITHER_BUT_PREFER_MU))
+ else if (opcode1->op->unit == IU)
{
+ if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
+ {
+ /* Case 103810 is a request from Mitsubishi that opcodes
+ with EITHER_BUT_PREFER_MU should not be executed in
+ reverse sequential order. */
+ write_1_short (opcode1, insn1, fx->next, false);
+ return 1;
+ }
+
/* reverse sequential */
insn = FM10 | (insn2 << 32) | insn1;
exec_type = EXEC_REVSEQ;
else
{
if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
- as_warn (_("Executing %s in IU may not work"), opcode2->op->name);
+ as_warn (_("Executing %s in IU in parallel with %s may not work"),
+ opcode1->op->name, opcode2->op->name);
insn = FM00 | (insn1 << 32) | insn2;
fx = fx->next;
as_bad (_("special left instruction `%s' kills instruction "
"`%s' in right container"),
opcode1->op->name, opcode2->op->name);
- if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
- as_warn (_("Executing %s in IU may not work"), opcode2->op->name);
insn = FM01 | (insn1 << 32) | insn2;
fx = fx->next;
break;
case EXEC_REVSEQ: /* reverse sequential */
if (opcode2->op->unit == MU)
as_bad (_("MU instruction may not be in the right container"));
- if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
- as_warn (_("Executing %s in IU may not work"), opcode2->op->name);
+ if (opcode1->op->unit == EITHER_BUT_PREFER_MU
+ || opcode2->op->unit == EITHER_BUT_PREFER_MU)
+ as_warn (_("Executing %s in reverse serial with %s may not work"),
+ opcode1->op->name, opcode2->op->name);
insn = FM10 | (insn1 << 32) | insn2;
fx = fx->next;
break;
+2000-06-27 Nick Clifton <nickc@cygnus.com>
+
+ * gas/d30v/bittest.l: Edit to match new warning messages produced
+ by assembler.
+
2000-06-19 Timothy Wall <twall@cygnus.com>
* gas/macros/macros.exp: Avoid tests which are not useful on tic54x.
.*: Assembler messages:
.*: Warning: Swapping instruction order
-.*: Warning: Executing bset in IU may not work
-.*: Warning: Executing btst in IU may not work
-.*: Warning: Executing bclr in IU may not work
-.*: Warning: Executing bnot in IU may not work
+.*: Warning: Executing nop in reverse serial with btst may not work
+.*: Warning: Executing nop in IU in parallel with bclr may not work
.*: Warning: Executing bset in IU may not work
.*: Warning: Swapping instruction order
GAS LISTING .*
11 00F00000
12
13 0010 00F00000 nop -> BSET R1, R2, R3
-.* Warning:Executing bset in IU may not work
13 82201083
14 0018 80F00000 nop <- BTST F1, R2, R3
-.* Warning:Executing btst in IU may not work
+.* Warning:Executing nop in reverse serial with btst may not work
14 02001083
15 0020 00F00000 nop || BCLR R1, R2, R3
-.* Warning:Executing bclr in IU may not work
+.* Warning:Executing nop in IU in parallel with bclr may not work
15 02301083
16 0028 00F00000 nop -> BNOT R1, R2, R3
-.* Warning:Executing bnot in IU may not work
16 82101083
17 0030 02101083 BNOT r1, r2, r3 -> nop
17 80F00000
25 88C04146
26
27 joinll r4, r5, r6
- 28 0050 82201083 bset r1, r2, r3
- 28 08C04146
+ 28 0050 08C04146 bset r1, r2, r3
+ 28 82201083