Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index fe83a8e38156aad9693617ccbaffbcfd3bb84371..65f28c585e126bac8c38a6c5660391e090a874ee 100644 (file)
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,7 +44,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
        genvar i;
        generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-`ifdef _ABC
                \$__ICE40_FULL_ADDER carry (
                        .A(AA[i]),
                        .B(BB[i]),
@@ -52,27 +51,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
                        .CO(CO[i]),
                        .O(Y[i])
                );
-`else
-               SB_CARRY carry (
-                       .I0(AA[i]),
-                       .I1(BB[i]),
-                       .CI(C[i]),
-                       .CO(CO[i])
-               );
-               SB_LUT4 #(
-                       //         I0: 1010 1010 1010 1010
-                       //         I1: 1100 1100 1100 1100
-                       //         I2: 1111 0000 1111 0000
-                       //         I3: 1111 1111 0000 0000
-                       .LUT_INIT(16'b 0110_1001_1001_0110)
-               ) adder (
-                       .I0(1'b0),
-                       .I1(AA[i]),
-                       .I2(BB[i]),
-                       .I3(C[i]),
-                       .O(Y[i])
-               );
-`endif
        end endgenerate
 
        assign X = AA ^ BB;

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index b4b8311650e156a759cebc5c050fcfe9c4a27666..511b7f6c6d62461fc62bd5f4820a5b91d6756fc0 100644 (file)
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -62,7 +62,7 @@ module \$lut (A, Y);
 endmodule
 `endif
 
-`ifdef _ABC
+`ifndef NO_ADDER
 module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
@@ -70,18 +70,16 @@ module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
     .CI(CI),
     .CO(CO)
   );
-  SB_LUT4 #(
-    //         I0: 1010 1010 1010 1010
-    //         I1: 1100 1100 1100 1100
-    //         I2: 1111 0000 1111 0000
-    //         I3: 1111 1111 0000 0000
-    .LUT_INIT(16'b 0110_1001_1001_0110)
+  \$lut #(
+    .WIDTH(4),
+    //    A[0]: 1010 1010 1010 1010
+    //    A[1]: 1100 1100 1100 1100
+    //    A[2]: 1111 0000 1111 0000
+    //    A[3]: 1111 1111 0000 0000
+    .LUT(16'b 0110_1001_1001_0110)
   ) adder (
-    .I0(1'b0),
-    .I1(A),
-    .I2(B),
-    .I3(CI),
-    .O(O)
+    .A({CI,B,A,1'b0}),
+    .Y(O)
   );
 endmodule
 `endif

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index be60a007114f7686ce708e8efecce2ff176e472a..93d5dcbd418eed35a914b5eaa964e6cf7412d6ac 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
        {
                if (check_label("begin"))
                {
-                       run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
+                       run("read_verilog -icells -lib +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }
@@ -294,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass
                        if (nocarry)
                                run("techmap");
                        else
-                               run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
+                               run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
                        if (retime || help_mode)
                                run(abc + " -dff", "(only if -retime)");
                        run("ice40_opt");
@@ -309,7 +309,7 @@ struct SynthIce40Pass : public ScriptPass
                                run("opt_merge");
                                run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
                        }
-                       run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+                       run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
                        run("opt_expr -mux_undef");
                        run("simplemap");
                        run("ice40_ffinit");
@@ -338,13 +338,12 @@ struct SynthIce40Pass : public ScriptPass
                                        else
                                                wire_delay = 250;
                                        run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
-                                       run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
                                }
                                else
                                        run(abc + " -dress -lut 4", "(skip if -noabc)");
                        }
+                       run("techmap -D NO_LUT -map +/ice40/cells_map.v");
                        run("clean");
-                       run("ice40_unlut");
                        run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
                }