i965/blorp: Add support for source swizzle

In order to support cases where gen9 uses RGBA format to back client
requested RGB, one needs to have means to force alpha channel to one
when user requested RGB surface is used as blit source.

v2 (Ken): Use helper for constructing the swizzle (this should be
          changed to use brw_get_texture_swizzle() as a follow-up).
          Also calculate the swizzle for CopyTexSubImage.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 38a32361f0be3aa36eb4f105b19303e1ab9c6391..04a019e07178bf46da0e763fb75ffdc00370ea7f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -43,7 +43,8 @@ brw_blorp_mip_info::brw_blorp_mip_info()
 
 brw_blorp_surface_info::brw_blorp_surface_info()
    : map_stencil_as_y_tiled(false),
-     num_samples(0)
+     num_samples(0),
+     swizzle(SWIZZLE_XYZW)
 {
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 8e307708bfb5e777467fad299fd61324ee24bec6..7ebcee27455cec64e02996d9217397f859b0a5ec 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -38,7 +38,7 @@ void
 brw_blorp_blit_miptrees(struct brw_context *brw,
                         struct intel_mipmap_tree *src_mt,
                         unsigned src_level, unsigned src_layer,
-                        mesa_format src_format,
+                        mesa_format src_format, int src_swizzle,
                         struct intel_mipmap_tree *dst_mt,
                         unsigned dst_level, unsigned dst_layer,
                         mesa_format dst_format,
@@ -164,6 +164,14 @@ public:
     * surface state for this surface.
     */
    intel_msaa_layout msaa_layout;
+
+   /**
+    * In order to support cases where RGBA format is backing client requested
+    * RGB, one needs to have means to force alpha channel to one when user
+    * requested RGB surface is used as blit source. This is possible by
+    * setting source swizzle for the texture surface.
+    */
+   int swizzle;
 };
 
 

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 52433418a9a172af85cb6e8a82169d3f24482ab0..369e0f56a59686d52a0b44b95d0aa8e1fda9a23c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -56,7 +56,7 @@ void
 brw_blorp_blit_miptrees(struct brw_context *brw,
                         struct intel_mipmap_tree *src_mt,
                         unsigned src_level, unsigned src_layer,
-                        mesa_format src_format,
+                        mesa_format src_format, int src_swizzle,
                         struct intel_mipmap_tree *dst_mt,
                         unsigned dst_level, unsigned dst_layer,
                         mesa_format dst_format,
@@ -105,11 +105,21 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
                                 dst_x0, dst_y0,
                                 dst_x1, dst_y1,
                                 filter, mirror_x, mirror_y);
+   params.src.swizzle = src_swizzle;
+
    brw_blorp_exec(brw, &params);
 
    intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
 }
 
+static int
+blorp_get_texture_swizzle(const struct intel_renderbuffer *irb)
+{
+   return irb->Base.Base._BaseFormat == GL_RGB ?
+      MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
+      SWIZZLE_XYZW;
+}
+
 static void
 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
               struct intel_renderbuffer *src_irb, mesa_format src_format,
@@ -123,11 +133,10 @@ do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
    struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
 
    const bool es3 = _mesa_is_gles3(&brw->ctx);
-
    /* Do the blit */
    brw_blorp_blit_miptrees(brw,
                            src_mt, src_irb->mt_level, src_irb->mt_layer,
-                           src_format,
+                           src_format, blorp_get_texture_swizzle(src_irb),
                            dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
                            dst_format,
                            srcX0, srcY0, srcX1, srcY1,
@@ -295,7 +304,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
 
    brw_blorp_blit_miptrees(brw,
                            src_mt, src_irb->mt_level, src_irb->mt_layer,
-                           src_rb->Format,
+                           src_rb->Format, blorp_get_texture_swizzle(src_irb),
                            dst_mt, dst_level, dst_slice,
                            dst_image->TexFormat,
                            srcX0, srcY0, srcX1, srcY1,
@@ -322,6 +331,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
          brw_blorp_blit_miptrees(brw,
                                  src_mt, src_irb->mt_level, src_irb->mt_layer,
                                  src_mt->format,
+                                 blorp_get_texture_swizzle(src_irb),
                                  dst_mt, dst_level, dst_slice,
                                  dst_mt->format,
                                  srcX0, srcY0, srcX1, srcY1,

diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.cpp b/src/mesa/drivers/dri/i965/gen8_blorp.cpp
index 503974a53accdd309bb461c4d3aad9403ced2336..1d3a62b5a4d0dc03a3602c95eaea1b6a354a9a04 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.cpp
@@ -598,7 +598,7 @@ gen8_blorp_emit_surface_states(struct brw_context *brw,
                                            layer, layer + depth,
                                            surface->level, max_level,
                                            surface->brw_surfaceformat,
-                                           SWIZZLE_XYZW,
+                                           surface->swizzle,
                                            &wm_surf_offset_texture,
                                            -1, false, false);
    }

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d263ff896e86ab6628198fa746b1ff6ebf121be4..f60e1c368f50a6da5c00f352c152d04bdbb1793a 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2166,7 +2166,8 @@ intel_miptree_updownsample(struct brw_context *brw,
 {
    if (brw->gen < 8) {
       brw_blorp_blit_miptrees(brw,
-                              src, 0 /* level */, 0 /* layer */, src->format,
+                              src, 0 /* level */, 0 /* layer */,
+                              src->format, SWIZZLE_XYZW,
                               dst, 0 /* level */, 0 /* layer */, dst->format,
                               0, 0,
                               src->logical_width0, src->logical_height0,
@@ -2188,7 +2189,7 @@ intel_miptree_updownsample(struct brw_context *brw,
 
       brw_blorp_blit_miptrees(brw,
                               src->stencil_mt, 0 /* level */, 0 /* layer */,
-                              src->stencil_mt->format,
+                              src->stencil_mt->format, SWIZZLE_XYZW,
                               dst->stencil_mt, 0 /* level */, 0 /* layer */,
                               dst->stencil_mt->format,
                               0, 0,