mr max, cost+5
setvl 0,0,8,0,1,1 # Set VL to 8 elements
- #sv.maxs/mr max, max, *cost
+ #sv.minmax/mr max, max, *cost, 3 # MMM=maxs
sv.cmp 0, 0, *cost, max
svstep retval, 5, 1
# sv.addi/m=eq retval,*,0
<!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
<!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
-# DRAFT Fixed Point Signed Max (Rc=1)
+# DRAFT Minimum/Maximum (Rc=1)
-X-Form
+MM-Form
-* maxs. RT,RA,RB (Rc=1)
+* minmax. RT,RA,RB,MMM (Rc=1)
Pseudo-code:
- a <- (RA)
+ a <- (RA|0)
b <- (RB)
- if a > b then RT <- a
- else RT <- b
- if a < b then c <- 0b100
- else if a > b then c <- 0b010
- else c <- 0b001
- CR0 <- c || XER[SO]
+ if MMM[0] then # word mode
+ # shift left by XLEN/2 to make the dword comparison
+ # do word comparison of the original inputs
+ a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
+ b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
+ if MMM[1] then # signed mode
+ # invert sign bits to make the unsigned comparison
+ # do signed comparison of the original inputs
+ a[0] <- ¬a[0]
+ b[0] <- ¬b[0]
+ # if Rc = 1 then store the result of comparing a and b to CR0
+ if Rc = 1 then
+ if a <u b then
+ CR0 <- 0b100 || XER[SO]
+ if a = b then
+ CR0 <- 0b001 || XER[SO]
+ if a >u b then
+ CR0 <- 0b010 || XER[SO]
+ if MMM[2] then # max mode
+ # swap a and b to make the less than comparison do
+ # greater than comparison of the original inputs
+ t <- a
+ a <- b
+ b <- t
+ # store the entire selected source (even in word mode)
+ # if Rc = 1 then store the result of comparing a and b to CR0
+ if a <u b then RT <- (RA|0)
+ else RT <- (RB)
Special Registers Altered:
CR0 (if Rc=1)
-# DRAFT Fixed Point Signed Max
+# DRAFT Minimum/Maximum
-X-Form
+MM-Form
-* maxs RT,RA,RB (Rc=0)
+* minmax RT,RA,RB,MMM (Rc=0)
Pseudo-code:
- if (RA) > (RB) then RT <- (RA)
- else RT <- (RB)
+ a <- (RA|0)
+ b <- (RB)
+ if MMM[0] then # word mode
+ # shift left by XLEN/2 to make the dword comparison
+ # do word comparison of the original inputs
+ a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
+ b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
+ if MMM[1] then # signed mode
+ # invert sign bits to make the unsigned comparison
+ # do signed comparison of the original inputs
+ a[0] <- ¬a[0]
+ b[0] <- ¬b[0]
+ # if Rc = 1 then store the result of comparing a and b to CR0
+ # if Rc = 1 then
+ # if a <u b then
+ # CR0 <- 0b100 || XER[SO]
+ # if a = b then
+ # CR0 <- 0b001 || XER[SO]
+ # if a >u b then
+ # CR0 <- 0b010 || XER[SO]
+ if MMM[2] then # max mode
+ # swap a and b to make the less than comparison do
+ # greater than comparison of the original inputs
+ t <- a
+ a <- b
+ b <- t
+ # store the entire selected source (even in word mode)
+ # if Rc = 1 then store the result of comparing a and b to CR0
+ if a <u b then RT <- (RA|0)
+ else RT <- (RB)
Special Registers Altered:
None
-# DRAFT Fixed Point Unsigned Max
-
-X-Form
-
-* maxu RT,RA,RB (Rc=0)
-* maxu. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- if (RA) >u (RB) then RT <- (RA)
- else RT <- (RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# DRAFT Fixed Point Signed Min
-
-X-Form
-
-* mins RT,RA,RB (Rc=0)
-* mins. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- if (RA) < (RB) then RT <- (RA)
- else RT <- (RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# DRAFT Fixed Point Unsigned Min
-
-X-Form
-
-* minu RT,RA,RB (Rc=0)
-* minu. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- if (RA) <u (RB) then RT <- (RA)
- else RT <- (RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
# DRAFT Average Add
X-Form
26/6=fmrgow,NORMAL,,1P,EXTRA3,NO,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
30/6=fmrgew,NORMAL,,1P,EXTRA3,NO,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
rlwnm,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+minmax,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
shadd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
shaddw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
shadduw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-minu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-maxu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mins,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
cprop,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-maxs,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
absds,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
absdu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
avgadd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
0000010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,rfid,XL,,,
0100010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,hrfid,XL,,,
-----00010,ALU,OP_ADD,CIA,CONST_DXHI4,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,addpcis,DX,,,
+----000011,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,minmax,MM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
# svshape2: {-100,mm,011001}
100--011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape2,SVM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
# A/V bitmanip
-0111001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,maxs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0011001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,maxu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0101001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,mins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
--01101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shadd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
--10101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shaddw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
dotstrp = asmop[:-1] if asmop[-1] == '.' else asmop
if dotstrp in [*FPTRANS_INSNS,
'ffmadds', 'fdmadds', 'ffadds',
- 'mins', 'maxs', 'minu', 'maxu',
+ 'minmax',
'setvl', 'svindex', 'svremap', 'svstep',
'svshape', 'svshape2',
'grev', 'ternlogi', 'bmask', 'cprop',
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
- "mins", "maxs", "minu", "maxu", # AV bitmanip
+ "minmax", # AV bitmanip
"modsd", "modsw", "modud", "moduw",
"mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
"mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
'sv.svstep. 2.v, 4, 0',
]
lst = [
- 'maxs 3,12,5',
- 'maxs. 3,12,5',
+ 'minmax 3,12,5,3',
+ 'minmax. 3,12,5,4',
'avgadd 3,12,5',
'absdu 3,12,5',
'absds 3,12,5',
add_arg = 0x80 - compare_rhs
return [
f"addi {temp_s}, 0, {max_arg}",
- f"sv.maxu *{out_v}, *{inp_v}, {temp_s}",
+ f"sv.minmax *{out_v}, *{inp_v}, {temp_s}, 1",
f"sv.addi *{out_v}, *{out_v}, {add_arg}"
]
return [
class AVTestCase(TestAccumulatorBase):
def case_0_maxs(self):
- lst = ["maxs 3, 1, 2"]
+ lst = ["minmax 3, 1, 2, 3"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_1_maxs(self):
- lst = ["maxs 3, 1, 2"]
+ lst = ["minmax 3, 1, 2, 3"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_2_maxs_(self):
- lst = [f"maxs. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 3"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_3_maxs_(self):
- lst = [f"maxs. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 3"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_4_maxs_(self):
- lst = [f"maxs. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 3"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
def case_5_maxs_(self):
"""max negative number compared against +ve number
"""
- lst = [f"maxs. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 3"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_6_maxs_(self):
- lst = [f"maxs. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 3"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_0_mins(self):
- lst = ["mins 3, 1, 2"]
+ lst = ["minmax 3, 1, 2, 2"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_2_mins_(self):
- lst = [f"mins. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 2"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
def case_5_mins_(self):
"""min negative number compared against +ve number
"""
- lst = [f"mins. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 2"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
e.intregs[1] = 1
e.intregs[2] = 0x8000_0000_0000_0000
e.intregs[3] = 0x8000_0000_0000_0000
- e.crregs[0] = 0x8 # RT is -ve
+ e.crregs[0] = 0x4 # r1 >s r2
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_0_maxu(self):
- lst = ["maxu 3, 1, 2"]
+ lst = ["minmax 3, 1, 2, 1"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
def case_5_minu_(self):
"""min +ve numbers
"""
- lst = [f"minu. 3, 1, 2"]
+ lst = [f"minmax. 3, 1, 2, 0"]
lst = list(SVP64Asm(lst, bigendian))
initial_regs = [0] * 32
e.intregs[1] = 1
e.intregs[2] = 0x8000_0000_0000_0000
e.intregs[3] = min(e.intregs[1], e.intregs[2])
- e.crregs[0] = 0x4
+ e.crregs[0] = 0x8 # r1 <u r2
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
def case_0_avgadd(self):
projects / openpower-isa.git / commitdiff