class Pins:
def __init__(self, *identifiers):
- self.identifiers = identifiers
+ self.identifiers = []
+ for i in identifiers:
+ self.identifiers += i.split()
class IOStandard:
def __init__(self, name):
("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
- Subsignal("a", Pins("P2", "N5", "N6", "M8", "P8", "T7", "N8", "T6",
- "R1", "P1", "N2", "N1", "L4")),
- Subsignal("ba", Pins("M7", "M6")),
+ Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")),
+ Subsignal("ba", Pins("M7 M6")),
Subsignal("cs_n", Pins("P6")),
Subsignal("cke", Pins("L7")),
Subsignal("ras_n", Pins("L2")),
Subsignal("cas_n", Pins("L1")),
Subsignal("we_n", Pins("C2")),
- Subsignal("dq", Pins("G2", "G1", "L8", "K5", "K2", "J2", "J1", "R7",
- "T4", "T2", "T3", "R3", "R5", "P3", "N3", "K1")),
+ Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")),
Subsignal("dqm", Pins("R6","T5")),
IOStandard("3.3-V LVTTL")
),
),
("gpio_0", 0,
- Pins("D3", "C3", "A2", "A3", "B3", "B4", "A4", "B5",
- "A5", "D5", "B6", "A6", "B7", "D6", "A7", "C6",
- "C8", "E6", "E7", "D8", "E8", "F8", "F9", "E9",
- "C9", "D9", "E11", "E10", "C11", "B11", "A12", "D11",
- "D12", "B12"),
+ Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6",
+ "C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11",
+ "D12 B12"),
IOStandard("3.3-V LVTTL")
),
("gpio_1", 0,
- Pins("F13", "T15", "T14", "T13", "R13", "T12", "R12", "T11",
- "T10", "R11", "P11", "R10", "N12", "P9", "N9", "N11",
- "L16", "K16", "R16", "L15", "P15", "P16", "R14", "N16",
- "N15", "P14", "L14", "N14", "M10", "L13", "J16", "K15",
- "J13", "J14"),
+ Pins("F13 T15 T14 T13 R13 T12 R12 T11 T10 R11 P11 R10 N12 P9 N9 N11",
+ "L16 K16 R16 L15 P15 P16 R14 N16 N15 P14 L14 N14 M10 L13 J16 K15",
+ "J13 J14"),
IOStandard("3.3-V LVTTL")
),
("gpio_2", 0,
- Pins("A14", "B16", "C14", "C16", "C15", "D16", "D15", "D14",
- "F15", "F16", "F14", "G16", "G15"),
+ Pins("A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15"),
IOStandard("3.3-V LVTTL")
),
]
Subsignal("det", Pins("AA21")),
Subsignal("cmd", Pins("AB22")),
Subsignal("clk", Pins("AB23")),
- Subsignal("dat", Pins("AC20", "AA23", "AA22", "AC21")),
+ Subsignal("dat", Pins("AC20 AA23 AA22 AC21")),
IOStandard("LVCMOS25")),
("lcd", 0,
- Subsignal("db", Pins("AA13", "AA10", "AA11", "Y10")),
+ Subsignal("db", Pins("AA13 AA10 AA11 Y10")),
Subsignal("e", Pins("AB10")),
Subsignal("rs", Pins("Y11")),
Subsignal("rw", Pins("AB13")),
IOStandard("LVCMOS25")),
("hdmi", 0,
- Subsignal("d", Pins("B23", "A23", "E23", "D23",
- "F25", "E25", "E24", "D24",
- "F26", "E26", "G23", "G24",
- "J19", "H19", "L17", "L18",
- "K19", "K20")),
+ Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")),
Subsignal("de", Pins("H17")),
Subsignal("clk", Pins("K18")),
Subsignal("vsync", Pins("H20")),
# the flash reset to be released before the system reset.
("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)),
("norflash", 0,
- Subsignal("adr", Pins("L22", "L20", "K22", "K21", "J19", "H20", "F22",
- "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
- "G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19")),
- Subsignal("d", Pins("AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
- "AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"), Misc("PULLDOWN")),
+ Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22",
+ "F21 K17 J17 E22 E20 H18 H19 F20",
+ "G19 C22 C20 D22 D21 F19 F18 D20 D19")),
+ Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7",
+ "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")),
Subsignal("oe_n", Pins("M22")),
Subsignal("we_n", Pins("N20")),
Subsignal("ce_n", Pins("M21")),
IOStandard("SSTL2_I")
),
("ddram", 0,
- Subsignal("a", Pins("B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
- "G6", "C1", "C3", "D1", "D2")),
- Subsignal("ba", Pins("A2", "E6")),
+ Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")),
+ Subsignal("ba", Pins("A2 E6")),
Subsignal("cs_n", Pins("F7")),
Subsignal("cke", Pins("G7")),
Subsignal("ras_n", Pins("E5")),
Subsignal("cas_n", Pins("C4")),
Subsignal("we_n", Pins("D3")),
- Subsignal("dq", Pins("Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
- "U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
- "M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1")),
- Subsignal("dm", Pins("E1", "E3", "F3", "G4")),
- Subsignal("dqs", Pins("F1", "F2", "H5", "H6")),
+ Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3",
+ "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4",
+ "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")),
+ Subsignal("dm", Pins("E1 E3 F3 G4")),
+ Subsignal("dqs", Pins("F1 F2 H5 H6")),
IOStandard("SSTL2_I")
),
Subsignal("rst_n", Pins("R22")),
Subsignal("dv", Pins("V21")),
Subsignal("rx_er", Pins("V22")),
- Subsignal("rx_data", Pins("U22", "U20", "T22", "T21")),
+ Subsignal("rx_data", Pins("U22 U20 T22 T21")),
Subsignal("tx_en", Pins("N19")),
Subsignal("tx_er", Pins("M19")),
- Subsignal("tx_data", Pins("M16", "L15", "P19", "P20")),
+ Subsignal("tx_data", Pins("M16 L15 P19 P20")),
Subsignal("col", Pins("W20")),
Subsignal("crs", Pins("W22")),
IOStandard("LVCMOS33")
("vga_clock", 0, Pins("A11"), IOStandard("LVCMOS33")),
("vga", 0,
- Subsignal("r", Pins("C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9")),
- Subsignal("g", Pins("C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10")),
- Subsignal("b", Pins("D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14")),
+ Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")),
+ Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")),
+ Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")),
Subsignal("hsync_n", Pins("A14")),
Subsignal("vsync_n", Pins("C15")),
Subsignal("psave_n", Pins("B14")),
("mmc", 0,
Subsignal("clk", Pins("A10")),
Subsignal("cmd", Pins("B18")),
- Subsignal("dat", Pins("A18", "E16", "C17", "A17")),
+ Subsignal("dat", Pins("A18 E16 C17 A17")),
IOStandard("LVCMOS33")
),
Subsignal("rst_n", Pins("AH13")),
Subsignal("dv", Pins("AM13")),
Subsignal("rx_er", Pins("AG12")),
- Subsignal("rx_data", Pins("AN13", "AF14", "AE14", "AN12", "AM12", "AD11", "AC12", "AC13")),
+ Subsignal("rx_data", Pins("AN13 AF14 AE14 AN12 AM12 AD11 AC12 AC13")),
Subsignal("tx_en", Pins("AJ10")),
Subsignal("tx_er", Pins("AH10")),
- Subsignal("tx_data", Pins("AM11", "AL11", "AG10", "AG11", "AL10", "AM10", "AE11", "AF11")),
+ Subsignal("tx_data", Pins("AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11")),
Subsignal("col", Pins("AK13")),
Subsignal("crs", Pins("AL13")),
IOStandard("LVCMOS25")
("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
("sdram", 0,
- Subsignal("a", Pins("P140", "P139", "P138", "P137", "P46", "P45", "P44",
- "P43", "P41", "P40", "P141", "P35", "P34")),
- Subsignal("ba", Pins("P143", "P142")),
+ Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44",
+ "P43 P41 P40 P141 P35 P34")),
+ Subsignal("ba", Pins("P143 P142")),
Subsignal("cs_n", Pins("P1")),
Subsignal("cke", Pins("P33")),
Subsignal("ras_n", Pins("P2")),
Subsignal("cas_n", Pins("P5")),
Subsignal("we_n", Pins("P6")),
- Subsignal("dq", Pins("P9", "P10", "P11", "P12", "P14", "P15", "P16", "P8",
- "P21", "P22", "P23", "P24", "P26", "P27", "P29", "P30")),
- Subsignal("dm", Pins("P7", "P17")),
+ Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")),
+ Subsignal("dm", Pins("P7 P17")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
]
("gpmc", 0,
Subsignal("clk", Pins("R26")),
- Subsignal("a", Pins("N17", "N18", "L23", "L24", "N19", "N20", "N21", "N22", "P17", "P19")),
- Subsignal("d", Pins("N23", "N24", "R18", "R19", "P21", "P22", "R20", "R21", "P24", "P26", "R23", "R24", "T22", "T23", "U23", "R25")),
+ Subsignal("a", Pins("N17 N18 L23 L24 N19 N20 N21 N22 P17 P19")),
+ Subsignal("d", Pins("N23 N24 R18 R19 P21 P22 R20 R21 P24 P26 R23 R24 T22 T23 U23 R25")),
Subsignal("we_n", Pins("W26")),
Subsignal("oe_n", Pins("AA25")),
Subsignal("ale_n", Pins("AA26")),
Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33"))
),
("ti_dac", 0, # DAC3283
- Subsignal("dat_p", Pins("AA10", "AA9", "V11", "Y11", "W14", "Y12", "AD14", "AE13"), IOStandard("LVDS_25")),
- Subsignal("dat_n", Pins("AB11", "AB9", "V10", "AA11", "Y13", "AA12", "AF14", "AF13"), IOStandard("LVDS_25")),
+ Subsignal("dat_p", Pins("AA10 AA9 V11 Y11 W14 Y12 AD14 AE13"), IOStandard("LVDS_25")),
+ Subsignal("dat_n", Pins("AB11 AB9 V10 AA11 Y13 AA12 AF14 AF13"), IOStandard("LVDS_25")),
Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")),
Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")),
Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25"))
),
("ti_adc", 0, # ADS62P49
- Subsignal("dat_a_p", Pins("AB14", "Y21", "W20", "AB22", "V18", "W17", "AA21")),
- Subsignal("dat_a_n", Pins("AC14", "AA22", "Y20", "AC22", "W19", "W18", "AB21")),
- Subsignal("dat_b_p", Pins("Y17", "U15", "AA19", "W16", "AA18", "Y15", "V14")),
- Subsignal("dat_b_n", Pins("AA17", "V16", "AB19", "Y16", "AB17", "AA16", "V15")),
+ Subsignal("dat_a_p", Pins("AB14 Y21 W20 AB22 V18 W17 AA21")),
+ Subsignal("dat_a_n", Pins("AC14 AA22 Y20 AC22 W19 W18 AB21")),
+ Subsignal("dat_b_p", Pins("Y17 U15 AA19 W16 AA18 Y15 V14")),
+ Subsignal("dat_b_n", Pins("AA17 V16 AB19 Y16 AB17 AA16 V15")),
IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
),
("fmc150_clocks", 0,
("epb", 0,
Subsignal("cs_n", Pins("K13")),
Subsignal("r_w_n", Pins("AF20")),
- Subsignal("be_n", Pins("AF14", "AF18")),
+ Subsignal("be_n", Pins("AF14 AF18")),
Subsignal("oe_n", Pins("AF21")),
- Subsignal("addr", Pins("AE23", "AE22", "AG18", "AG12", "AG15", "AG23", "AF19", "AE12", "AG16", "AF13", "AG20", "AF23",
- "AH17", "AH15", "L20", "J22", "H22", "L15", "L16", "K22", "K21", "K16", "J15")),
- Subsignal("addr_gp", Pins("L21", "G22", "K23", "K14", "L14", "J12")),
- Subsignal("data", Pins("AF15", "AE16", "AE21", "AD20", "AF16", "AE17", "AE19", "AD19", "AG22", "AH22", "AH12", "AG13",
- "AH20", "AH19", "AH14", "AH13")),
+ Subsignal("addr", Pins("AE23 AE22 AG18 AG12 AG15 AG23 AF19 AE12 AG16 AF13 AG20 AF23",
+ "AH17 AH15 L20 J22 H22 L15 L16 K22 K21 K16 J15")),
+ Subsignal("addr_gp", Pins("L21 G22 K23 K14 L14 J12")),
+ Subsignal("data", Pins("AF15 AE16 AE21 AD20 AF16 AE17 AE19 AD19 AG22 AH22 AH12 AG13",
+ "AH20 AH19 AH14 AH13")),
Subsignal("rdy", Pins("K12")),
IOStandard("LVCMOS33")
),
projects / litex.git / commitdiff