verilog: improve specify support when not in -specify mode

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index f37c6d99b9d3068fce97d2e75e29cba68c938f8b..155de8f90417e6e7b52844e2811f5db3f2e1a7c0 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1043,7 +1043,7 @@ list_of_specparam_assignments:
        specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
 
 specparam_assignment:
-       ignspec_id '=' constant_mintypmax_expression ;
+       ignspec_id '=' ignspec_expr ;
 
 ignspec_opt_cond:
        TOK_IF '(' ignspec_expr ')' | /* empty */;
@@ -1060,13 +1060,15 @@ simple_path_declaration :
        ;
 
 path_delay_value :
-       '(' path_delay_expression list_of_path_delay_extra_expressions ')'
-       |     path_delay_expression
-       |     path_delay_expression list_of_path_delay_extra_expressions
+       '(' ignspec_expr list_of_path_delay_extra_expressions ')'
+       |     ignspec_expr
+       |     ignspec_expr list_of_path_delay_extra_expressions
        ;
 
 list_of_path_delay_extra_expressions :
-       ',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
+       ',' ignspec_expr
+       | ',' ignspec_expr list_of_path_delay_extra_expressions
+       ;
 
 specify_edge_identifier :
        TOK_POSEDGE | TOK_NEGEDGE ;
@@ -1120,14 +1122,6 @@ system_timing_args :
        system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
        system_timing_args ',' system_timing_arg ;
 
-path_delay_expression :
-       ignspec_constant_expression;
-
-constant_mintypmax_expression :
-       ignspec_constant_expression
-       | ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression
-       ;
-
 // for the time being this is OK, but we may write our own expr here.
 // as I'm not sure it is legal to use a full expr here (probably not)
 // On the other hand, other rules requiring constant expressions also use 'expr'

diff --git a/tests/various/specify.v b/tests/various/specify.v
index aa8aca4bcd80c3d2fc271f7273587266e129ec18..5655ded21aa57fe573fb7ffa4526b26093e3e268 100644 (file)
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,11 +7,9 @@ module test (
                if (EN) Q <= D;
 
        specify
-`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
                if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
                $setup(D, posedge CLK &&& EN, 5);
                $hold(posedge CLK, D &&& EN, 6);
-`endif
        endspecify
 endmodule
 

diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 00597e1e282c9d0ae7367b235d7cc606faec0934..a2b6038e47e81f95701e4a55c4aaa3ffb600acda 100644 (file)
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,4 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
+read_verilog specify.v