Revert "In sat: 'x' in init attr should not override constant"

This reverts commit 2b37a093e95036b267481b2dae2046278eef4040.

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index bcc690fa3817f553ac8c8ffa84f8ca87d34689e0..dd56d8c71197d0e4f80952e92b6d352b37f2e2d2 100644 (file)
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -268,8 +268,6 @@ struct SatHelper
                                RTLIL::SigSpec removed_bits;
                                for (int i = 0; i < lhs.size(); i++) {
                                        RTLIL::SigSpec bit = lhs.extract(i, 1);
-                                       if (bit.is_fully_const() && rhs[i] == State::Sx)
-                                               rhs[i] = bit;
                                        if (!satgen.initial_state.check_all(bit)) {
                                                removed_bits.append(bit);
                                                lhs.remove(i, 1);

diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index d46ccae484ae4a779a757e11f080b6a52c25d859..5b661f8d6a0488c6e453cffa7f1a1db1632ab9d1 100644 (file)
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,7 +1,6 @@
 module test(input clk, input [3:0] bar, output [3:0] foo);
   reg [3:0] foo = 0;
   reg [3:0] last_bar = 0;
-  reg [3:0] asdf = 4'b1xxx;
 
   always @*
     foo[1:0] <= bar[1:0];
@@ -12,8 +11,5 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
   always @(posedge clk)
     last_bar <= bar;
 
-  always @*
-    asdf[2:0] <= 3'b111;
-
   assert property (foo == {last_bar[3:2], bar[1:0]});
 endmodule

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 3d88aa971dcecba1514a623a31e010ff04baa3dc..2079d2f34e13971cd336cb50372e14baace6b9e9 100644 (file)
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -1,4 +1,4 @@
 read_verilog -sv initval.v
-proc;
+proc;;
 
 sat -seq 10 -prove-asserts