anv: Stall before fast-clear operations

During initial CCS bring-up, I discovered that you have to do a full CS
stall prior to doing a CCS resolve as well as afterwards.  It appears
that the same is needed for fast-clears as well.  This fixes rendering
corruptions on The Talos Principle on Sky Lake GT4.  The issue hasn't
been demonstrated on any other hardware however, given that this appears
to be a "too many things in the pipe" problem, having it be easier to
reproduce on a system with more EUs makes sense.  The issues with
resolves is demonstrable on a GT3 or GT2 so this is probably also a
problem on all GTs.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 05790d268cb7a80cd3d108e7711f9bd25a90e321..8de339cf09e08063edef8842d7d948cb73443478 100644 (file)
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1206,6 +1206,25 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
       if (att_state->fast_clear) {
          surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
 
+         /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
+          *
+          *    "After Render target fast clear, pipe-control with color cache
+          *    write-flush must be issued before sending any DRAW commands on
+          *    that render target."
+          *
+          * This comment is a bit cryptic and doesn't really tell you what's
+          * going or what's really needed.  It appears that fast clear ops are
+          * not properly synchronized with other drawing.  This means that we
+          * cannot have a fast clear operation in the pipe at the same time as
+          * other regular drawing operations.  We need to use a PIPE_CONTROL
+          * to ensure that the contents of the previous draw hit the render
+          * target before we resolve and then use a second PIPE_CONTROL after
+          * the resolve to ensure that it is completed before any additional
+          * drawing occurs.
+          */
+         cmd_buffer->state.pending_pipe_bits |=
+            ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+
          blorp_fast_clear(&batch, &surf, iview->isl.format,
                           iview->isl.base_level,
                           iview->isl.base_array_layer, fb->layers,
@@ -1213,12 +1232,6 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
                           render_area.offset.x + render_area.extent.width,
                           render_area.offset.y + render_area.extent.height);
 
-         /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
-          *
-          *    "After Render target fast clear, pipe-control with color cache
-          *    write-flush must be issued before sending any DRAW commands on
-          *    that render target."
-          */
          cmd_buffer->state.pending_pipe_bits |=
             ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
       } else {