operands[2] = gen_reg_rtx (DImode);
operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
operands[4] = rs6000_immed_double_const (0, 0x43300000, DImode);
- operands[5] = force_reg (DFmode, rs6000_immed_double_const (0x43300000,
- 0x80000000,
- DFmode));
+ operands[5] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
}")
(define_expand "floatunssidf2"
{
operands[2] = gen_reg_rtx (DImode);
operands[3] = rs6000_immed_double_const (0, 0x43300000, DImode);
- operands[4] = force_reg (DFmode, rs6000_immed_double_const (0x43300000, 0, DFmode));
+ operands[4] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
}")
;; For the above two cases, we always split.
""
"
{
+ if (GET_CODE (operands[0]) == MEM)
+ operands[1] = force_reg (DImode, operands[1]);
+
if (GET_CODE (operands[1]) == CONST_DOUBLE
|| GET_CODE (operands[1]) == CONST_INT)
{
- emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
- operand_subword (operands[1], 0, 0, DImode));
- emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
- operand_subword (operands[1], 1, 0, DImode));
+ HOST_WIDE_INT low;
+ HOST_WIDE_INT high;
+
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ low = CONST_DOUBLE_LOW (operands[1]);
+ high = CONST_DOUBLE_HIGH (operands[1]);
+ }
+ else
+ {
+ low = INTVAL (operands[1]);
+ high = (low < 0) ? ~0 : 0;
+ }
+
+ emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN),
+ GEN_INT (low));
+
+ emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], !WORDS_BIG_ENDIAN),
+ GEN_INT (high));
DONE;
}
- if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (DImode, operands[1]);
-
/* Stores between FPR and any non-FPR registers must go through a
temporary stack slot. */