/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2015 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
Tick
PioPort::recvAtomic(PacketPtr pkt)
{
- // @todo: We need to pay for this and not just zero it out
+ // technically the packet only reaches us after the header delay,
+ // and typically we also need to deserialise any payload
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
const Tick delay(pkt->isRead() ? device->read(pkt) : device->write(pkt));
assert(pkt->isResponse() || pkt->isError());
- return delay;
+ return delay + receive_delay;
}
AddrRangeList
/*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
{
assert(pkt->getAddr() >= configAddr &&
pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
- // @todo someone should pay for this
+
+ // technically the packet only reaches us after the header delay,
+ // and typically we also need to deserialise any payload
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
- return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
+
+ const Tick delay(pkt->isRead() ? device->readConfig(pkt) :
+ device->writeConfig(pkt));
+ return delay + receive_delay;
}
AddrRangeList
DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
- // @todo: We need to pay for this and not just zero it out
+ // technically the packet only reaches us after the header delay,
+ // and typically we also need to deserialise any payload (unless
+ // the two sides of the bridge are synchronous)
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
- slavePort.schedTimingResp(pkt, bridge.clockEdge(delay));
+ slavePort.schedTimingResp(pkt, bridge.clockEdge(delay) +
+ receive_delay);
return true;
}
}
if (!retryReq) {
- // @todo: We need to pay for this and not just zero it out
+ // technically the packet only reaches us after the header
+ // delay, and typically we also need to deserialise any
+ // payload (unless the two sides of the bridge are
+ // synchronous)
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
- masterPort.schedTimingReq(pkt, bridge.clockEdge(delay));
+ masterPort.schedTimingReq(pkt, bridge.clockEdge(delay) +
+ receive_delay);
}
}
/*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
return false;
}
- // @todo someone should pay for this
+ // technically the packet only reaches us after the header delay,
+ // and since this is a memory controller we also need to
+ // deserialise the payload before performing any write operation
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
// update the release time according to the bandwidth limit, and
// recvAtomic() should already have turned packet into
// atomic response
assert(pkt->isResponse());
- // to keep things simple (and in order), we put the packet at
- // the end even if the latency suggests it should be sent
- // before the packet(s) before it
- packetQueue.emplace_back(pkt, curTick() + getLatency());
+
+ Tick when_to_send = curTick() + receive_delay + getLatency();
+
+ // typically this should be added at the end, so start the
+ // insertion sort with the last element, also make sure not to
+ // re-order in front of some existing packet with the same
+ // address, the latter is important as this memory effectively
+ // hands out exclusive copies (shared is not asserted)
+ auto i = packetQueue.end();
+ --i;
+ while (i != packetQueue.begin() && when_to_send < i->tick &&
+ i->pkt->getAddr() != pkt->getAddr())
+ --i;
+
+ // emplace inserts the element before the position pointed to by
+ // the iterator, so advance it one step
+ packetQueue.emplace(++i, pkt, when_to_send);
+
if (!retryResp && !dequeueEvent.scheduled())
schedule(dequeueEvent, packetQueue.back().tick);
} else {
#ifndef __SIMPLE_MEMORY_HH__
#define __SIMPLE_MEMORY_HH__
-#include <deque>
+#include <list>
#include "mem/abstract_mem.hh"
#include "mem/port.hh"
* actual memory access. Note that this is where the packet spends
* the memory latency.
*/
- std::deque<DeferredPacket> packetQueue;
+ std::list<DeferredPacket> packetQueue;
/**
* Bandwidth in ticks per byte. The regulation affects the