add PACK/UNPACK Mode descriptions to power_svp64_rm.py

(update comments, first) and add new PACK mode to SVP64RMMode
in poewr_enums.py

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 9ef7b1910daaf572855bc0522a532ac80a3cd04a..03333548b4ffb343e87bcd8dd3a5463f56df9829 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -197,6 +197,7 @@ class SVP64RMMode(Enum):
     SATURATE = 3
     PREDRES = 4
     BRANCH = 5
+    PACK = 6
 
 
 @unique

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 02c459bc7c1b3d5ea2ed983270a7edb6be43095c..4f6d65c35a9d02a4de1e2796290fc18ea4ecc460 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -47,11 +47,11 @@ https://libre-soc.org/openpower/sv/ldst/
 https://libre-soc.org/openpower/sv/branches/
 
 LD/ST immed:
-00     0       dz els  normal mode (with element-stride)
-00     1       dz rsvd bit-reversed mode
+00     0       zz els  normal mode (with element-stride option)
+00     1       zz els  Pack/unpack (with element-stride option)
 01     inv     CR-bit  Rc=1: ffirst CR sel
 01     inv     els RC1 Rc=0: ffirst z/nonz
-10     N       dz els  sat mode: N=0/1 u/s
+10     N       zz els  sat mode: N=0/1 u/s
 11     inv     CR-bit  Rc=1: pred-result CR sel
 11     inv     els RC1 Rc=0: pred-result z/nonz
 
@@ -62,17 +62,19 @@ LD/ST indexed:
 01     inv     dz RC1  Rc=0: ffirst z/nonz
 10     N       sz dz   sat mode: N=0/1 u/s
 11     inv     CR-bit  Rc=1: pred-result CR sel
-11     inv     dz RC1  Rc=0: pred-result z/nonz
+11     inv     zz RC1  Rc=0: pred-result z/nonz
 
 Arithmetic:
-00     0       sz dz   normal mode
-00     1       dz CRM  reduce mode (mapreduce), SUBVL=1
-00     1       SVM CRM subvector reduce mode, SUBVL>1
-01     inv     CR-bit  Rc=1: ffirst CR sel
-01     inv     dz RC1  Rc=0: ffirst z/nonz
-10     N       sz dz   sat mode: N=0/1 u/s
-11     inv     CR-bit  Rc=1: pred-result CR sel
-11     inv     dz RC1  Rc=0: pred-result z/nonz
+00     0   dz sz       normal mode
+00     1   0 RG        scalar reduce mode (mapreduce), SUBVL=1
+00     1   1 /         parallel reduce mode (mapreduce), SUBVL=1
+00     1   SVM 0       subvector reduce mode, SUBVL>1
+00     1   SVM 1       Pack/Unpack mode, SUBVL>1
+01     inv CR-bit      Rc=1: ffirst CR sel
+01     inv VLi RC1     Rc=0: ffirst z/nonz
+10     N   dz sz       sat mode: N=0/1 u/s
+11     inv CR-bit      Rc=1: pred-result CR sel
+11     inv zz RC1      Rc=0: pred-result z/nonz 
 
 Branch Conditional:
 note that additional BC modes are in *other bits*, specifically
@@ -118,6 +120,7 @@ class SVP64RMModeDecode(Elaboratable):
         self.pred_sz = Signal(1) # predicate source zeroing
         self.pred_dz = Signal(1) # predicate dest zeroing
 
+        # Modes n stuff
         self.saturate = Signal(SVP64sat)
         self.RC1 = Signal()
         self.cr_sel = Signal(2)  # bit of CR to test (index 0-3)