cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index a15c2ec19677c335e75658d87380e0443a71a6d8..ed07b8716c34b892bb2bebbac2d2bc1c41f8d0f5 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -64,7 +64,7 @@ class XilinxClocking(Module, AutoCSR):
         config = {}
         for divclk_divide in range(*self.divclk_divide_range):
             config["divclk_divide"] = divclk_divide
-            for clkfbout_mult in range(*self.clkfbout_mult_frange):
+            for clkfbout_mult in reversed(range(*self.clkfbout_mult_frange)):
                 all_valid = True
                 vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide
                 (vco_freq_min, vco_freq_max) = self.vco_freq_range